A power device

Abstract

The present disclosure provides a power device including a transistor and a clamping driving circuit. The clamping driving circuit is configured to: receive a first voltage from a first pin of the power device; receive a second voltage from a second pin of the power device; generate a gate driving voltage to a gate of the transistor based on the first voltage when the first voltage is higher than the second voltage; generate the gate driving voltage to the gate of the transistor based on the second voltage when the first voltage is lower than the second voltage; and generate the gate driving voltage to the gate of the transistor based on the first voltage or the second voltage when the first voltage is equal to the second voltage. The clamping driving circuit can handle and effectively utilize a wide range of input voltages, without an additional power pin to provide a normal accurate driving voltage to drive the transistor, ensuring that the transistor can exert its optimal switching performance. Moreover, the power device only needs a three-pin package, has good heat dissipation performance, high reliability, and greatly facilitates subsequent PCB packaging.

Description

Technical Field

[0001] This application generally relates to a power device, and more specifically, to a three-pin packaged integrated power device comprising an enhancement-mode gallium nitride (GaN) transistor and clamping drive circuitry. Background Technology

[0002] GaN semiconductor devices (e.g., high electron mobility field-effect transistors (HEMTs)) are widely used as power devices because they have advantages such as low power loss and fast switching speed compared to silicon (Si) semiconductor devices (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)).

[0003] Due to the low gate breakdown voltage of enhancement-mode GaN HEMTs, power devices based on GaN HEMTs generally require both a regulated power supply and a driver circuit. Current GaN power device packages include discrete devices, integrated circuits (ICs), and intelligent power modules (IPMs). The advantage of discrete device packages is their similarity to the driver structure of existing Si power devices, allowing the use of existing packaging equipment. However, discrete GaN power devices require a highly precise regulated power supply and have larger parasitic parameters, making the driver loop prone to ringing. When using IC packages, optimal switching performance can be achieved because the driver loop and the regulated LDO control the drive voltage are internal to the chip. However, IC packages have more pins, generally requiring surface-mount packages with many pins such as QFN, PSOP, and SOIC. Furthermore, the thermal design of these packages is more complex, and their reliability is generally lower than that of discrete packages. Summary of the Invention

[0004] One objective of this application is to provide a three-pin packaged integrated power device that includes an enhanced gallium nitride (GaN) transistor and clamping drive circuitry.

[0005] According to one aspect of this application, a power device is provided, comprising: a first pin, a second pin, and a third pin; an enhancement-mode gallium nitride transistor, wherein the drain of the transistor is electrically connected to the second pin, and the source of the transistor is electrically connected to the third pin; and a clamping drive circuit having a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the first terminal of the clamping drive circuit is connected to the first pin, the second terminal of the clamping drive circuit is connected to the second pin, the third terminal of the clamping drive circuit is connected to the third pin, and the fourth terminal of the clamping drive circuit is connected to the gate of the transistor. The clamping drive circuit is configured to receive a first voltage V from the first pin. IN1 ; Receive the second voltage V from the second pin IN2When the first voltage V IN1 Higher than the second voltage V IN2 At that time, based on the first voltage V IN1 Generate gate drive voltage V G To the gate of the transistor; when the first voltage V IN1 Below the second voltage V IN2 At that time, based on the second voltage V IN2 Generate the gate drive voltage V G To the gate of the transistor; and when the first voltage V IN1 Equal to the second voltage V IN2 At that time, based on the first voltage V IN1 Or the second voltage V IN2 Generate the gate drive voltage V G To the gate of the transistor.

[0006] The clamping drive circuit in the power device provided by this invention can handle and effectively utilize a wide range of input voltages V. IN1 and V IN2 (Up to 700V), no additional power supply pin is required to provide a normal and accurate drive voltage V G This drives the transistor, ensuring that the transistor can perform at its optimal switching performance. Moreover, the power device only requires a three-pin package, has good heat dissipation, high reliability, and greatly simplifies subsequent circuit board packaging. Attached Figure Description

[0007] The following detailed description is read in conjunction with the accompanying drawings for an easy understanding of various aspects of this disclosure. It should be noted that the various features may not be drawn to scale. That is, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Embodiments of this disclosure are described in more detail below with reference to the drawings, in which:

[0008] Figure 1 A circuit block diagram of a power device according to some embodiments of the present invention is shown.

[0009] Figure 2 A circuit diagram of a clamping voltage regulator circuit according to some embodiments of the present invention is shown.

[0010] Figure 3 A circuit diagram of a gate drive circuit according to some embodiments of the present invention is shown.

[0011] Figure 4 A circuit diagram of an inverter according to some embodiments of the present invention is shown.

[0012] Figure 5 A circuit diagram of a gate drive circuit according to some other embodiments of the present invention is shown.

[0013] Figure 6 Circuit block diagrams of power devices according to other embodiments of the present invention are depicted.

[0014] Figure 7 A circuit diagram of a clamping voltage regulator circuit according to some embodiments of the present invention is shown.

[0015] Figure 8 A circuit diagram of a gate drive circuit 62-1 according to another embodiment of the present invention is shown.

[0016] Figure 9 Circuit diagrams of inverters according to other embodiments of the present invention are shown.

[0017] Figure 10 A circuit diagram of a gate drive circuit 62-2 according to another embodiment of the present invention is shown.

[0018] Figure 11 The following diagram shows various signal waveforms of a power controller according to an embodiment of the present invention. Detailed Implementation

[0019] In the following description, embodiments of a controller for controlling a gallium nitride semiconductor device are set forth as preferred examples according to this application. Those skilled in the art will understand that modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring the invention; however, this disclosure is prepared to enable those skilled in the art to practice the teachings herein without engaging in undue experimentation.

[0020] Figure 1 A circuit block diagram of a power device according to some embodiments of the present invention is shown. (Reference) Figure 1 The power device 1 has a first pin 1A, a second pin 1B, and a third pin 1C. The power device 1 includes a clamping drive circuit 10 and an enhancement gallium nitride transistor 20.

[0021] Transistor 20 has a gate G, a source S, and a drain D. The drain D is electrically connected to the second pin 1B, and the source S is electrically connected to the third pin 1C.

[0022] The clamping drive circuit 10 has a first terminal 10A, a second terminal 10B, a third terminal 10C, and a fourth terminal 10D. The first terminal 10A is connected to the first pin 1A. The second terminal 10B is connected to the second pin 1B. The third terminal 10C is connected to the third pin 1C. The fourth terminal 10D is connected to the gate G of the transistor 20.

[0023] The clamping drive circuit 10 is configured to receive a first voltage V from the first pin 1A.IN1 Receive the second voltage V from the second pin 1B IN2 When the first voltage V IN1 Higher than the second voltage V IN2 At that time, based on the first voltage V IN1 Generate driving voltage V G To the gate G of transistor 20; when the first voltage V IN1 Below the second voltage V IN2 At that time, based on the second voltage V IN2 Generate gate drive voltage V G to the gate G of transistor 20; and when the first voltage V IN1 Equal to the second voltage V IN2 At that time, based on the first voltage V IN1 Or the second voltage V IN2 Generate gate drive voltage V G To the gate G of transistor 20.

[0024] The clamping drive circuit 10 includes a clamping voltage regulator circuit 11 and a gate drive circuit 12.

[0025] The clamping voltage regulator circuit 11 has a first terminal 11A, a second terminal 11B, a third terminal 11C, and a fourth terminal 11D. The first terminal 11A is connected to the first terminal 10A of the clamping drive circuit 10. The second terminal 11B is connected to the second terminal 10B of the clamping drive circuit 10. The third terminal 11C is connected to the third terminal 10C of the clamping drive circuit 10.

[0026] The gate drive circuit 12 has a first terminal 12A, a second terminal 12B, a third terminal 12C, and a fourth terminal 12D. The first terminal 12A is connected to the first terminal 10A of the clamp drive circuit 10, the second terminal 12B of the gate drive circuit 12 is connected to the fourth terminal 10D of the clamp drive circuit 10, the third terminal 12C of the gate drive circuit 12 is connected to the third terminal 10C of the clamp drive circuit 10, and the fourth terminal 12D of the gate drive circuit 12 is connected to the fourth terminal 11D of the clamp voltage regulator circuit 11.

[0027] The clamping voltage regulator circuit 11 is configured to receive a first voltage V from the first terminal 10A of the clamping drive circuit 10. IN1 The second voltage V is received from the second terminal 10B of the clamping drive circuit 10. IN2 When the first voltage V IN1 Higher than the second voltage V IN2 At that time, based on the first voltage V IN1 Generating operating voltage V DD To the fourth terminal 12D of the gate drive circuit 12; when the first voltage V IN1 Below the second voltage V IN2 At that time, based on the second voltage V IN2Generating operating voltage V DD To the fourth terminal 12D of the gate drive circuit 12; and when the first voltage V IN1 Equal to the second voltage V IN2 At that time, based on the first voltage V IN1 Or the second voltage V IN2 Generating operating voltage V DD To the fourth terminal 12D of the gate drive circuit 12.

[0028] The gate drive circuit 12 is configured to receive a first voltage V from the first terminal 10A of the clamp drive circuit 10. IN1 The operating voltage V is received from the fourth terminal 11D of the clamping voltage regulator circuit 11. DD ; and based on the first voltage V IN1 and operating voltage V DD Generate gate drive voltage V G .

[0029] Figure 2 A circuit diagram of a clamping voltage regulator circuit according to some embodiments of the present invention is shown. (Reference) Figure 2 The clamping voltage regulator circuit 11 includes a first diode D1, a second diode D2, a high-voltage junction field-effect transistor 111, a reference voltage regulator 112, an operational amplifier 113, a first voltage regulator transistor M1, a second voltage regulator transistor M2, a first resistor R1, and a second resistor R2.

[0030] The positive terminal of the first diode D1 is connected to the first terminal 11A of the clamping voltage regulator circuit 11.

[0031] The cathode of the second diode D2 is connected to the cathode of the first diode D1;

[0032] The high-voltage junction field-effect transistor 111 has a gate G, a drain D, and a source S. The drain D of the high-voltage junction field-effect transistor 111 is connected to the second terminal 11B of the clamping voltage regulator circuit 11, and the source S of the high-voltage junction field-effect transistor 111 is connected to the positive terminal of the second diode D2; the gate G of the high-voltage junction field-effect transistor 111 is connected to the third terminal 11C of the clamping voltage regulator circuit 11.

[0033] The reference regulator 112 has an input terminal 112A and an output terminal 112B. The input terminal 112A is connected to the negative terminal of the first diode D1 and the negative terminal of the second diode D2.

[0034] The positive input terminal of operational amplifier 113 is connected to the output terminal 112B of reference regulator 112.

[0035] The drain of the first Zener transistor M1 is connected to the input terminal 112A of the reference regulator 112, and the gate of the first Zener transistor M1 is connected to the output terminal of the operational amplifier 113.

[0036] The gate and drain of the second Zener transistor M2 are connected together to the fourth terminal 11D of the clamping voltage regulator circuit 11.

[0037] One end of the first resistor R1 is connected to the source of the second Zener transistor M2.

[0038] One end of the second resistor R2 is connected to the other end of the first resistor R1, and the other end of the second resistor R2 is connected to the third terminal 11C of the clamping voltage regulator circuit 11.

[0039] Figure 3 A circuit diagram of a gate drive circuit 12-1 according to some embodiments of the present invention is shown. (Refer to...) Figure 3 The gate drive circuit 12-1 includes a first drive transistor M3, a second drive transistor M4, an inverting Schmitt trigger 121, a buffer circuit 122, and an inverter 123.

[0040] The drain of the first driving transistor M3 is connected to the first terminal 12A of the gate driving circuit 12-1, and the source of the first driving transistor M3 is connected to the second terminal 12B of the gate driving circuit 12-1.

[0041] The drain of the second driving transistor M4 is connected to the second terminal 12B of the gate driving circuit 12-1, and the source of the second driving transistor M4 is connected to the third terminal 12C of the gate driving circuit 12-1.

[0042] The input terminal of the inverting Schmitt trigger 121 is connected to the first terminal 12A of the gate drive circuit 12-1.

[0043] The input of the buffer circuit 122 is connected to the output of the inverting Schmitt trigger 121. The buffer circuit 122 may include one or more buffers connected in series.

[0044] The input terminal 123A of inverter 123 is connected to the output terminal of the buffer circuit 122, and the output terminal 123B of inverter 123 is connected to the gate of the first driving transistor M3; the power supply terminal 123D of inverter 123 is connected to the fourth terminal 12D of the gate driving circuit 12-1; and the ground terminal 123C of inverter 123 is connected to the third terminal 12C of the gate driving circuit 12-1.

[0045] Figure 4 A circuit diagram of an inverter according to some embodiments of the present invention is shown. (Reference) Figure 4 The inverter 123 may include a pair of P-type transistors M P and N-type transistor M N P-type transistor M PThe gate of the N-type transistor is connected to the input terminal 123A of the inverter 123, the source is connected to the power supply terminal 123D of the inverter 123, and the drain is connected to the output terminal 123B of the inverter 123. N The gate of the inverter is connected to the input terminal 123A of the inverter 123, the source is connected to the ground terminal 123C of the inverter 123, and the drain is connected to the output terminal 123B of the inverter 123.

[0046] Figure 5 A circuit diagram of a gate drive circuit 12-2 according to other embodiments of the present invention is shown. The gate drive circuit 12-2 and... Figure 3 The gate drive circuit 12-1 is roughly the same as that in the previous version. For the sake of simplicity, it will be omitted here. Figure 3 and Figure 5 Identical or similar devices / parts will use the same reference numerals. Figure 5 Gate drive circuit 12-2 and Figure 3 The difference between the gate drive circuit 12-1 and the gate drive circuit 12-2 is that the gate drive circuit 12-2 also includes a third diode D3. The anode of the third diode D3 is connected to the first port 12A of the gate drive circuit 12-2, and the drain of the first drive transistor M3 is connected to the cathode of the third diode D3.

[0047] Figure 6 Circuit block diagrams of power devices according to other embodiments of the present invention are depicted. (Reference) Figure 6 The power device 6 has a first pin 6A, a second pin 6B, and a third pin 6C. The power device 6 includes a clamping drive circuit 60 and a transistor 20.

[0048] Transistor 20 has a gate G, a source S, and a drain D. The drain D is electrically connected to the second pin 6B, and the source S is electrically connected to the third pin 6C.

[0049] The clamping drive circuit 60 has a first terminal 60A, a second terminal 60B, a third terminal 60C, and a fourth terminal 60D. The first terminal 60A is connected to the first pin 6A. The second terminal 60B is connected to the second pin 6B. The third terminal 60C is connected to the third pin 6C. The fourth terminal 60D is connected to the gate G of the transistor 20.

[0050] The clamping drive circuit 60 is configured to receive a first voltage V from the first pin 6A. IN1 Receive the second voltage V from the second pin 6B IN2 When the first voltage V IN1 Higher than the second voltage V IN2 At that time, based on the first voltage V IN1 Generate driving voltage V G To the gate G of transistor 20; when the first voltage V IN1Below the second voltage V IN2 At that time, based on the second voltage V IN2 Generate gate drive voltage V G to the gate G of transistor 20; and when the first voltage V IN1 Equal to the second voltage V IN2 At that time, based on the first voltage V IN1 Or the second voltage V IN2 Generate gate drive voltage V G To the gate G of transistor 20.

[0051] The clamping drive circuit 60 includes a clamping voltage regulator circuit 61 and a gate drive circuit 62.

[0052] The clamping voltage regulator circuit 61 has a first terminal 61A, a second terminal 61B, a third terminal 61C, a fourth terminal 61D, and a fifth terminal 61E. The first terminal 61A is connected to the first terminal 60A of the clamping drive circuit 60. The second terminal 61B is connected to the second terminal 60B of the clamping drive circuit 60. The third terminal 61C is connected to the third terminal 60C of the clamping drive circuit 60.

[0053] The gate drive circuit 62 has a first terminal 62A, a second terminal 62B, a third terminal 62C, a fourth terminal 62D, and a fifth terminal 62E. The first terminal 62A is connected to the first terminal 60A of the clamp drive circuit 60, the second terminal 62B of the gate drive circuit 62 is connected to the fourth terminal 60D of the clamp drive circuit 60, the third terminal 62C of the gate drive circuit 62 is connected to the third terminal 60C of the clamp drive circuit 60, the fourth terminal 62D of the gate drive circuit 62 is connected to the fourth terminal 61D of the clamp voltage regulator circuit 61, and the fifth terminal 62E of the gate drive circuit 62 is connected to the fifth terminal 61E of the clamp voltage regulator circuit 61.

[0054] The clamping voltage regulator circuit 61 is configured to receive a first voltage V from the first terminal 60A of the clamping drive circuit 60. IN1 The second voltage V is received from the second terminal 60B of the clamping drive circuit 60. IN2 When the first voltage V IN1 Higher than the second voltage V IN2 At that time, based on the first voltage V IN1 Generating operating voltage V DD To the fourth terminal 62D of the gate drive circuit 62; when the first voltage V IN1 Below the second voltage V IN2 At that time, based on the second voltage V IN2 Generating operating voltage V DD To the fourth terminal 62D of the gate drive circuit 62; and when the first voltage V IN1 Equal to the second voltage V IN2 At that time, based on the first voltage V IN1 Or the second voltage VIN2 Generating operating voltage V DD To the fourth terminal 62D of the gate drive circuit 62 and the generated reference voltage V REF To the fifth terminal 62E of the gate drive circuit 62.

[0055] The gate drive circuit 62 is configured to receive a first voltage V from the first terminal 60A of the clamp drive circuit 60. IN1 The operating voltage V is received from the fourth terminal 60D of the clamping voltage regulator circuit 61. DD ; and based on the first voltage V IN1 Operating voltage V DD and reference voltage V REF Generate gate drive voltage V G .

[0056] Figure 7 A circuit diagram of a clamping voltage regulator circuit 61 according to some embodiments of the present invention is shown. (See reference) Figure 7 The clamping voltage regulator circuit 61 includes a first diode D1, a second diode D2, a high-voltage junction field-effect transistor 611, a reference voltage regulator 612, an operational amplifier 613, a first voltage regulator transistor M1, a second voltage regulator transistor M2, a first resistor R1, and a second resistor R2.

[0057] The positive terminal of the first diode D1 is connected to the first terminal 61A of the clamping voltage regulator circuit 61.

[0058] The cathode of the second diode D2 is connected to the cathode of the first diode D1;

[0059] The high-voltage junction field-effect transistor 611 has a gate G, a drain D, and a source S. The drain D of the high-voltage junction field-effect transistor 611 is connected to the second terminal 61B of the clamping voltage regulator circuit 61, and the source S of the high-voltage junction field-effect transistor 611 is connected to the positive terminal of the second diode D2; the gate G of the high-voltage junction field-effect transistor 611 is connected to the third terminal 61C of the clamping voltage regulator circuit 61.

[0060] The reference regulator 612 has an input terminal 612A and an output terminal 612B. The input terminal 612A is connected to the cathode of the first diode D1 and the cathode of the second diode D2, and the output terminal 612B is connected to the fifth terminal 61E of the clamping regulator circuit 60.

[0061] The positive input terminal of operational amplifier 613 is connected to the output terminal 612B of reference regulator 612.

[0062] The drain of the first Zener transistor M1 is connected to the input terminal 612A of the reference Zener 612, and the gate of the first Zener transistor M1 is connected to the output terminal of the comparator 613.

[0063] The gate and drain of the second Zener transistor M2 are connected together to the fourth terminal 61D of the clamping voltage regulator circuit 61.

[0064] One end of the first resistor R1 is connected to the source of the second Zener transistor M2.

[0065] One end of the second resistor R2 is connected to the other end of the first resistor R1, and the other end of the second resistor R2 is connected to the third terminal 61C of the clamping voltage regulator circuit 61.

[0066] Figure 8 A circuit diagram of a gate drive circuit 62-1 according to other embodiments of the present invention is shown. (See reference) Figure 8 The gate drive circuit 62-1 includes a first drive transistor M3, a second drive transistor M4, a comparator 621, a buffer circuit 622, and an inverter 623.

[0067] The drain of the first driving transistor M3 is connected to the first terminal 62A of the gate driving circuit 62-1, and the source of the first driving transistor M3 is connected to the second terminal 62B of the gate driving circuit 62-1.

[0068] The drain of the second driving transistor M4 is connected to the second terminal 62B of the gate driving circuit 62-1, and the source of the second driving transistor M4 is connected to the third terminal 62C of the gate driving circuit 62-1.

[0069] The positive input terminal of comparator 621 is connected to the first terminal 62A of gate drive circuit 62-1, and the negative input terminal is connected to the fifth terminal 62E of gate drive circuit 62-1.

[0070] The input of buffer circuit 622 is connected to the output of comparator 621. Buffer circuit 622 may include one or more buffers connected in series.

[0071] The input terminal 623A of inverter 623 is connected to the output terminal of buffer circuit 622, and the output terminal 623B of inverter 623 is connected to the gate of first driving transistor M3; the power supply terminal 623D of inverter 623 is connected to the fourth terminal 62D of gate driving circuit 62-1; the ground terminal 623C of inverter 623 is connected to the third terminal 62C of gate driving circuit 62-1.

[0072] Figure 9 Circuit diagrams of inverters according to other embodiments of the present invention are shown. (Reference) Figure 9 The inverter 623 may include a pair of P-type transistors M P and N-type transistor M N P-type transistor M PThe gate of the transistor is connected to the input terminal 623A of the inverter 623, the source is connected to the power supply terminal 623D of the inverter 623, and the drain is connected to the output terminal 623B of the inverter 623. N-type transistor M N The gate of the inverter 623 is connected to the input terminal 623A, the source is connected to the ground terminal 623C of the inverter 623, and the drain is connected to the output terminal 623B of the inverter 623.

[0073] Figure 10 A circuit diagram of a gate drive circuit 62-2 according to other embodiments of the present invention is shown. The gate drive circuit 62-2 and... Figure 8 The gate drive circuit 62-1 in the above is roughly the same, and for the sake of simplicity, it will be omitted. Figure 8 and Figure 10 Identical or similar devices / parts will use the same reference numerals. Figure 10 Gate drive circuit 62-2 and Figure 8 The difference between the gate drive circuit 62-1 and the gate drive circuit 62-2 is that the gate drive circuit 62-2 also includes a third diode D3. The anode of the third diode D3 is connected to the first port 62A of the gate drive circuit 62-2, and the drain of the first drive transistor M3 is connected to the cathode of the third diode D3.

[0074] Figure 11 The following diagram shows various signal waveforms of a power controller according to an embodiment of the present invention. (Reference) Figure 7 Regardless of the first voltage V IN1 Second voltage V IN2 It has a high or low level value, and the operating voltage is V. DD All values ​​stabilize at a given operating value. It is evident that, due to the clamping voltage regulator circuit, the clamping drive circuit can operate at a stable operating voltage, providing a normal and accurate drive voltage V. G This drives transistor 20, ensuring that transistor 20 can perform its optimal switching performance.

[0075] The above selection and description of embodiments are intended to best explain the principles of the invention and its practical application, and are not intended to exhaustively describe all possible implementations of the invention or to limit the invention to the precise forms disclosed. Various modifications and variations based on the described embodiments for various specific intended uses will be readily apparent to those skilled in the art.

Claims

1. A power device, characterized in that, include: First pin, second pin, and third pin; An enhancement-mode gallium nitride (GaN) transistor, wherein the drain of the GaN transistor is electrically connected to the second pin, and the source of the GaN transistor is electrically connected to the third pin; and A clamping drive circuit has a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the first terminal of the clamping drive circuit is connected to the first pin, the second terminal of the clamping drive circuit is connected to the second pin, the third terminal of the clamping drive circuit is connected to the third pin, and the fourth terminal of the clamping drive circuit is connected to the gate of the enhancement-mode gallium nitride transistor. The clamping drive circuit is configured as follows: Receive a first voltage V from the first pin IN1 ; Receive the second voltage V from the second pin IN2 ; When the first voltage V IN1 Higher than the second voltage V IN2 At that time, based on the first voltage V IN1 Generate gate drive voltage V G To the gate of the enhanced gallium nitride transistor; When the first voltage V IN1 Below the second voltage V IN2 At that time, based on the second voltage V IN2 Generate the gate drive voltage V G To the gate of the enhanced gallium nitride transistor; as well as When the first voltage V IN1 Equal to the second voltage V IN2 At that time, based on the first voltage V IN1 Or the second voltage V IN2 Generate the gate drive voltage V G To the gate of the enhanced gallium nitride transistor.

2. The power device according to claim 1, characterized in that, The clamping drive circuit includes: A clamping voltage regulator circuit has a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the first terminal of the clamping voltage regulator circuit is connected to a first terminal of a clamping drive circuit, the second terminal of the clamping voltage regulator circuit is connected to a second terminal of the clamping drive circuit, and the third terminal of the clamping voltage regulator circuit is connected to a third terminal of the clamping drive circuit; and A gate driving circuit has a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the first terminal of the gate driving circuit is connected to the first terminal of the clamping driving circuit, the second terminal of the gate driving circuit is connected to the fourth terminal of the clamping driving circuit, the third terminal of the gate driving circuit is connected to the third terminal of the clamping driving circuit, and the fourth terminal of the gate driving circuit is connected to the fourth terminal of the clamping voltage regulator circuit. The clamping voltage regulator circuit is configured as follows: Receives a first voltage V from the first terminal of the clamping drive circuit. IN1 ; Receives a second voltage V from the second terminal of the clamping drive circuit. IN2 ; When the first voltage V IN1 Higher than the second voltage V IN2 At that time, based on the first voltage V IN1 Generating operating voltage V DD To the fourth terminal of the gate drive circuit; When the first voltage V IN1 Below the second voltage V IN2 At that time, based on the second voltage V IN2 Generating operating voltage V DD To the fourth terminal of the gate drive circuit; and When the first voltage V IN1 Equal to the second voltage V IN2 At that time, based on the first voltage V IN1 Or the second voltage V IN2 Generating operating voltage V DD To the fourth terminal of the gate drive circuit; and The gate drive circuit is configured as follows: Receives a first voltage V from the first terminal of the clamping drive circuit. IN1 ; The operating voltage V is received from the fourth terminal of the clamping voltage regulator circuit. DD ;as well as Based on the first voltage V IN1 and the operating voltage V DD Generate the gate drive voltage V G .

3. The power device according to claim 2, characterized in that, The clamping voltage regulator circuit includes: A first diode, the anode of which is connected to the first terminal of the clamping voltage regulator circuit; A second diode, the negative terminal of which is connected to the negative terminal of the first diode; A high-voltage junction field-effect transistor (JFET), wherein the drain of the JFET is connected to the second terminal of the clamping voltage regulator circuit, the source of the JFET is connected to the positive terminal of the second diode, and the gate of the JFET is connected to the third terminal of the clamping voltage regulator circuit. A reference regulator, the input of which is connected to the negative terminals of the first diode and the second diode; An operational amplifier, the positive input of which is connected to the output of the reference regulator; The first Zener transistor has its drain connected to the input terminal of the reference regulator, its gate connected to the output terminal of the operational amplifier, and its source connected to the fourth terminal of the clamping regulator circuit. The second Zener transistor has its gate and drain connected together to the fourth terminal of the clamping voltage regulator circuit. A first resistor, one end of which is connected to the source of the second Zener transistor; and A second resistor, one end of which is connected to the other end of the first resistor, and the other end of which is connected to the third terminal of the clamping voltage regulator circuit.

4. The power device according to claim 3, characterized in that, The gate driving circuit includes: A first driving transistor, the drain of which is connected to the first terminal of the gate driving circuit, the The source of the first driving transistor is connected to the second terminal of the gate driving circuit; The second driving transistor has its drain connected to the second terminal of the gate driving circuit and its source connected to the third terminal of the gate driving circuit. An inverting Schmitt trigger, wherein the input terminal of the inverting Schmitt trigger is connected to the first terminal of the gate drive circuit; A buffer circuit comprising one or more buffers connected in series, the input of the buffer circuit being connected to the output of the inverting Schmitt trigger, and the output of the buffer circuit being connected to the gate of the second driving transistor; and An inverter, the input terminal of which is connected to the output terminal of the buffer circuit, the output terminal of which is connected to the gate of the first driving transistor; the power supply terminal of which is connected to the fourth terminal of the gate driving circuit; and the ground terminal of which is connected to the third terminal of the gate driving circuit.

5. The power device according to claim 4, characterized in that, The inverter includes: A P-type transistor, wherein the gate of the P-type transistor is connected to the input terminal of the inverter, the source of the P-type transistor is connected to the power supply terminal of the inverter, and the drain of the P-type transistor is connected to the output terminal of the inverter; and An N-type transistor, wherein the gate of the N-type transistor is connected to the input terminal of the inverter, the source of the N-type transistor is connected to the ground terminal of the inverter, and the drain of the N-type transistor is connected to the output terminal of the inverter.

6. The power device according to claim 3, characterized in that, The gate driving circuit includes: The third diode, the positive terminal of which is connected to the first terminal of the gate drive circuit; A first driving transistor, the drain of which is connected to the negative terminal of the third diode, and the source of which is connected to the second terminal of the gate driving circuit. The second driving transistor has its drain connected to the second terminal of the gate driving circuit and its source connected to the third terminal of the gate driving circuit. An inverting Schmitt trigger, wherein the input terminal of the inverting Schmitt trigger is connected to the first terminal of the gate drive circuit; A buffer circuit comprising one or more buffers connected in series, the input of the buffer circuit being connected to the output of the inverting Schmitt trigger, and the output of the buffer circuit being connected to the gate of the second driving transistor; and An inverter, the input terminal of which is connected to the output terminal of the buffer circuit, the output terminal of which is connected to the gate of the first driving transistor; the power supply terminal of which is connected to the fourth terminal of the gate driving circuit; and the ground terminal of which is connected to the third terminal of the gate driving circuit.

7. The power device according to claim 6, characterized in that, The inverter includes: A P-type transistor, wherein the gate of the P-type transistor is connected to the input terminal of the inverter, the source of the P-type transistor is connected to the power supply terminal of the inverter, and the drain of the P-type transistor is connected to the output terminal of the inverter; and An N-type transistor, wherein the gate of the N-type transistor is connected to the input terminal of the inverter, the source of the N-type transistor is connected to the ground terminal of the inverter, and the drain of the N-type transistor is connected to the output terminal of the inverter.

8. The power device according to any one of claims 1 to 7, characterized in that, The enhanced gallium nitride transistor is an enhanced field-effect transistor.

9. The power device according to claim 8, characterized in that, The enhancement-mode field-effect transistor is a GaN enhancement-mode field-effect transistor.

10. The power device according to claim 9, characterized in that, The GaN enhancement-mode field-effect transistor is an AlGaN / GaN enhancement-mode field-effect transistor.

11. The power device according to claim 10, characterized in that, The AlGaN / GaN enhancement-mode field-effect transistor is an AlGaN / GaN enhancement-mode high electron mobility field-effect transistor.

12. The power device according to claim 1, characterized in that, The clamping drive circuit includes: A clamping voltage regulator circuit has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal, wherein the first terminal of the clamping voltage regulator circuit is connected to the first terminal of the clamping drive circuit, the second terminal of the clamping voltage regulator circuit is connected to the second terminal of the clamping drive circuit, and the third terminal of the clamping voltage regulator circuit is connected to the third terminal of the clamping drive circuit; and A gate driving circuit has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal, wherein the first terminal of the gate driving circuit is connected to the first terminal of the clamping driving circuit, the second terminal of the gate driving circuit is connected to the fourth terminal of the clamping driving circuit, the third terminal of the gate driving circuit is connected to the third terminal of the clamping driving circuit, the fourth terminal of the gate driving circuit is connected to the fourth terminal of the clamping voltage regulator circuit, and the fifth terminal of the gate driving circuit is connected to the fifth terminal of the clamping voltage regulator circuit. The clamping voltage regulator circuit is configured as follows: Receives a first voltage V from the first terminal of the clamping drive circuit. IN1 ; Receives a second voltage V from the second terminal of the clamping drive circuit. IN2 ; When the first voltage V IN1 Higher than the second voltage V IN2 At that time, based on the first voltage V IN1 Generating operating voltage V DD To the fourth terminal of the gate drive circuit; When the first voltage V IN1 Below the second voltage V IN2 At that time, based on the second voltage V IN2 Generating operating voltage V DD To the fourth terminal of the gate drive circuit; and When the first voltage V IN1 Equal to the second voltage V IN2 At that time, based on the first voltage V IN1 Or the second voltage V IN2 Generating operating voltage V DD To the fourth terminal of the gate drive circuit and generate the reference voltage V REF To the fifth terminal of the gate drive circuit; and The gate drive circuit is configured as follows: Receives a first voltage V from the first terminal of the clamping drive circuit. IN1 ; The operating voltage V is received from the fourth terminal of the clamping voltage regulator circuit. DD ;as well as Based on the first voltage V IN1 The operating voltage V DD and the reference voltage V REF Generate the gate drive voltage V G .

13. The power device according to claim 12, characterized in that, The clamping voltage regulator circuit includes: A first diode, the anode of which is connected to the first terminal of the clamping voltage regulator circuit; A second diode, the negative terminal of which is connected to the negative terminal of the first diode; A high-voltage junction field-effect transistor (JFET), wherein the drain of the JFET is connected to the second terminal of the clamping voltage regulator circuit, the source of the JFET is connected to the positive terminal of the second diode, and the gate of the JFET is connected to the third terminal of the clamping voltage regulator circuit. A reference regulator, the input terminal of which is connected to the negative terminals of the first diode and the second diode, and the output terminal of which is connected to the fifth terminal of the clamping regulator circuit; An operational amplifier, the positive input of which is connected to the output of the reference regulator; The first Zener transistor has its drain connected to the input terminal of the reference regulator, its gate connected to the output terminal of the operational amplifier, and its source connected to the fourth terminal of the clamping regulator circuit. The second Zener transistor has its gate and drain connected together to the fourth terminal of the clamping voltage regulator circuit. A first resistor, one end of which is connected to the source of the second Zener transistor; and A second resistor, one end of which is connected to the other end of the first resistor, and the other end of which is connected to the third terminal of the clamping voltage regulator circuit.

14. The power device according to claim 13, characterized in that, The gate driving circuit includes: A first driving transistor, the drain of which is connected to a first terminal of the gate driving circuit, and the source of which is connected to a second terminal of the gate driving circuit. The second driving transistor has its drain connected to the second terminal of the gate driving circuit and its source connected to the third terminal of the gate driving circuit. A comparator, wherein the positive input terminal of the comparator is connected to the first terminal of the gate driving circuit, and the negative input terminal of the comparator is connected to the fifth terminal of the gate driving circuit; A buffer circuit comprising one or more buffers connected in series, the input of the buffer circuit being connected to the output of the comparator, and the output of the buffer circuit being connected to the gate of the second driving transistor; and An inverter, the input terminal of which is connected to the output terminal of the buffer circuit, the output terminal of which is connected to the gate of the first driving transistor; the power supply terminal of which is connected to the fourth terminal of the gate driving circuit; and the ground terminal of which is connected to the third terminal of the gate driving circuit.

15. The power device according to claim 14, characterized in that, The inverter includes: A P-type transistor, wherein the gate of the P-type transistor is connected to the input terminal of the inverter, the source of the P-type transistor is connected to the power supply terminal of the inverter, and the drain of the P-type transistor is connected to the output terminal of the inverter; and An N-type transistor, wherein the gate of the N-type transistor is connected to the input terminal of the inverter, the source of the N-type transistor is connected to the ground terminal of the inverter, and the drain of the N-type transistor is connected to the output terminal of the inverter.

16. The power device according to claim 13, characterized in that, The gate driving circuit includes: The third diode, the positive terminal of which is connected to the first terminal of the gate drive circuit; A first driving transistor, the drain of which is connected to the negative terminal of the third diode, and the source of which is connected to the second terminal of the gate driving circuit. The second driving transistor has its drain connected to the second terminal of the gate driving circuit and its source connected to the third terminal of the gate driving circuit. A comparator, wherein the positive input terminal of the comparator is connected to the first terminal of the gate driving circuit, and the negative input terminal of the comparator is connected to the fifth terminal of the gate driving circuit; A buffer circuit comprising one or more buffers connected in series, the input of the buffer circuit being connected to the output of the comparator, and the output of the buffer circuit being connected to the gate of the second driving transistor; and An inverter, the input terminal of which is connected to the output terminal of the buffer circuit, the output terminal of which is connected to the gate of the first driving transistor; the power supply terminal of which is connected to the fourth terminal of the gate driving circuit; and the ground terminal of which is connected to the third terminal of the gate driving circuit.

17. The power device according to claim 16, characterized in that, The inverter includes: A P-type transistor, wherein the gate of the P-type transistor is connected to the input terminal of the inverter, the source of the P-type transistor is connected to the power supply terminal of the inverter, and the drain of the P-type transistor is connected to the output terminal of the inverter; and An N-type transistor, wherein the gate of the N-type transistor is connected to the input terminal of the inverter, the source of the N-type transistor is connected to the ground terminal of the inverter, and the drain of the N-type transistor is connected to the output terminal of the inverter.

18. The power device according to any one of claims 12 to 17, characterized in that, The enhanced gallium nitride transistor is an enhanced field-effect transistor.

19. The power device according to claim 18, characterized in that, The enhancement-mode field-effect transistor is a GaN enhancement-mode field-effect transistor.

20. The power device according to claim 19, characterized in that, The GaN enhancement-mode field-effect transistor is an AlGaN / GaN enhancement-mode field-effect transistor.

21. The power device according to claim 20, characterized in that, The AlGaN / GaN enhancement-mode field-effect transistor is an AlGaN / GaN enhancement-mode high electron mobility field-effect transistor.

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