Control circuit, integrated circuit, electronic converter and method

Abstract

Control circuits, integrated circuits, electronic converters and methods are disclosed. In a control circuit for a switching stage of an electronic converter, a phase detector generates a drive signal in response to a phase difference between a first clock signal and a second clock signal. The first clock signal and the second clock signal are generated by a first current-controlled oscillator and a second current-controlled oscillator, respectively. An operational transconductance amplifier generates first and second control currents in response to a difference between a reference and a feedback of the electronic converter, the first and second currents being applied to control the first and second current-controlled oscillators. In response to a switching clock having a first state, a switching circuit applies first and second bias currents to control inputs of the first and second current-controlled oscillators, respectively. Conversely, in response to the switching clock having a second state, the switching circuit applies the second and first bias currents to the control inputs of the first and second current-controlled oscillators, respectively.

Description

[0001] Cross-reference of related technologies

[0002] This application claims priority to Italian patent application No. 102021000029294, filed on November 19, 2021, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] The embodiments in this specification relate to control devices for buck voltage converters. Background Technology

[0004] Power supply circuits, such as AC / DC or DC / DC switching power supplies, are well known in the art. Various types of electronic converters exist, primarily categorized as isolated and non-isolated converters. For example, non-isolated electronic converters include buck converters, boost converters, and buck-boost converters. Converters of the “SEPIC” and “ZETA” types. In contrast, isolated converters are converters of the “flyback”, “forward”, “half-bridge”, and “full-bridge” types, for example. Such converters are well known to those skilled in the art, as demonstrated, for example, by L. Wuidart’s 1999 application note AN513 / 0393 “Topologies for Switched Mode PowerSupplies” in STMicroelectronics (incorporated herein by reference).

[0005] Figure 1 This is a schematic diagram of a DC / DC electronic converter 20. Specifically, the general-purpose electronic converter 20 includes components for receiving a DC voltage V. in The two input terminals 200a and 200b and the one for providing DC voltage V out The two output terminals are 202a and 202b. For example, the input voltage V in The voltage can be supplied by a DC voltage source 10, such as a battery, or it can be obtained from an AC voltage using a rectifier circuit, such as a bridge rectifier, and possibly a filter circuit. Conversely, the output voltage V out It can be used to power a load of 30.

[0006] Figure 2 A circuit diagram of a typical buck converter 20 is shown. Specifically, the buck converter 20 includes a circuit for receiving a DC input voltage V. in The two input terminals 200a and 200b and the voltage V used to provide regulation voltage out The two output terminals 202a and 202b, wherein the output voltage is equal to or lower than the input voltage V.in .

[0007] Specifically, typically, the buck converter 20 includes two electronic switches Q1 and Q2 (and their current paths) connected in series (e.g., directly) between input terminals 200a and 200b, wherein the intermediate node between electronic switches Q1 and Q2 represents a switching node Lx. Specifically, electronic switch Q1 is a high-side switch (e.g., directly) connected between the (positive) terminal 200a and the switching node Lx, and electronic switch Q2 is a low-side switch (e.g., directly) connected between the switching node Lx and the (negative) terminal 200b, which typically represents ground GND. Therefore, the (high-side) switch Q1 and the (low-side) switch Q2 are configured to connect the switching node Lx to terminal 200a (voltage V). in (or a half-bridge with terminal 200b (GND)).

[0008] For example, switches Q1 and / or Q2 are typically transistors, such as field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), n-channel FETs, or NMOS transistors. Typically, the second electronic switch Q2 is also implemented using only a diode, with the anode connected to terminal 200b and the cathode connected to the switching node Lx.

[0009] In the example under consideration, an inductor L, such as an inductor, is connected (e.g., directly) between the switching node Lx and the (positive) output terminal 202a. Conversely, the (negative) output terminal 202b is connected (e.g., directly) to the (negative) input terminal 200b.

[0010] In the example considered, in order to stabilize the output voltage V out Converter 20 typically includes (e.g., directly) a capacitor Cout connected between output terminals 202a and 202b.

[0011] in this case, Figure 3 Exemplary waveforms of the signals from this electronic converter are shown, wherein: waveform a) shows the signal DRV1 used to switch electronic switch Q1; waveform b) shows the signal DRV2 used to switch the second electronic switch Q2; and waveform c) shows the current I flowing through electronic switch Q1. Q1 Waveform d) shows the voltage V at the switching node Lx. Lx (That is, the voltage at the second switch Q2); and waveform e) shows the current I flowing through inductor L. L .

[0012] Specifically, when electronic switch Q1 is closed (on state) at time t1, the current I in inductor L is... L(Effectively) linearly increases. Electronic switch Q2 opens simultaneously. Conversely, when electronic switch Q1 is at interval T... ON1 Then, at time t2, when the switch is turned off, electronic switch Q2 closes, and current I... L It decreases (basically) linearly. Finally, switch Q1 at interval T OFF1 Then it closes again. In the example under consideration, when switch Q1 is open, switch Q2 (or a similar diode) is therefore closed, and vice versa.

[0013] Therefore, current I L It can be used to charge capacitor Cout, which provides a voltage V at terminals 202a and 202b. out .

[0014] In the example considered, the electronic converter 20 therefore includes a control circuit 22 configured to drive the switching of switch Q1, and possibly the switching of switch Q2, to periodically repeat interval T. ON1 and T OFF1 For example, typically, the buck converter 20 also includes a feedback circuit 24, such as a voltage divider (Div), which is configured to generate an indication output voltage V. out (and preferably with output voltage V) out The feedback signal FB is proportional to the reference signal (e.g., reference voltage V), and the control circuit 22 is configured to provide a feedback signal FB proportional to the reference signal (e.g., reference voltage V). REF The drive signals DRV1 and DRV2 are generated by comparing them.

[0015] Numerous driving schemes are known for generating drive signal DRV1 and optionally DRV2. These solutions share the characteristic of adjusting the interval T. ON1 and / or interval T OFF1 The duration is used to adjust the output voltage V. out The possibility.

[0016] For example, in many applications, control circuit 22 generates a pulse width modulation (PWM) signal DRV1, where the switching interval T SW =T ON1 +T OFF1 The duration is constant, but the duty cycle T ON / T SW It is variable. For example, a typical control scheme includes interval T. ON1 The duration is changed by a regulator circuit with at least an integral component, such as a PI (proportional-integral) or PID (proportional-integral-derivative) regulator.

[0017] Specifically, as is well known, buck converters can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or conversion mode (TM).

[0018] like Figure 4A As shown, when the control circuit 20 operates the converter in CCM mode, the current I flowing through the inductor L is... L At interval T OFF1 It ends with a value other than zero (see Figure 3 In this case, control circuit 20 uses two switching stages T1 and T2, where T... SW =T1+T2, where: in stage T1 (T1=T ON1 =T OFF2 During this period, switch Q1 is closed and switch / diode Q2 is open; and in stage T2 (T2 = T OFF1 =T ON2 During this period, switch Q1 is open and switch / diode Q2 is closed.

[0019] For example, in a CCM, the control circuit 20 can use a switching cycle T with a fixed duration. SW However, the connection duration T ON1 =T1 can be changed via a PID controller; that is, signal DRV1 is a PWM signal with a (fixed or predetermined frequency), but the on-time / duty cycle is adjusted according to the output voltage (and the reference signal V). REF This is determined by [the signal]. Conversely, the optional signal DRV2 can correspond to the inverted version of signal DRV1.

[0020] On the contrary, such as Figure 4B As shown, when the control circuit 20 operates the converter in DCM mode, the current I flowing through the inductor L is... L At interval T OFF1 It reaches zero during the period and remains zero until the interval T. OFF1 End (see) Figure 3 In this case, control circuit 20 actually uses three switching stages T1, T2, and T3, where T... SW =T1+T2+T3, where: in stage T1 (T1=T ON1 During this period, switch Q1 is closed and switch / diode Q2 is open; in stage T2 (T2 = T ON2 During this period, switch Q1 is open and switch / diode Q2 is closed; and in stage T3(T OFF1 =T2+T3 and T OFF2 During the period (T3+T1), switch Q1 is open and switch / diode Q2 is open.

[0021] For example, when a diode is used as a switch Q2, when the current I...L When the current reaches zero, the diode will automatically turn off, thus ending interval T2. Conversely, when using a controllable electronic switch Q2, the control circuit 20 typically includes (or is connected to) a demagnetization detection circuit configured to determine the current I. L The moment it reaches zero (corresponding to the end of interval T2 and the beginning of interval T3). For example, this demagnetization detection circuit can monitor the current I. L For example, in Figure 2 The diagram shows a current sensor 24b connected in series with an electronic switch Q2, such as a shunt resistor, which thus generates a current I indicating the current flowing through the inductor L during interval T2. L The measurement signal CS (and preferably proportional to it).

[0022] Therefore, in the DCM, the control circuit 20 can reuse the switching cycle T with a fixed duration. SW The connection duration T ON1 =T1 can be changed again via a PID controller, that is, signal DRV1 is a PWM signal with a fixed or predetermined frequency, and the on-time / duty cycle is based on the output voltage (and reference signal V). REF This can be determined by [the specific circuit]. However, when using a controllable electronic switch Q2, the control circuit 20 can be configured to disconnect the electronic switch Q2 when the signal CS indicates demagnetization of the inductor L.

[0023] Therefore, the CCM and DCM modes of the buck converter have something in common: the electronic switch Q1 can typically be driven using a fixed-frequency PWM signal DRV1. Conversely, the optional drive signal DRV2 can be determined based on the drive signal DRV1 and an additional signal CS (when operating in DCM) that indicates the demagnetization of the inductor L.

[0024] Typically, a (usually fixed) dead time can be introduced between switching of drive signals, such as between the falling edge of signal DRV1 and the rising edge of signal DRV2, and similarly (in CCM mode) between the falling edge of signal DRV2 and the rising edge of signal DRV1. This dead time is related to the duration T. ON and T OFF In contrast, these intervals are typically shorter, and therefore will not be considered in the following text. However, in the same case, the drive signal DRV2 can be determined based on the drive signal DRV1.

[0025] Other electronic converters that typically use PWM modulation include boost, buck-boost, flyback or forward converters, and various types of half-bridge converters.

[0026] For example, Figure 5An example of a boost converter is shown. Specifically, in the example under consideration, an inductor L (e.g., directly) is connected between the positive input terminal 200a and the switching node Lx. The switching node Lx is connected to the negative input terminal 200b via a first electronic switch S1 (current path, e.g., directly), and the negative input terminal 200b is typically connected in turn (e.g., directly) to the negative output terminal 202b. The switching node Lx is also connected to the positive output terminal 202a via a second electronic switch S2 (current path, e.g., directly). For example, electronic switches S1 and S2 can be MOSFETs. Typically, electronic switch S2 can also be implemented using only a diode. Typically, a capacitor Cout, such as a capacitor, is connected between the output terminals 202a and 202b.

[0027] In the same scenario, electronic switch S1 can be driven by PWM signal DRV1, where the duty cycle is determined by the output voltage V. out and reference voltage V REF Conversely, when using a controllable electronic switch S2, the electronic switch S2 can be driven by a signal DRV2, which in the CCM can correspond to the inverted version of signal DRV1; or it can be determined based on signal DRV1 and a signal CS indicating the demagnetization of inductor L, for example, the current measurement signal CS and the current I flowing through inductor L. L Proportional.

[0028] in this regard, Figure 6 A general-purpose electronic converter 20 using a PWM signal DRV with a fixed or predetermined frequency is shown. Specifically, the electronic converter 20 includes a switching stage 26 connected between input terminals 200a, 200b and output terminals 202a, 202b. This switching stage 26 includes one or more electronic switches SW. 26 and at least one inductor L 26 For example, an inductor or transformer, and optionally one or more capacitors C 26 For example, capacitors. For example, in a buck converter ( Figure 2 These components are switch Q1, switch or diode Q2, inductor L, and capacitor Cout. Conversely, in a boost converter ( Figure 5 These components are switch S1, switch or diode S2, inductor L, and capacitor Cout.

[0029] In the considered example, the control circuit 22 includes a driver circuit 222 configured to respond to the PWM signal DRV and the indicator inductor L. 26 The optional measurement signal CS for demagnetization generates one or more drive signals for switching stage 26. The PWM signal DRV has a switching period T. SW(with a fixed or predetermined period), where the signal DRV is set to a first duration T ON The first logic level (e.g., high) and the second duration T OFF The second logic level (e.g., low), where T SW =T ON +T OFF (See also) Figure 7 ).

[0030] For example, as mentioned earlier, the PWM signal DRV can be used to drive... Figure 2 Switch Q1 and Figure 5 Switch S1. Conversely, when the electronic converter operates in DCM mode, the measurement signal CS can be used, for example, for driving. Figure 2 electronic switch Q2 or Figure 5 Switch S2.

[0031] according to Figure 2 The description typically uses feedback circuit 24 to generate the indicator output voltage V. out (and preferably with output voltage V) out Proportional, for example, proportional to the output voltage V out The feedback signal FB corresponds to the input signal. Next, the regulator circuit 220, such as a PID controller, can adjust the input signal based on the feedback signal FB and the reference signal V. REF To change the duration T of the PWM signal DRV ON .

[0032] For example, as described in U.S. Patent No. 9,091,741B2 (incorporated by reference), such a PID controller is typically implemented using an error amplifier that includes an operational amplifier and a feedback network that includes one or more capacitors and resistors.

[0033] Recently, another type of regulator circuit 220 has been used, in which a time-based regulator is used to generate the PWM signal DRV. Time-based DC-DC converters are becoming increasingly popular because this type of control scheme offers many advantages. Due to the continuous-time digital nature of time-based regulators, they combine the advantages of traditional analog and digital controller circuits 220. Essentially, they work with digital signals (e.g., CMOS level) without adding any quantization errors typically present in digital controllers. The time-based regulator circuit 220 deploys simple circuitry such as ring oscillators, delay lines, and flip-flops, eliminating the need for wide-bandwidth error amplifiers and PWM blocks in analog regulator circuits, or high-resolution analog-to-digital converters (ADCs) and digital PWM blocks in digital regulator circuits. Using time as the processing variable, this new control provides an attractive solution for realizing electronic converters based on wide-bandwidth, high-switching-frequency PWM, as it eliminates the need for power- and area-intensive wide-bandwidth amplifiers and high-speed comparators found in traditional PID controllers.

[0034] For example, such a time-based PID is described in U.S. Patent Publication No. 2021 / 0226531A1 (incorporated by reference).

[0035] There is a need in the art for a time-based control device for PWM-driven electronic converters (e.g., buck or boost converters). Summary of the Invention

[0036] According to one or more embodiments, a control circuit for an electronic converter is provided. The embodiments also relate to related integrated circuits, electronic converters, and methods.

[0037] Various embodiments of this disclosure relate to control circuitry for a switching stage of an electronic converter, the switching stage being configured to provide an output voltage via two output terminals. For example, the electronic converter may be a buck or boost converter.

[0038] In various embodiments, such as control circuitry implemented in an integrated circuit, one or more terminals are configured to provide one or more corresponding drive signals to one or more electronic switches of a switching stage of an electronic converter, and the terminals are configured to receive a first feedback signal proportional to the output voltage from a feedback circuit.

[0039] In various embodiments, the control circuitry includes a driver circuit configured to generate one or more drive signals based on a pulse width modulation (PWM) signal, and a PWM signal generator circuit configured to generate a PWM signal based on a first feedback signal and a reference voltage.

[0040] Specifically, in various embodiments, the PWM signal generator circuit includes a first current-controlled oscillator and a second current-controlled oscillator. The first current-controlled oscillator has an input terminal for receiving a first current and being configured to generate a first clock signal based on the first current, and the second current-controlled oscillator has an input terminal for receiving a second current and being configured to generate a second clock signal based on the second current.

[0041] Furthermore, in various embodiments, the PWM signal generator circuit includes a first operational transconductance amplifier and a phase detector. Specifically, the first operational transconductance amplifier has a first output terminal and is configured to provide a third current at the first output terminal indicating the difference between a reference voltage and a first feedback signal, wherein the first output terminal of the first operational transconductance amplifier is connected to the input terminal of a first current-controlled oscillator. The phase detector has inputs coupled to a first oscillator and a second oscillator and provides a PWM signal at its output.

[0042] Specifically, according to various embodiments, the PWM signal generator circuit further includes a first bias current generator and a second bias current generator. The first bias current generator has an output terminal and is configured to provide a first bias current at the output terminal, and the second bias current generator has an output terminal and is configured to provide a second bias current at the output terminal. Specifically, in various embodiments, the switching circuit is configured to receive a clock signal and determine the logic level of the clock signal. In response to determining that the logic level of the clock signal has a first logic level, the switching circuit connects the output terminal of the first bias current generator to the input terminal of a first current-controlled oscillator and connects the output terminal of the second bias current generator to the input terminal of the second current-controlled oscillator. Conversely, in response to determining that the logic level of the clock signal has a second logic level, the switching circuit connects the output terminal of the first bias current generator to the input terminal of the second current-controlled oscillator and connects the output terminal of the second bias current generator to the input terminal of the first current-controlled oscillator.

[0043] For example, in various embodiments, the clock signal is derived from a first clock signal or a second clock signal. For example, the clock signal may correspond to either the first clock signal or the second clock signal.

[0044] In various embodiments, the PWM signal generator circuit may further include one or more first delay lines connected between a first oscillator and a phase detector, and / or one or more second delay lines connected between a second oscillator and a phase detector. For example, these delay lines can be used to implement the proportional and / or derivative components of the regulator. For example, to implement the proportional component, one or more first delay lines and / or one or more second delay lines can be driven based on the difference between a reference voltage and a first feedback signal. Conversely, to implement the derivative component, the control circuit may include a third terminal configured to receive a second feedback signal proportional to the derivative of the output voltage from an analog differentiator. In this case, one or more first delay lines and / or one or more second delay lines can be driven based on the difference between the reference voltage and the second feedback signal.

[0045] For example, in various embodiments, one or more first delay lines and one or more second delay lines are current-controlled delay lines. In this case, the PWM signal generator circuit may include a second operational transconductance amplifier and / or a third operational transconductance amplifier, the second operational transconductance amplifier being configured to generate a fourth current indicating the difference between the reference voltage and the first feedback signal, and the third operational transconductance amplifier being configured to generate a fifth current indicating the difference between the reference voltage and the second feedback signal. Therefore, the fourth and fifth currents may be provided to one or more first delay lines and / or one or more second delay lines.

[0046] Typically, a differential operational amplifier can also be used. For example, the first operational transconductance amplifier can be a differential operational transconductance amplifier including a second output terminal, wherein the first operational transconductance amplifier is configured to provide a sixth current at the second output terminal, wherein the difference between the sixth current and the third current is proportional to the difference between the reference voltage and the first feedback signal. In this case, the second output terminal of the first operational transconductance amplifier can therefore be connected to the input terminal of a second current-controlled oscillator.

[0047] Similarly, to achieve the proportional component, the second operational transconductance amplifier can actually generate two currents, where a first current is applied to one or more first delay lines and a second current is applied to one or more second delay lines, wherein the difference between these currents is proportional to the difference between the reference voltage and the first feedback signal. Conversely, to achieve the derivative component, the third operational transconductance amplifier can generate two currents, where a first current is applied to one or more first delay lines and a second current is applied to one or more second delay lines, wherein the difference between these currents is proportional to the difference between the reference voltage and the second feedback signal. In various embodiments, the first current generated by the second operational transconductance amplifier and the first current generated by the third operational transconductance amplifier can be added and applied to the same one or more first delay lines. Similarly, the second current generated by the second operational transconductance amplifier and the second current generated by the third operational transconductance amplifier can be added and applied to the same one or more second delay lines. Attached Figure Description

[0048] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided purely by way of non-limiting example, in which:

[0049] The features and advantages of the present invention will become apparent from the following detailed description of practical embodiments thereof, which are illustrated by non-limiting examples in the accompanying drawings, wherein:

[0050] Figure 1 An example of an electronic converter is shown;

[0051] Figure 2 An example of a buck converter is shown;

[0052] Figure 3 It shows Figure 2 An exemplary waveform of a buck converter;

[0053] Figure 4A It shows Figure 2 The waveform of the buck converter when it is operating in CCM mode;

[0054] Figure 4B It shows Figure 2 Waveform of a step-down converter operating in DCM mode;

[0055] Figure 5 An example of a boost converter is shown;

[0056] Figure 6 An example of an electronic converter using a PWM signal is shown;

[0057] Figure 7 It shows Figure 6 An example of a PWM signal for an electronic converter;

[0058] Figure 8 It shows the use of Figure 6 A first example of a time-based control circuit for an electronic converter;

[0059] Figure 9 It shows Figure 8 Exemplary waveforms of the control circuit;

[0060] Figure 10 It shows the use of Figure 6 A second example of a time-based control circuit for an electronic converter;

[0061] Figure 11 It shows Figure 10 Exemplary waveforms of the control circuit;

[0062] Figure 12 It shows Figure 10 Possible implementations of time-based control circuits;

[0063] Figure 13 An embodiment of a modified time-based control circuit is shown; and

[0064] Figure 14 It shows in Figure 13 An example of a switching circuit used in a time-based control circuit. Detailed Implementation

[0065] In the following description, various specific details are shown to provide a thorough understanding of the embodiments. Embodiments may be provided without one or more specific details, or may have other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so that various aspects of the embodiments are not obscured.

[0066] References to "embodiment" or "an embodiment" within the framework of this specification mean that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at different points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific conformations, structures, or features may be combined in any suitable manner.

[0067] The reference numerals used herein are provided for convenience only and are therefore not intended to limit the scope of protection or the scope of the embodiments.

[0068] The following description Figures 8 to 14 In the middle, it has been referenced Figures 1 to 7The parts, elements, or assemblies described are indicated by the same reference numerals used previously in these figures. These elements have already been described and, to avoid burdening this detailed description, will not be repeated below.

[0069] As explained above, various embodiments of this disclosure relate to an improved time-based control circuit 22a for an electronic converter. For a general description of an electronic converter using a PWM signal, refer to the preceding... Figures 1 to 7 The description of the time-based PID controller is not provided. Instead, for a general description of the time-based PID controller, see previously cited U.S. Patent Application Publication No. 2021 / 0226531A1 (incorporated by reference).

[0070] For example, Figure 8 An example of a time-based control circuit 22a, for example, in the form of an integrated circuit, is schematically shown. Specifically, also in this case, the control circuit 22a includes a PWM signal generator 220a, which is configured to generate an output voltage V according to an indication of the switching stage (SS) 26 of the electronic converter. out and reference voltage V REF The feedback signal FB is used to generate the PWM signal DRV; and the driver circuit 222 is configured to drive the switching stage 26 according to the PWM signal DRV.

[0071] Specifically, in the considered embodiment, the PWM signal generator 220a includes: a first voltage-controlled oscillator 2220 configured to generate a first clock signal CLK1 based on a feedback signal FB; and an analog differentiator 2222 configured to generate a signal indicating the derivative of the feedback signal FB (and preferably proportional to the derivative of the feedback signal FB), the signal being, for example, generated by a capacitor C connected in series between the feedback signal FB and a reference voltage (e.g., ground). D and resistor R D This is achieved (the reference voltage may, for example, correspond to the negative input terminal 200b or the negative output terminal 202b), where capacitor C... D and resistor R D The intermediate node between them corresponds to a signal indicating the derivative of the feedback signal FB; a first delay line 2224 having a delay according to the feedback signal FB and a second delay line 2226 having a delay according to the signal indicating the derivative of the feedback signal FB, wherein the first delay line and the second delay line are cascaded and generate a delayed first clock signal CLK1'; a second voltage-controlled oscillator 2228, which is configured to operate according to a reference voltage V REF A second clock signal CLK2 is generated; and a phase detector (PD) circuit 2230 is configured to generate a PWM signal DRV, wherein the duty cycle of the PWM signal DRV is determined based on the phase difference Φ between the clock signal CLK2 and the delayed clock signal CLK1'.

[0072] Delay lines having programmable delays based on voltage or current signals are well known in the art. For example, U.S. Patent Nos. 5,650,739A and 7,696,799B2 (incorporated by reference) may be cited herein.

[0073] For example, such as Figure 9 As shown, the phase detector circuit 2230 can be configured to set the DRV signal high when the second clock signal CLK2 is high and the delayed first clock signal CLK1' is low. For example, the phase detector 2230 can be implemented using one or more logic gates and / or one or more latches.

[0074] In the considered embodiment, the second voltage-controlled oscillator 2228 therefore operates according to the reference voltage V. REF A clock signal CLK2 with a given (fixed or configurable) frequency is provided. Conversely, the first voltage-controlled oscillator 2220 changes the frequency of the first clock signal CLK1 until the feedback signal FB corresponds to the reference voltage V. REF Furthermore, in this stable state, the frequency of the first clock signal CLK1 corresponds to the frequency of the second clock signal CLK2, but the clock signals are phase-shifted by a given phase Φ. I Therefore, the first oscillator 2220 achieves a phase Φ I The regulator for the I (integral) component. Conversely, the first delay line 2224 and the second delay line 2226 introduce an additional phase Φ proportional to the feedback signal FB. P The additional phase Φ is proportional to the derivative of the feedback signal FB. D That is, the total phase shift Φ corresponds to: Φ = Φ I +Φ P +Φ D Among them, such as Figure 9 As shown, the phase shift Φ is related to the on-time T. ON Proportional (and preferably corresponding to) the on-time T ON (For example, T) ON =T SW (Φ / 2π)), that is, the signal DRV is a PWM signal, where, based on the feedback signal FB and the reference voltage V REF The on-time duration T is changed by time-based control (with PID regulation) of the phase shift Φ. ON / duty cycle. Therefore, the phase detector 2230 can also perform other operations, such as downscaling the frequency of clock signals CLK1 / CLK2, and only relevantly, the phase detector 2230 is configured to generate a PWM signal DRV, wherein the on-time T of the signal DRV is... ON It is determined based on the phase shift Φ.

[0075] Figure 10 A second example of a time-based PWM signal generator 220a is shown.

[0076] Specifically, in the considered embodiment, the following modifications have been performed, which can also be used individually: voltage-controlled oscillators 2220 and / or delay lines 2224 and 2226 have been replaced by current-controlled oscillators and / or delay lines; delay lines 2224 and 2226 have been combined into the same delay line 2234; and a differential method is used, wherein oscillators 2220 / 2228 and / or delay lines 2234 / 2235 are driven by differential signals.

[0077] Specifically, in the considered embodiment, feedback circuit 24 is again used to determine the relationship between the output voltage V and the voltage V. out A proportional feedback signal FB. For example, in various embodiments, the feedback circuit 24 is implemented using a voltage divider 24, which includes two or more resistors R connected in series between terminals 202a and 202b. FB1 and R FB2 One of the resistors (e.g., resistor R) FB2 Voltage V at point ) FB This corresponds to the feedback signal FB.

[0078] In the considered embodiment, the feedback signal FB and the reference voltage V REF It is provided to the first differential transconductor 2236, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2236 provides: a first current i I+ =i I0 +i I / 2; and the second current i I- =i I0 -i I / 2.

[0079] Specifically, in the differential transconductor 2236, the current i I+ and i I- The difference between i I =i I+ –i I- With each input voltage (i.e., reference voltage V) REF The difference between the feedback voltage (VFB) and the voltage is proportional, i. I =G MI (V REF -V FB ).

[0080] In the considered embodiment, the current i I+ The current i is supplied to the current-controlled oscillator 2228. I-The current is supplied to a current-controlled oscillator 2220, such as two ring oscillators. Therefore, the oscillator 2228 generates an oscillator with a current i I+ A clock signal CLK2 with a proportional frequency is generated by oscillator 2220, which has a frequency corresponding to the current i. I- A clock signal CLK1 with a proportional frequency. Therefore, when the feedback voltage VFB corresponds to the reference voltage V... REF At that time, current i is supplied to the two oscillators. I0 This allows us to determine the steady-state frequencies of clock signals CLK1 and CLK2.

[0081] Similarly, the feedback signal FB and the reference voltage V REF This is provided to a second differential transconductor 2238, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2238 provides: a first current i P+ =i P0 +i P / 2; and the second current i P- =i P0 -i P / 2.

[0082] Specifically, in the differential transconductor 2238, the current i P+ and i P- The difference between i P =i P+ –i P- With each input voltage (i.e., reference voltage V) REF The difference between the feedback voltage (VFB) and the voltage is proportional, i. P =G MP (V REF -V FB ).

[0083] In the considered embodiment, the analog differentiator 2222 is again used to generate the output voltage V. out The derivative of the signal V is proportional to the derivative. D For example, in the considered embodiment, the analog differentiator 2222 is connected to the output voltage V. out Or the feedback signal FB and the reference voltage (e.g., ground or preferably reference voltage V) REF The capacitor C between) D and resistor R D Implementation. For example, when resistor R... D Connected to reference voltage V REF At that time, the derivative signal V D With V REF The offset, output voltage V out The derivative component is added to that offset.

[0084] In the considered embodiment, the derivative signal V D For example, capacitor C D and resistor R D The voltage at the intermediate node between them, and the reference voltage V REF This is provided to a third differential transconductor 2240, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2240 provides: a first current i D+ =i D0 +i D / 2; and the second current i D- =i D0 –i D / 2.

[0085] Specifically, in the differential transconductor 2240, the current i D+ and i D- The difference between i D =i D+ –i D- With each input voltage (i.e., reference voltage V) REF and derivative signal V D The difference between i and i is proportional, i. P =G MD (V REF –V D ).

[0086] Similar to Figure 8 Description of current i P+ and i D+ and / or current i P- and i D- This can be provided to the corresponding delay lines, for example: two delay lines connected in series (basically corresponding to delay lines 2224 and 2226) can be configured to operate according to the current i respectively. P- and i D- A delayed version of the clock signal CLK1, CLK1', is generated; and / or two series-connected delay lines can be configured to operate according to the current i. P+ and i D+ Generate a delayed version of the clock signal CLK2, CLK2'.

[0087] Generally speaking, the term "and / or" emphasizes the possibility of providing these delay lines for each clock signal (e.g., Figure 10 The differential method shown, or the possibility of providing these delay lines only for a single clock signal (such as...). Figure 8 (As shown).

[0088] Conversely, in the considered embodiment, the current i P+ and i D+It is provided to the first summing node, which in turn provides the current I. R =i P+ +i D+ , and / or current i P- and i D- It is provided to the second summing node, which in turn provides the current I. F =i P- +i D- In the considered embodiment, the current I R Provided to delay line 2235 and / or current I F Provided to delay line 2234, for example having according to the corresponding power supply current (i.e., current I) F and I R The delay level sequence of ) .

[0089] Therefore, in the considered embodiments and also as Figure 11 As shown, delay stage 2235 generates a delay t relative to clock signal CLK2. d2 The delayed clock signal CLK2', and / or the delay stage 2234 generates a delay t relative to the clock signal CLK1. d1 The delayed clock signal CLK1'.

[0090] In the considered embodiment, the delayed clock signals CLK2' and CLK1' are then provided to a phase detector, which is configured, for example, to set the signal DRV to a first logic level (e.g., high) on the rising edge of CLK2' and to set the signal DRV to a second logic level (e.g., low) on the rising edge of signal CLK1'.

[0091] Therefore, in the considered embodiment, in steady state, the feedback signal V FB Corresponding to the reference voltage V REF And by connecting the analog differentiator to the reference voltage V REF Signal V D Also corresponds to the reference voltage V REF Therefore, in steady state, the differential current i D i P and i I The delay t of delay line 2234 is zero, and (when using the differential method) the delay t is zero. d1 The delay t corresponding to delay line 2235 d2 Furthermore, oscillators 2220 and 2228 provide the same frequency and phase shift Φ. I The two clock signals are CLK1 and CLK2. Since delay lines 2234 and 2235 introduce the same delay t in the considered embodiment. d1 =td2 The phase shift Φ between the delayed clock signals CLK1' and CLK2' corresponds to Φ I For example, duration T ON Corresponding to delay Φ I (or proportional to it), for example, T ON =T SW (Φ I / 2π). Therefore, the duty cycle of the signal DRV is D = T. ON / T SW Corresponding to Φ I / 2π. For example, in a buck converter, the duty cycle can be (approximately) determined based on the input and output voltages, i.e., D = Φ. I / 2π=V out / V in .

[0092] As mentioned earlier, it is also possible to use only one of the delay lines 2234 or 2235, or one of the delay lines can introduce a constant delay, i.e., a delay t. d1 or t d2 One of them can be zero or at least constant. In fact, in this case, oscillators 2220 and 2228 will generate a phase shift Φ I The clock signal, which also compensates for the constant delay t d1 or t d2 Therefore, generally, in various embodiments, one or more first delay lines 2234 are connected between the oscillator 2220 and the phase detector 2230 and / or one or more second delay lines 2235 are connected between the oscillator 2228 and the phase detector 2230, wherein one or more first delay lines 2234 and / or one or more second delay lines 2235 are connected via current i P and i D drive.

[0093] As previously mentioned, in various embodiments, the feedback signal FB and the reference voltage V REF It is provided to the first differential transconductor 2236, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2236 provides: a first current i I +=i I0 +i I / 2; and the second current i I- =i I0 -i I / 2.

[0094] in this regard, Figure 12 The diagram shows the method for realizing current i I0 The above-described embodiments of the bias.

[0095] Specifically, in the considered embodiment, the differential transconductor 2236 provides only the differential component i I That is, the first (positive) terminal of the differential transconductor 2236 provides the first current i I / 2, where the first terminal is connected to the current-controlled oscillator 2228; the second (negative) terminal of the differential transconductor 2236 provides the first current -i I / 2, where the first terminal is connected to the current-controlled oscillator 2220.

[0096] In the considered embodiment, a current I is provided. BIAS+ =i I0 The first current source 2250 is therefore connected to the first terminal of the differential transconductor 2236, thereby the current-controlled oscillator 2228 receives current i I+ =i I0 +i I / 2. Similarly, provide current I BIAS- =i I0 The second current source 2252 is connected to the second terminal of the differential transconductor 2236, thereby the current-controlled oscillator 2220 receives current i. I- =i I0 -i I / 2.

[0097] Typically, the differential transconductor 2236 can also provide a common-mode current, which will also be added to the current supplied to the current-controlled oscillators 2220 and 2228. However, without loss of generality, this common-mode current is usually very small and will be ignored below. Therefore, ignoring the common-mode current provided by the differential transconductor 2236, the current-controlled oscillators 2220 and 2228 supply a common-mode current I... BIAS+ =I BIAS- Equal biases are applied such that in steady state (i.e., when the loop is closed), FB = V. REF The differential current i provided by the differential transconductor 2236 I The value is zero, meaning that the current-controlled oscillators 2220 and 2228 oscillate at the same frequency FSW. Therefore, the frequency F... SW It is nominally constant across the entire input and output voltage range and is determined solely by the bias current I. BIAS+ and I BIAS- (And the actual common-mode current of the differential transconductance 2236) is determined. This also applies to the single-ended configuration, where the differential amplifier 2236 supplies current I to only one of the current-controlled oscillators 2220 or 2228. I .

[0098] Conversely, focusing on delay lines 2234 and 2235, in steady state, the (differential) current i provided by (differential) transconductors 2238 and 2240...D and i P The delay is zero. Assuming the delay lines are matched, they all introduce the same delay t. d1 =t d2 Therefore, the same phase shift is introduced.

[0099] In this regard, in steady state, the regulator circuit should generate a PWM signal DRV, which ensures that the electronic converter generates the required output voltage V. out As mentioned earlier, in this case, the two oscillators 2220 and 2228 provide the same frequency F. SW The two clock signals CLK1 and CLK2 are used, and the phase shift Φ is related to the converter duty cycle DPWM, for example, in the case of buck converter and without considering efficiency:

[0100] D PWM =T ON / (T ON +T OFF ))=Φ / 2π=V out / V in

[0101] Similarly, it is important to note that the phase shift Φ is determined solely by the integral Φ I The effect determines the proportion Φ. P and derivative Φ P The effect only occurs during the transient period.

[0102] However, it should be noted that under steady-state conditions, the output voltage V out It may be subject to offset.

[0103] On the one hand, as mentioned earlier, a resistor divider R is typically used. FB1 and R FB2 A feedback signal FB is generated, which is provided to transconductor 2236 (and similarly transconductor 2238). Such a voltage divider may therefore introduce offset due to an unexpected divider ratio. However, due to the integral action, the regulator circuit changes the current I. I- and I I+ until the feedback signal FB corresponds to the reference voltage V REF Therefore, resistor R FB1 and R FB2 The mismatch between them is converted into adjusting the output voltage V. out The offset error. Similar problems may also exist in other feedback circuits 24, such as level shifters. This feedback mismatch is well known in the context of PID regulators and is not limited to time-based controllers. Although integrated resistors can match very well, the residual output voltage offset can be minimized using fine-tuning on the feedback divider 24 or other calibration methods.

[0104] On the other hand, in a time-based controller, the output voltage V out Another major source of the offset is the potentially unequal common-mode currents of the current-controlled oscillators 2220 and 2228. For example, when the bias current I... BIAS+ and I BIAS- When the currents are unequal, the control loop must account for this unbalanced bias of the current-controlled oscillators 2220 and 2228. Essentially, in this case, even in steady state, the control loop must provide a current I that is not zero. I This will cause the current I to be transferred again. I+ =I I- Applied to the current-controlled oscillator, thereby increasing the output voltage V out This introduces unwanted offsets.

[0105] Similar problems do not apply to delay lines (for proportional and derivative adjustments) because even with a delay of t... d1 and t d2 The currents may not be equal (e.g., due to unequal common-mode currents), but this effect is compensated by integral regulation and therefore does not affect the output offset.

[0106] In this respect, the offset introduced by such mismatched bias currents can also be quite large. Therefore, to reduce this voltage offset, bias current sources 2250 and 2252 should be matched.

[0107] For example, in various embodiments, current sources 2250 and 2252 can be implemented using two output stages of the same current mirror, where the two output transistors of the current mirror are matched transistors. However, in the same case, current I BIAS+ and I BIAS- It may not be a perfect match, and for example, it may require a current I. BIAS+ and I BIAS- Fine-tuning or calibration operations.

[0108] Unfortunately, the nominal operating frequency F of this time-based regulator circuit is limited. SW It should typically be configurable, for example, programmable, which therefore means that current sources 2250 and 2252 should also provide a configurable current I. BIAS+ and I BIAS- For example, in various embodiments, current generators 2250 and 2252 may be variable current generators, wherein current I... BIAS+ and I BIAS- The value is settable / programmable, for example, based on a digital or analog control signal. For example, in the case of a current mirror with two output transistors, the current fed to the input stage of the current mirror can be settable.

[0109] For example, such programming may be necessary due to changing operating conditions, and it can often be executed dynamically (i.e., on-demand, in real-time). This translates to the fact that the frequency F typically varies with the operating frequency. SW The output adjustment offset changes.

[0110] Furthermore, the current offset between current sources 2250 and 2252 is typically process-voltage-temperature (PVT) dependent. Therefore, a robust solution is needed to avoid this uncontrolled output offset under various operating conditions of the regulator circuit 220a.

[0111] In this regard, simply performing a trimming action to compensate for this offset may therefore be practically impossible, especially in the multiple application scenarios mentioned above. Furthermore, trimming solutions are by definition very time-consuming and add extra costs to the final testing. Finally, trimming solutions are generally not robust and reliable because they are open-loop solutions that do not account for temperature variations, aging, and all other possible phenomena that may occur after final testing (e.g., packaging and assembly, soldering, etc.). Moreover, the discrete and finite nature of trimming actions typically does not allow for achieving zero residuals.

[0112] Figure 13 Examples of different solutions are shown.

[0113] As mentioned earlier, the current I BIAS+ and I BIAS- Mismatches between them are often unavoidable, especially under all operating conditions.

[0114] In the considered embodiment, regulator circuit 220a is configured to perform averaging operation of the bias current supplied to current-controlled oscillators 2220 and 2228. Specifically, time-based averaging is used for this purpose, wherein 50% of the current I supplied to current-controlled oscillator 2220 is provided over a given time period. BIAS+ And provides 50% of the current I to the current-controlled oscillator 2228. BIAS+ Similarly, 50% of the current I is supplied to the current-controlled oscillator 2228. BIAS- And provides 50% of the current I to the current-controlled oscillator 2220. BIAS- .

[0115] For example, this is in Figure 13 The diagram schematically shows that current generators 2250 and 2252 are connected to the output terminals of differential transconductor 2236, i.e., the input terminals of current-controlled oscillators 2220 and 2228, via a switching circuit 2254, such as a butterfly switching circuit.

[0116] Therefore, as Figure 14As schematically shown, this switching circuit 2254 includes four terminals, wherein: terminal N1 is connected to the positive output terminal of transconductor 2236 / current-controlled oscillator 2228; terminal N2 is connected to the negative output terminal of transconductor 2236 / current-controlled oscillator 2220; terminal N3 is connected to current generator 2250; and terminal N4 is connected to current generator 2252.

[0117] Furthermore, the switching circuit 2254 is configured such that: under a first switching condition, terminal N1 is connected to terminal N4, i.e., current generator 2252 is connected to oscillator 2228, and terminal N2 is connected to terminal N3, i.e., current generator 2250 is connected to oscillator 2220; and under a second switching condition, terminal N1 is connected to terminal N3, i.e., current generator 2250 is connected to oscillator 2228, and terminal N2 is connected to terminal N4, i.e., current generator 2252 is connected to oscillator 2220.

[0118] For example, such as Figure 14 As schematically shown, for this purpose, the switching circuit 2254 may include two bias switches SW1 and SW2. For example, the bias switches may be implemented using two electronic switches (e.g., FETs).

[0119] As mentioned earlier, the switching between these two switching conditions should be performed based on the logic level of a PWM signal (e.g., clock signal CLK) with a 50% duty cycle.

[0120] In this implementation embodiment, averaging can be performed using a frequency maintained outside the bandwidth of the control loop, i.e., such that the averaging process should not affect the control loop. It should be noted that the clock signal CLK should not be too high so that the current supplied to oscillators 2220 and 2228 can properly stabilize within (at least) half of the clock cycle.

[0121] In an exemplary embodiment, the clock signal CLK may correspond to one of the clock signals already used in the regulator circuit 220a, such as clock signal CLK1 or clock signal CLK2 generated by oscillators 2220 and 2228, respectively. In this respect, the choice of clock signal CLK1 or clock signal CLK2 is fairly irrelevant, since the two clock signals should have the same frequency in a steady state. Typically, the clock signal CLK may also correspond to a reduced version of clock signal CLK1 or CLK2; that is, the clock signal CLK may be generated via a frequency divider that receives clock signal CLK1 or CLK2 at the input, whereby the period of the clock signal CLK is a multiple of the period of clock signal CLK1 or CLK2.

[0122] On the one hand, this avoids the need for an additional clock generator. On the other hand, it ensures that the average operation is consistent with the converter switching frequency F.SW Automatic execution occurs at a frequency typically higher than the loop bandwidth. In this way, if the DC-DC converter supports different switching frequencies F... SW (That is, the different common-mode bias currents I supplying power to oscillators 2220 and 2228) BIAS+ and I BIAS- If the averaging action is not recalibrated / retuned, it will not require recalibration / retuning because it remains consistent with the DC-DC switching frequency F. SW Automatic alignment.

[0123] Therefore, the proposed solution allows for the avoidance of mismatch and non-idealities in the common-mode current generators 2250 and 2252, thereby ensuring current I I- and I I+ The steady-state average value, which corresponds to AVG(I) I- ) = AVG(I I+ Therefore, the negative feedback loop does not need to provide any balancing action, so the (differential) current I provided by the transconductor 2236 is... I It remains zero in steady state (i.e., I0). I =0). This also means the output voltage V out The mismatch will not cause imbalance.

[0124] In various embodiments, the proposed solution is automatically consistent and automatically performs averaging to ensure stable zeroing of the output offset. As an averaging-based solution, the output offset is eliminated regardless of any PVT variations, aging, component derating, or any other phenomena that may occur after final testing and packaging / assembly. Therefore, this solution is effective relative to operating conditions, particularly the switching frequency F. SW Input and output voltage V in and V out And the inductor L of switching stage 26 26 and capacitor C 26 The value of the gain G, and the selection of loop compensation, especially the gain G of the transconductor 2236. mI It is stable.

[0125] It should be noted that the proposed solution has almost no impact on quiescent current consumption (efficiency and power consumption). In fact, in various embodiments, the solution only requires actuating the butterfly switch 2254, without any other complex analog or digital circuitry. Furthermore, in various embodiments, there is no need to generate a separate clock signal CLK. Therefore, in terms of system complexity and scope, there is essentially no substantial difference regarding implementations without the proposed solution.

[0126] It will also be noted that the proposed solution improves not only the static performance of the converter but also its dynamic performance. In fact, without bias current matching, transconductor 2236 would remain unbalanced in steady state. Therefore, transconductor 2236 would be forced to operate under bias conditions that inherently exacerbate its nonlinearity and emphasize its non-ideal nature. Nonlinearity within the loop negatively impacts the overall DC-DC transient response and should always be minimized. Instead, by utilizing the proposed averaging solution, the difference in common-mode bias current I due to the oscillators 2220 and 2228 is mitigated. BIAS+ and I BIAS- This causes an imbalance in the transconductor 2236, and thus improves the system linearity and the converter transient response.

[0127] Finally, as previously stated, current generators 2250 and 2252 can be implemented as two output stages of the same current mirror. In this respect, the proposed solution allows the current mirror to have a less complex design, since the larger mismatch between the output stages of the current mirror is also compensated for by the disclosed average operation.

[0128] Of course, without prejudice to the principles of the invention, the details of the structure and embodiments may vary considerably from what is described and shown herein purely by way of example, without departing from the scope of the invention as defined by the appended claims.

[0129] For example, although the preceding embodiments have been described with respect to PID controllers, these embodiments primarily involve implementing the I component using transconductor 2236 and current-controlled oscillators 2220 and 2228. Therefore, the D and / or P components are entirely optional. For example, this means that one or even both of transconductors 2238 and 2240 can be omitted.

[0130] Furthermore, these solutions can also be applied by simply replacing oscillators 2220 and 2228 with current-controlled oscillators. Figure 8 The PID controller is shown. For example, this means that a voltage-controlled delay line can also be used. Furthermore, instead of using a differential amplifier, a single-ended configuration can also be used for one or more of the components P, I, and D.

[0131] The claims form part of the technical teachings described herein.

Claims

1. A control circuit for a switching stage of an electronic converter configured to provide an output voltage, the control circuit comprising: The first terminal is configured to provide a drive signal to the corresponding electronic switch of the switching stage; The second terminal is configured to receive a first feedback signal proportional to the output voltage from the feedback circuit. The driver circuit is configured to generate the drive signal based on the pulse width modulation (PWM) signal; as well as A PWM signal generator circuit is configured to generate the PWM signal based on the first feedback signal and a reference voltage, wherein the PWM signal generator circuit includes: A first current-controlled oscillator has an input terminal configured to receive a first current and generate a first clock signal based on the first current. The second current-controlled oscillator has an input terminal configured to receive a second current and generate a second clock signal according to the second current; A first operational transconductance amplifier is configured to provide a third current at its first amplifier output, the third current indicating the difference between the reference voltage and the first feedback signal, wherein the first amplifier output of the first operational transconductance amplifier is connected to the input terminal of the first current-controlled oscillator; and A phase detector has inputs coupled to the first current-controlled oscillator and the second current-controlled oscillator, and provides the PWM signal at the output; The PWM signal generator circuit further includes: A first bias current generator is configured to provide a first bias current at a first bias output; A second bias current generator is configured to provide a second bias current at the second bias output; and The switching circuit is configured to receive a switching clock signal, and: When the logic level of the switching clock signal has a first logic level, the first bias output of the first bias current generator is connected to the input terminal of the first current-controlled oscillator, and the second bias output of the second bias current generator is connected to the input terminal of the second current-controlled oscillator. When the logic level of the switching clock signal has a second logic level, the first bias output of the first bias current generator is connected to the input terminal of the second current-controlled oscillator, and the second bias output of the second bias current generator is connected to the input terminal of the first current-controlled oscillator.

2. The control circuit according to claim 1, wherein the switching clock signal is derived from the first clock signal or the second clock signal.

3. The control circuit according to claim 2, wherein the switching clock signal corresponds to one of the first clock signal or the second clock signal.

4. The control circuit according to claim 1, wherein the PWM signal generator circuit further comprises: A first delay line is connected between the first current-controlled oscillator and the phase detector, and The second delay line is connected between the second current-controlled oscillator and the phase detector.

5. The control circuit of claim 4, wherein one or more of the first delay line and the second delay line are driven according to the difference between the reference voltage and the first feedback signal.

6. The control circuit of claim 4, comprising a terminal configured to receive a second feedback signal proportional to the derivative of the output voltage from the analog differentiator, wherein, One or more of the first and second delay lines are driven according to the difference between the reference voltage and the second feedback signal.

7. The control circuit according to claim 6, comprising at least one of the following: The one or more electronic switches of the switching stage; The feedback circuit; and The analog differentiator.

8. The control circuit of claim 6, wherein each of the first delay line and the second delay line is a current-controlled delay line, and wherein, The PWM signal generator circuit also includes: A second operational transconductance amplifier is configured to generate a fourth current, the fourth current indicating the difference between the reference voltage and the first feedback signal; A third operational transconductance amplifier is configured to generate a fifth current, the fifth current indicating the difference between the reference voltage and the second feedback signal; The fourth current and the fifth current are provided to one or more of the first delay line and the second delay line.

9. The control circuit of claim 1, wherein the first operational transconductance amplifier is a differential operational transconductance amplifier configured to provide a sixth current at the output of the second amplifier, wherein the difference between the sixth current and the third current is proportional to the difference between the reference voltage and the first feedback signal, and wherein, The second amplifier output of the first operational transconductance amplifier is connected to the input terminal of the second current-controlled oscillator.

10. The control circuit according to claim 1, wherein the electronic converter is a buck or boost converter.

11. The control circuit of claim 1, wherein the frequency of the switching clock signal is outside the bandwidth of the control loop used by the control circuit.

12. An integrated circuit comprising the control circuit according to claim 1.

13. An electronic converter, comprising: Switching levels, and The control circuit according to claim 1.

14. A control circuit for a switching stage of an electronic converter configured to generate an output voltage, the control circuit comprising: A feedback circuit is configured to generate a feedback signal from the output voltage; An operational transconductance amplifier is configured to generate a first output current and a second output current in response to the difference between a reference voltage and the feedback signal; A first current-controlled oscillator has an input coupled to receive the first output current and configured to generate a first clock signal; A second current-controlled oscillator has an input coupled to receive the second output current and configured to generate a second clock signal; A phase detector circuit is configured to generate a drive signal for the switching stage of the electronic converter in response to the phase difference between the first clock signal and the second clock signal. A first bias current generator is configured to generate a first bias current; A second bias current generator is configured to generate a second bias current; as well as The switching circuit is controlled by a switching clock signal to: When the switching clock signal has a first logic level, the first bias current is applied to the input of the first current-controlled oscillator, and the second bias current is applied to the input of the second current-controlled oscillator. When the switching clock signal has a second logic level, the second bias current is applied to the input of the first current-controlled oscillator, and the first bias current is applied to the input of the second current-controlled oscillator.

15. The control circuit of claim 14, wherein the frequency of the switching clock signal is outside the bandwidth of the control loop used in the control circuit.

16. The control circuit according to claim 14, wherein the switching clock signal is derived from the first clock signal.

17. The control circuit of claim 14, wherein the switching clock signal is derived from the second clock signal.

18. The control circuit according to claim 14, wherein the switching clock signal corresponds to the first clock signal.

19. The control circuit according to claim 14, wherein the switching clock signal corresponds to the second clock signal.

20. The control circuit of claim 14, wherein the electronic converter is a buck or boost converter.

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