latch circuit, frequency divider, and hs-mmd

Abstract

The application provides a latch circuit, a divide-by-two, divide-by-three and divide-by-five circuit and an HS-MMD, which comprises a first tri-state gate, a second tri-state gate and a first inverter; an input end of the first tri-state gate is a first input end of the latch circuit, a control end of the first tri-state gate is a second input end of the latch circuit, the control end of the first tri-state gate is used for receiving a first clock signal, an output end of the first tri-state gate is an output end of the latch circuit, the output end of the first tri-state gate is also connected to an input end of the first inverter, an output end of the first inverter is connected to a first input end of the second tri-state gate, an output end of the second tri-state gate is connected to the output end of the first tri-state gate, and a second input end of the second tri-state gate is used for receiving a second clock signal. The application does not need to set a high-speed pre-divider, the MMD can directly process signals from a VCO, is beneficial to the modular integration of a PLL, and improves the integration degree of the PLL.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a latch circuit, a two-to-three frequency divider, and an HS-MMD. Background Technology

[0002] Phase-locked loops (PLLs) are widely used in various clock circuits to provide clock references for other chips and to modulate and demodulate signals. The feedback divider is one of the main modules within the PLL. It divides the high-speed signal from the voltage-controlled oscillator (VCO) and sends the divided signal to a phase-frequency detector (PFD). The PFD compares the frequency and phase of the divided signal with the input reference frequency, continuously adjusting the VCO frequency to ultimately lock the PLL loop.

[0003] Currently, a multi-modulus divider (MMD) is typically used as the feedback divider, and an additional high-speed prescaler is required to prescale the signal before inputting it to the MMD.

[0004] However, the additional high-speed prescaler is not conducive to the modular integration of PLL, resulting in a low degree of integration of PLL. Summary of the Invention

[0005] This invention provides a latch circuit, a two-to-three frequency divider, and an HS-MMD to solve the problem of low integration level of PLLs in the prior art.

[0006] This invention provides a latch circuit, comprising: a first tri-state gate, a second tri-state gate, and a first inverter;

[0007] The input terminal of the first tri-state gate serves as the first input terminal of the latch circuit, the control terminal of the first tri-state gate serves as the second input terminal of the latch circuit, the control terminal of the first tri-state gate is used to receive a first clock signal, the output terminal of the first tri-state gate serves as the output terminal of the latch circuit, the output terminal of the first tri-state gate is also connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the second tri-state gate, the output terminal of the second tri-state gate is connected to the output terminal of the first tri-state gate, and the second input terminal of the second tri-state gate is used to receive a second clock signal.

[0008] According to a latch circuit provided by the present invention, the latch circuit further includes a buffer;

[0009] The output of the first tri-state gate is used as the output of the latch circuit through the buffer.

[0010] According to a latch circuit provided by the present invention, at least one of the first tri-state gate, the second tri-state gate, and the first inverter adopts an ultra-low threshold voltage (ULVT) type MOS transistor.

[0011] The present invention also provides a divide-and-divide frequency converter based on a latch circuit, comprising:

[0012] The first logic module, the second logic module, the third logic module, the fourth logic module, the first latch circuit, the second latch circuit, the third latch circuit, and the fourth latch circuit are latch circuits as described in any of the above embodiments;

[0013] The first input terminal of the first logic module serves as the output terminal of the latch circuit-based frequency divider. The output terminal of the first logic module is connected to the first input terminal of the first latch circuit. The second input terminal of the first latch circuit is used to receive a first clock signal. The output terminal of the first latch circuit is connected to the first input terminal of the second latch circuit. The second input terminal of the second latch circuit is used to receive a third clock signal. The output terminal of the second latch circuit is connected to the input terminal of the second logic module. The output terminal of the second logic module is connected to the first input terminal of the first logic module. The output terminal of the second latch circuit is also connected to the first input terminal of the third logic module. The second input terminal of the third logic module is used to receive an adjustment signal. The output terminal of the third logic module is connected to the first input terminal of the third latch circuit. The second input terminal of the third latch circuit is used to receive the first clock signal. The output terminal of the third latch circuit is connected to the first input terminal of the fourth logic module. The second input terminal of the fourth logic module is used to receive a control signal. The output terminal of the fourth logic module is connected to the first input terminal of the fourth latch circuit. The second input terminal of the fourth latch circuit is used to receive the third clock signal. The output terminal of the fourth latch circuit is connected to the second input terminal of the first logic module.

[0014] According to the present invention, a latch circuit-based frequency divider is provided, wherein the first logic module is configured to output a high level through the output terminal of the first logic module when the first input terminal of the first logic module is at a low level and the second input terminal of the first logic module is at a low level.

[0015] According to the present invention, a latch circuit-based divide-and-conquer frequency divider is provided, wherein the second logic module is used to: output a high level through the output terminal of the second logic module when the input terminal of the second logic module is at a low level; and output a low level through the output terminal of the second logic module when the input terminal of the second logic module is at a high level.

[0016] According to the present invention, a latch circuit-based frequency divider is provided, wherein the third logic module is used to output a low level through the output terminal of the third logic module when the first input terminal of the third logic module is at a high level and the second input terminal of the third logic module is at a high level.

[0017] According to the present invention, a latch circuit-based frequency divider is provided, wherein the fourth logic module is used to output a low level through the output terminal of the fourth logic module when the first input terminal of the fourth logic module is at a high level and the second input terminal of the fourth logic module is at a high level.

[0018] According to the present invention, a latch circuit-based frequency divider is provided, wherein the first logic module includes a NOR gate;

[0019] The first input terminal of the NOR gate serves as the first input terminal of the first logic module, the second input terminal of the NOR gate serves as the second input terminal of the first logic module, and the output terminal of the NOR gate serves as the output terminal of the first logic module.

[0020] According to the present invention, a latch circuit-based frequency divider is provided, wherein the first logic module includes an AND gate and a second inverter;

[0021] The first input terminal of the AND gate serves as the first input terminal of the first logic module, the second input terminal of the AND gate is connected to the output terminal of the second inverter, the input terminal of the second inverter serves as the second input terminal of the first logic module, and the output terminal of the AND gate serves as the output terminal of the first logic module.

[0022] According to the present invention, a latch circuit-based frequency divider is provided, wherein the second logic module includes a third inverter;

[0023] The input terminal of the third inverter serves as the input terminal of the second logic module, and the output terminal of the third inverter serves as the output terminal of the second logic module.

[0024] According to the present invention, a latch circuit-based frequency divider is provided, wherein the third logic module includes a first NAND gate;

[0025] The first input terminal of the first NAND gate serves as the first input terminal of the third logic module, the second input terminal of the first NAND gate serves as the second input terminal of the third logic module, and the output terminal of the first NAND gate serves as the output terminal of the third logic module.

[0026] According to the present invention, a latch circuit-based frequency divider is provided, wherein the fourth logic module includes a second NAND gate;

[0027] The first input terminal of the second NAND gate serves as the first input terminal of the fourth logic module, the second input terminal of the second NAND gate serves as the second input terminal of the fourth logic module, and the output terminal of the second NAND gate serves as the output terminal of the fourth logic module.

[0028] The present invention also provides a high-speed multimode divider HS-MMD, comprising: N two-to-three dividers connected in series, where N is an integer greater than 1, and the first two-to-three divider among the N two-to-three dividers is the two-to-three divider based on the latch circuit described in any of the above embodiments.

[0029] The latch circuit, divide-and-divide frequency converter, and HS-MMD provided by this invention address the issue that in related technologies, an additional high-speed prescaler is required to prescale the high-speed signal from the VCO before inputting the signal to the MMD. This is mainly due to the high transmission delay of the MMD. The latch circuit provided in this embodiment of the invention places the inverter on the transmission path of the latch circuit in the MMD of the related technologies on the feedback branch of the latch circuit. While ensuring the function of the latch circuit, it effectively reduces the transmission delay of the latch circuit, thereby effectively reducing the transmission delay of the MMD. It eliminates the need for a high-speed prescaler, and the MMD can directly process the signal from the VCO, which is beneficial for the modular integration of the PLL and improves the integration level of the PLL. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 This is one of the structural schematic diagrams of the latch circuit provided by the present invention;

[0032] Figure 2 This is a schematic diagram of the structure of a PLL loop in related technologies;

[0033] Figure 3 This is a schematic diagram of the structure of MMD in related technologies;

[0034] Figure 4 This is a schematic diagram of the structure of a two-way frequency divider in related technologies;

[0035] Figure 5 This is a schematic diagram of the latch structure in related technologies;

[0036] Figure 6 This is the second schematic diagram of the latch circuit provided by the present invention;

[0037] Figure 7 This is one of the structural schematic diagrams of a two-to-three frequency divider based on a latch circuit provided by the present invention;

[0038] Figure 8 This is the second schematic diagram of the structure of the two-third frequency divider based on the latch circuit provided by the present invention;

[0039] Figure 9 This is the third schematic diagram of the structure of the two-three frequency divider based on the latch circuit provided by the present invention;

[0040] Figure 10 This is the fourth schematic diagram of the structure of the two-third frequency divider based on the latch circuit provided by the present invention;

[0041] Figure 11 This is a schematic diagram of the output waveform of MMD when clk is 8GHz, provided by the present invention;

[0042] Figure 12 This is a schematic diagram of the output waveform of MMD when clk is 15GHz, provided by the present invention.

[0043] Figure label:

[0044] 100: Latch circuit; 200: Two-way divider based on latch circuit;

[0045] 101: First tri-state gate; 102: Second tri-state gate; 103: First inverter; 104: Buffer;

[0046] 201: First logic module; 202: Second logic module; 203: Third logic module; 204: Fourth logic module; 205: First latch circuit; 206: Second latch circuit; 207: Third latch circuit; 208: Fourth latch circuit. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0048] The latch circuit, frequency divider, and MMD of the present invention are described below with reference to the accompanying drawings.

[0049] Figure 1 This is one of the structural schematic diagrams of the latch circuit provided by the present invention, such as... Figure 1 As shown, the latch circuit 100 includes: a first tri-state gate 101, a second tri-state gate 102, and a first inverter 103;

[0050] The circuit connection structure of latch circuit 100 is as follows:

[0051] The input terminal of the first tri-state gate 101 serves as the first input terminal of the latch circuit 100, and the control terminal of the first tri-state gate 101 serves as the second input terminal of the latch circuit 100. The control terminal of the first tri-state gate 101 is used to receive the first clock signal clk. The output terminal of the first tri-state gate 101 serves as the output terminal of the latch circuit 100. The output terminal of the first tri-state gate 101 is also connected to the input terminal of the first inverter 103. The output terminal of the first inverter 103 is connected to the first input terminal of the second tri-state gate 102, and the output terminal of the second tri-state gate 102 is connected to the output terminal of the first tri-state gate 101. The second input terminal of the second tri-state gate 102 is used to receive the second clock signal clkn.

[0052] The relevant technologies will be introduced below:

[0053] Figure 2 This is a schematic diagram of the structure of a PLL loop in related technologies, such as... Figure 2As shown, the PFD simultaneously receives the input reference frequency signal (ck_ref signal) and the feedback signal (ck_fb signal), continuously compares the frequency and phase of these two signals, and inputs the processed signal to the charge pump (CP). The CP then outputs the processed signal to the VCO, and the VCO outputs the ck_out signal. In addition, the Feedback Divider divides the high-speed signal output by the VCO and uses the divided signal as the ck_fb signal, which is sent to the PFD to compare the frequency and phase with the ck_ref signal, continuously adjusting the VCO frequency, and finally locking the PLL loop.

[0054] It's important to note that when using an MMD as a Feedback Divider, the typical architecture of a PLL loop for processing the VCO output frequency is as follows: the signal is first divided by a high-speed prescaler before being input to the Feedback Divider. Therefore, the input frequency that the MMD divider itself can handle cannot be very high. However, adding an extra high-speed prescaler and having multiple modules is not conducive to PLL modular integration; moreover, the MMD structure itself must ensure the correctness of the division result by guaranteeing the state cycle of the divider within the division cycle, and must have the same cyclic logic as the subsequent divider. Therefore, high-speed dividers such as True Single-Phase Clocks (TPSCs) cannot be used as the internal structure of the MMD.

[0055] The structure of MMD in related technologies is described below. Figure 3 This is a structural diagram of MMD in related technologies, such as Figure 3 As shown, the MMD is composed of multiple stages of frequency dividers (DIV2_3) connected in series. Specifically, it consists of stage 0 (DIV2_3), stage 1 (DIV2_3) to stage n (DIV2_3) connected in series. Stage 0 (DIV2_3) receives the first clock signal clk and outputs the processed data to stage 1 (DIV2_3), and so on, until it reaches stage n (DIV2_3). The output of stage n (DIV2_3) is used as the output of the MMD. Furthermore, stage 0 (DIV2_3), stage 1 (DIV2_3) to stage n (DIV2_3) also receive corresponding control signals P. <0> P <1> To P <n>Additionally, the nth level DIV2_3 will adjust the signal modi. <n>Returning to the previous level DIV2_3, and so on, until the transmission reaches level 0 DIV2_3, where level 0 DIV2_3 outputs the adjustment signal modi. <0> .

[0056] Figure 4 This is a schematic diagram of the structure of a two-to-three frequency divider in related technologies, such as... Figure 4 As shown, the divider consists of four latches and logic gates forming a divider loop. Each stage of the divider can achieve either a 2-fold or a 3-fold frequency division, specifically achieved by the adjustment signal modi and the control signal P. When both modi and P are high, it exhibits a 3-fold frequency division; otherwise, it performs a 2-fold frequency division.

[0057] It should be noted that the modo signal in the diagram represents the output position of the control signal for the second and third frequency division of this stage, for example... Figure 3 The first level of modi <2> The input modi signal, modi <1> This is the output modo signal.

[0058] A single-stage MMD includes a 2 / 3 divider, where the 3-divide period is one more input signal cycle than the 2-divide period. For an n-stage MMD, the weight of the added cycle in the nth stage is twice that of the (n-1)th stage, so the maximum number of added cycles in an n-stage MMD is 1 + 2. 1 +2 2 +…+2 n-1 =2 n -1;

[0059] For an n-level MMD, the minimum division ratio is 2. n Adding the above-mentioned increase in the number of cycles can achieve a frequency division ratio of 2. n ~2 n+1 Consecutive integers between -1 and 1. A frequency division ratio extension technique can be used to lock the higher-order stages to allow for variations in the stage number n, thus achieving a wide range of integer frequency division ratios.

[0060] Figure 5 This is a schematic diagram of the latch structure in related technologies, such as... Figure 5 As shown, the latch in the related technology includes two tri-state gates, an inverter and a buffer. The buffer can be understood as being composed of two inverters. It can be seen that the input transmission path of the traditional latch signal needs to go through multiple inverters, resulting in a high delay generated by the latch.

[0061] This invention proposes a high-speed multi-modulus divider (HS-MMD). For the MMD, the highest-speed signal processing occurs in the first-stage 2 / 3 divider. Since the output frequency of the first-stage 2 / 3 divider is already the frequency after 2 / 3 or 3 / 2 division, the design focus can be on the loop of the first-stage 2 / 3 divider. The HS-MMD optimizes the logic gates of the first-stage signal transmission loop and reduces the transmission delay of the latch circuit by optimizing the latch circuit. The HS-MMD has a maximum input frequency of up to 15 GHz and can directly process high-speed signals input to the VCO without the need for an additional high-speed prescaler.

[0062] In this embodiment of the invention, the latch circuit in the first-stage divider / divider was redesigned, and a minimum delay latch structure was proposed. For high-speed signals processed by the divider, the lower the transmission delay of the signal within the divider loop, the better.

[0063] like Figure 1 and Figure 5 As shown, compared to the structure of the latch circuit in related technologies, the embodiment of the present invention moves the first inverter on the transmission path of the latch circuit to the feedback branch of the latch circuit and removes the buffer on the transmission path of the latch circuit to achieve the lowest latency of the latch circuit.

[0064] It should be noted that the latch circuit in this embodiment of the invention minimizes the number of logic gates from data input to output while ensuring the functionality of the latch circuit, thereby reducing the input-to-output delay to the greatest extent. As can be seen, in the structure of the latch circuit in this embodiment of the invention, the delay from the input terminal d to the output terminal Qn of the latch circuit is only through the delay of a single inverter (first tri-state gate). Compared with the delay of the four-stage inverter in the traditional structure, this embodiment of the invention reduces the transmission delay by 75%.

[0065] In addition, the first inverter and the first tri-state gate, which are not on the main data transmission path, still constitute a first-level buffer, which can provide a stable level when the latch is held by clk, thus ensuring the data retention function of the latch.

[0066] In the latch circuit provided in this embodiment of the invention, in related technologies, an additional high-speed prescaler is required to prescale the high-speed signal from the VCO before inputting the signal to the MMD. This is mainly because the MMD has high transmission delay. The latch circuit provided in this embodiment of the invention places the inverter on the transmission path of the latch circuit in the MMD in the feedback branch of the latch circuit. While ensuring the function of the latch circuit, the transmission delay of the latch circuit is effectively reduced, thereby effectively reducing the transmission delay of the MMD. It eliminates the need for a high-speed prescaler, and the MMD can directly process the signal from the VCO, which is beneficial for the modular integration of the PLL and improves the integration level of the PLL.

[0067] Optionally, Figure 6 This is the second schematic diagram of the latch circuit provided by the present invention, as shown below. Figure 6 As shown, the latch circuit 100 also includes a buffer 104;

[0068] The output of the first tri-state gate 101 is used as the output of the latch circuit 100 through the buffer 104.

[0069] Specifically, adding a buffer between the first tri-state gate and the output of the latch circuit can further improve the stability of the latch circuit's output level and ensure the latch circuit's data retention function.

[0070] Optionally, at least one of the first tri-state gate, the second tri-state gate, and the first inverter uses an ultra-low voltage (ULVT) type MOSFET.

[0071] Specifically, compared to using MOSFETs of type LVT, at least one of the logic gates in the first tri-state gate, the second tri-state gate, and the first inverter in this embodiment of the invention uses an ULVT type MOSFET, which can reduce the delay of the logic gate and improve the speed.

[0072] On the other hand, the present invention also provides a two-to-three frequency divider based on a latch circuit.

[0073] Figure 7 This is one of the structural schematic diagrams of the two-thirds frequency divider based on the latch circuit provided by the present invention, as shown below. Figure 7 As shown, the latch circuit-based divider / divider 200 includes: a first logic module 201, a second logic module 202, a third logic module 203, a fourth logic module 204, a first latch circuit 205, a second latch circuit 206, a third latch circuit 207, and a fourth latch circuit 208. The first latch circuit 205, the second latch circuit 206, the third latch circuit 207, and the fourth latch circuit 208 are latch circuits 100 mentioned in any of the above embodiments.

[0074] The circuit connection structure of the two-way frequency divider based on the latch circuit is described in detail below:

[0075] The first input terminal of the first logic module 201 serves as the output terminal (output) of the latch circuit-based divide-and-conqueror 200. The output terminal of the first logic module 201 is connected to the first input terminal of the first latch circuit 205. The second input terminal of the first latch circuit 205 receives a first clock signal (clk). The output terminal of the first latch circuit 205 is connected to the first input terminal of the second latch circuit 206. The second input terminal of the second latch circuit 206 receives a third clock signal (clkb). The output terminal of the second latch circuit 206 is connected to the input terminal of the second logic module 202. The output terminal of the second logic module 202 is connected to the first input terminal of the first logic module 201. The output terminal of the second latch circuit 206 is also connected to... The third logic module 203 has a first input terminal, a second input terminal for receiving an adjustment signal modi, an output terminal for being connected to the first input terminal of the third latch circuit 207, a second input terminal for receiving the first clock signal, an output terminal for being connected to the first input terminal of the fourth logic module 204, a second input terminal for receiving a control signal P, an output terminal for being connected to the first input terminal of the fourth latch circuit 208, a second input terminal for receiving the third clock signal, and an output terminal for being connected to the second input terminal of the first logic module 201.

[0076] Optionally, the first logic module 201 is configured to output a high level through the output terminal of the first logic module 201 when the first input terminal of the first logic module 201 is at a low level and the second input terminal of the first logic module 201 is at a low level.

[0077] Specifically, when both the first and second input terminals of the first logic module are at a low level, the first logic module outputs a high level through its output terminal; otherwise, the first logic module outputs a low level through its output terminal.

[0078] Optionally, the second logic module 202 is configured to: output a high level through the output terminal of the second logic module 202 when the input terminal of the second logic module 202 is at a low level; and output a low level through the output terminal of the second logic module 202 when the input terminal of the second logic module 202 is at a high level.

[0079] Specifically, when the input terminal of the second logic module is at a low level, the output terminal of the second logic module outputs a high level; when the input terminal of the second logic module is at a high level, the output terminal of the second logic module outputs a low level.

[0080] Optionally, the third logic module 203 is configured to output a low level through the output terminal of the third logic module 203 when the first input terminal of the third logic module 203 is at a high level and the second input terminal of the third logic module 203 is at a high level.

[0081] Specifically, when both the first and second input terminals of the third logic module are at a high level, the third logic module outputs a low level through its output terminal; otherwise, the third logic module outputs a high level through its output terminal.

[0082] Optionally, the fourth logic module 204 is configured to output a low level through its output terminal when the first input terminal of the fourth logic module 204 is at a high level and the second input terminal of the fourth logic module 204 is at a high level.

[0083] When both the first and second input terminals of the fourth logic module are at a high level, the fourth logic module outputs a low level through its output terminal. Otherwise, the fourth logic module outputs a high level through its output terminal.

[0084] It should be noted that the third clock signal clkb is the result of inverting the first clock signal clk; the adjustment signal modi is the output signal of the next stage two-three frequency divider.

[0085] Optionally, a specific implementation of the first logic module may be provided. Figure 8 This is the second schematic diagram of the two-thirds frequency divider based on the latch circuit provided by the present invention, as shown below. Figure 8 As shown, the first logic module 201 includes NOR gates;

[0086] The first input terminal of the NOR gate serves as the first input terminal of the first logic module 201, the second input terminal of the NOR gate serves as the second input terminal of the first logic module 201, and the output terminal of the NOR gate serves as the output terminal of the first logic module 201.

[0087] Optionally, another specific implementation of the first logic module is provided. Figure 9 This is the third schematic diagram of the two-three frequency divider based on the latch circuit provided by the present invention, as shown below. Figure 9 As shown, the first logic module 201 includes an AND gate and a second inverter;

[0088] The first input terminal of the AND gate serves as the first input terminal of the first logic module 201, the second input terminal of the AND gate is connected to the output terminal of the second inverter, the input terminal of the second inverter serves as the second input terminal of the first logic module 201, and the output terminal of the AND gate serves as the output terminal of the first logic module 201.

[0089] Optionally, a specific implementation of the second logic module may be provided, such as Figure 8 As shown, the second logic module 202 includes a third inverter;

[0090] The input terminal of the third inverter serves as the input terminal of the second logic module 202, and the output terminal of the third inverter serves as the output terminal of the second logic module 202.

[0091] Optionally, a specific implementation of the third logic module may be provided, such as Figure 8 As shown, the third logic module 203 includes a first NAND gate;

[0092] The first input terminal of the first NAND gate serves as the first input terminal of the third logic module 203, the second input terminal of the first NAND gate serves as the second input terminal of the third logic module 203, and the output terminal of the first NAND gate serves as the output terminal of the third logic module 203.

[0093] Optionally, a specific implementation of the fourth logic module is provided, such as Figure 8 As shown, the fourth logic module 204 includes a second NAND gate;

[0094] The first input terminal of the second NAND gate serves as the first input terminal of the fourth logic module 204, the second input terminal of the second NAND gate serves as the second input terminal of the fourth logic module 204, and the output terminal of the second NAND gate serves as the output terminal of the fourth logic module 204.

[0095] It should be noted that if the third logic module includes the first NAND gate, the fourth logic module includes the second NAND gate;

[0096] In one embodiment, both the third logic module and the fourth logic module can be configured as AND gates.

[0097] In this embodiment of the invention, a low-latency two-thirds frequency divider loop structure composed of the aforementioned latch circuit is proposed. While ensuring the loop logic remains unchanged, a lower-latency logic gate structure is adopted; for example, compared to a NAND gate, an AND gate can reduce the delay of one inverter. This reduces the delay of a total of four inverters, significantly improving the loop speed and thus enhancing the first-stage two-thirds frequency divider's ability to process high-speed signals.

[0098] In another aspect, the present invention also provides an HS-MMD, which includes: N two-thirds frequency dividers connected in series, where N is an integer greater than 1, and the first two-thirds frequency divider among the N two-thirds frequency dividers is the two-thirds frequency divider 200 based on the latch circuit described in any of the above embodiments.

[0099] The following examples illustrate the latch circuit, two-to-three frequency divider, and HS-MMD provided in the embodiments of the present invention.

[0100] Figure 10 This is the fourth schematic diagram of the two-thirds frequency divider based on the latch circuit provided by the present invention, as shown below. Figure 10 As shown, the divide-and-conquer frequency divider includes four latch circuits. The first input terminal of each latch circuit is the D port, the second input terminal is the ck port, and the output terminal is the Qb port. The SN / RN on each latch circuit indicates whether the latch circuit is set to 1 or 0 during reset. The figure illustrates an example where the first logic module includes a NAND gate, the second logic module includes a third inverter, the third logic module includes a first NAND gate, and the fourth logic module includes a second NAND gate.

[0101] In addition, this invention also proposes an HS-MMD that can directly process high-speed signals output by VCO without the need for a pre-high-speed prescaler.

[0102] Figure 11 This is a schematic diagram of the output waveform of MMD when clk is 8GHz, as provided by the present invention. Figure 11 As shown in the figure, this figure compares the output of a conventional two-to-three divider (Normal) and the first stage (High speed) of the HS-MMD when the clock input is 8GHz. It can be seen that the input-output delay of the conventional two-to-three divider is 207.2ps, while the delay of the first stage of the HS-MMD is only 26.6ps, a delay reduction of 87.1%.

[0103] Figure 12 This is a schematic diagram of the output waveform of MMD when clk is 15GHz, as provided by the present invention. Figure 12 As shown in the figure, this is the input of a 15GHz high-speed clock signal. Because the conventional structure can only reach a maximum input of 8GHz, it can be seen that the frequency division ratio (three-way division) has been incorrect, while the HS-MMD can complete the normal frequency division function.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.< / n> < / n>

Claims

1. A latch circuit, characterized in that, include: The first three-state gate, the second three-state gate, and the first inverter; The input terminal of the first tri-state gate serves as the first input terminal of the latch circuit, the control terminal of the first tri-state gate serves as the second input terminal of the latch circuit, the control terminal of the first tri-state gate is used to receive a first clock signal, the output terminal of the first tri-state gate serves as the output terminal of the latch circuit, the output terminal of the first tri-state gate is also connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the second tri-state gate, the output terminal of the second tri-state gate is connected to the output terminal of the first tri-state gate, and the second input terminal of the second tri-state gate is used to receive a second clock signal. At least one of the first tri-state gate, the second tri-state gate, and the first inverter uses an ultra-low threshold voltage (ULVT) type MOSFET.

2. The latch circuit according to claim 1, characterized in that, The latch circuit also includes a buffer; The output of the first tri-state gate is used as the output of the latch circuit through the buffer.

3. A frequency divider based on a latch circuit, characterized in that, include: The first logic module, the second logic module, the third logic module, the fourth logic module, the first latch circuit, the second latch circuit, the third latch circuit, and the fourth latch circuit, wherein the first latch circuit, the second latch circuit, the third latch circuit, and the fourth latch circuit are the latch circuits described in claim 1 or 2 above. The first input terminal of the first logic module serves as the output terminal of the two-thirds frequency divider based on the latch circuit. The output terminal of the first logic module is connected to the first input terminal of the first latch circuit. The second input terminal of the first latch circuit is used to receive a first clock signal. The output terminal of the first latch circuit is connected to the first input terminal of the second latch circuit. The second input terminal of the second latch circuit is used to receive a third clock signal. The output terminal of the second latch circuit is connected to the input terminal of the second logic module. The output terminal of the second logic module is connected to the first input terminal of the first logic module. The output terminal of the second latch circuit is also connected to the first... The first input terminal of the three logic modules, the second input terminal of the third logic module for receiving adjustment signals, the output terminal of the third logic module connected to the first input terminal of the third latch circuit, the second input terminal of the third latch circuit for receiving the first clock signal, the output terminal of the third latch circuit connected to the first input terminal of the fourth logic module, the second input terminal of the fourth logic module for receiving control signals, the output terminal of the fourth logic module connected to the first input terminal of the fourth latch circuit, the second input terminal of the fourth latch circuit for receiving the third clock signal, and the output terminal of the fourth latch circuit connected to the second input terminal of the first logic module.

4. The two-thirds frequency divider based on a latch circuit according to claim 3, characterized in that, The first logic module is configured to output a high level through its output terminal when both the first input terminal and the second input terminal of the first logic module are at a low level.

5. The two-thirds frequency divider based on a latch circuit according to claim 4, characterized in that, The second logic module is configured to: output a high level through the output terminal of the second logic module when the input terminal of the second logic module is at a low level; and output a low level through the output terminal of the second logic module when the input terminal of the second logic module is at a high level.

6. The two-thirds frequency divider based on a latch circuit according to claim 5, characterized in that, The third logic module is used to output a low level through its output terminal when the first input terminal of the third logic module is at a high level and the second input terminal of the third logic module is at a high level.

7. The two-thirds frequency divider based on a latch circuit according to claim 6, characterized in that, The fourth logic module is used to output a low level through its output terminal when the first input terminal of the fourth logic module is at a high level and the second input terminal of the fourth logic module is at a high level.

8. The two-thirds frequency divider based on a latch circuit according to any one of claims 3 to 7, characterized in that, The first logic module includes NOR gates; The first input terminal of the NOR gate serves as the first input terminal of the first logic module, the second input terminal of the NOR gate serves as the second input terminal of the first logic module, and the output terminal of the NOR gate serves as the output terminal of the first logic module.

9. The two-thirds frequency divider based on a latch circuit according to any one of claims 3 to 7, characterized in that, The first logic module includes an AND gate and a second inverter; The first input terminal of the AND gate serves as the first input terminal of the first logic module, the second input terminal of the AND gate is connected to the output terminal of the second inverter, the input terminal of the second inverter serves as the second input terminal of the first logic module, and the output terminal of the AND gate serves as the output terminal of the first logic module.

10. The two-thirds frequency divider based on a latch circuit according to claim 9, characterized in that, The second logic module includes a third inverter; The input terminal of the third inverter serves as the input terminal of the second logic module, and the output terminal of the third inverter serves as the output terminal of the second logic module.

11. The two-thirds frequency divider based on a latch circuit according to claim 10, characterized in that, The third logic module includes a first NAND gate; The first input terminal of the first NAND gate serves as the first input terminal of the third logic module, the second input terminal of the first NAND gate serves as the second input terminal of the third logic module, and the output terminal of the first NAND gate serves as the output terminal of the third logic module.

12. The two-thirds frequency divider based on a latch circuit according to claim 11, characterized in that, The fourth logic module includes a second NAND gate; The first input terminal of the second NAND gate serves as the first input terminal of the fourth logic module, the second input terminal of the second NAND gate serves as the second input terminal of the fourth logic module, and the output terminal of the second NAND gate serves as the output terminal of the fourth logic module.

13. A high-speed multimode frequency divider HS-MMD, characterized in that, include: N frequency dividers connected in series, where N is an integer greater than 1, wherein the first frequency divider among the N frequency dividers is the frequency divider based on the latch circuit as described in any one of claims 3 to 12.

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