Vertical non-volatile memory device

Abstract

A vertical non-volatile memory device is provided. The non-volatile memory device includes a lower insulating layer on a substrate, a multi-layer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric, and a channel structure, and has an opening extending through the multi-layer structure and exposing the lower insulating layer. The opening includes a first opening portion extending through at least one layer of the multi-layer structure with a first width, and a second opening portion extending through the multi-layer structure with a second width smaller than the first width. A gate dielectric layer is located in the opening, and the channel structure is disposed on the gate dielectric layer and electrically connected to the substrate.

Description

[0001] This patent application is a divisional application of Chinese patent application No. 201711157724.7, filed on November 20, 2017.

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2016-0173917, filed on December 19, 2016, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a non-volatile memory device having a vertical structure and a method for manufacturing the non-volatile memory device. Background Technology

[0004] Despite their small size, electronic products need to process large amounts of data. Therefore, non-volatile memory devices with vertical transistor structures have been proposed to replace existing horizontal transistor structures to improve the integration density of semiconductor memory devices. These non-volatile memory devices have vertical channels formed in vias with a high aspect ratio. Therefore, a simple and reliable method for forming these vias is required in the fabrication of non-volatile memory devices with vertical transistor structures. Summary of the Invention

[0005] According to one aspect of the inventive concept, a non-volatile memory device is provided, the non-volatile memory device comprising: a substrate, a lower insulating layer disposed on the substrate, a multilayer structure including a plurality of layers of gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric, and a channel structure, wherein the multilayer structure has an opening extending vertically from the lower insulating layer, the opening including a first opening portion and a second opening portion, the first opening portion extending from the lower insulating layer through at least one of the plurality of layers of the multilayer structure, the second opening portion being located on the first opening portion and extending vertically upward from the first opening portion in the multilayer structure, the opening having a first width at the first opening portion and a second width at the second opening portion, the second width being less than the first width, the gate dielectric extending along an inner surface and a lower surface defining a side and a bottom of the opening, respectively, the channel structure being configured on the gate dielectric within the opening to extend along the inner surface and the lower surface defining the side and bottom of the opening, the channel structure extending through the lower insulating layer and electrically connected to the substrate.

[0006] According to another aspect of the inventive concept, a non-volatile memory device is provided, the non-volatile memory device comprising: a substrate; a lower insulating layer disposed on the substrate; at least one gate electrode and at least one first interlayer insulating layer alternately stacked on the lower insulating layer; a second gate electrode and a second interlayer insulating layer alternately stacked on the at least one first interlayer insulating layer; a gate dielectric layer; and a channel structure, wherein the non-volatile memory device has an opening extending therein, the opening including a first opening portion extending through the at least one gate electrode and the at least one first interlayer insulating layer, and a second opening portion extending through the second gate electrode and the second interlayer insulating layer, the width of the second opening portion being smaller than the width of the first opening portion, the gate dielectric layer extending along an inner surface and a lower surface defining a side and a bottom of the opening, respectively; the channel structure disposed on the gate dielectric layer and located on the inner surface and the lower surface defining the side and bottom of the opening, the channel structure extending through the lower insulating layer and electrically connected to the substrate.

[0007] According to another aspect of the inventive concept, a non-volatile memory device is provided, the non-volatile memory device comprising: a substrate having a main surface; a lower insulating layer disposed on the main surface of the substrate; a plurality of lower stacked layers disposed on the lower insulating layer, the plurality of lower stacked layers including a lower gate electrode and a lower interlayer insulating layer disposed on the lower gate electrode; a plurality of upper stacked layers disposed on the plurality of lower stacked layers, the plurality of upper stacked layers including an upper gate electrode and an upper interlayer insulating layer, the upper interlayer insulating layer and the upper gate electrode being alternately disposed in a vertical direction, the plurality of upper stacked layers having a uppermost surface; and a columnar structure having a first portion extending vertically through the plurality of lower stacked layers and a second portion extending vertically through the plurality of upper stacked layers from the first portion to the uppermost surface of the plurality of upper stacked layers. The first portion of the columnar structure contacts the plurality of layers of the lower stacked layers and has a cross-section in a vertical plane extending perpendicularly to the main surface of the substrate. The second portion of the columnar structure contacts multiple layers of the upper stack and has a cross-section in the vertical plane. The columnar structure includes gate dielectrics facing multiple layers of the lower stack and multiple layers of the upper stack, and a vertical channel extending through a lower insulating layer. The gate dielectric is disposed between the vertical channel and the gate electrode layers of the lower and upper stacks. Furthermore, at the interface between the multiple layers of the lower stack and the multiple layers of the upper stack, the width of the first portion of the columnar structure in the vertical plane is greater than the width of the second portion of the columnar structure in the vertical plane. Attached Figure Description

[0008] The inventive concept will be more clearly understood through the following detailed description of examples of the inventive concept in conjunction with the accompanying drawings, in which:

[0009] Figure 1It is an equivalent circuit diagram of a memory cell array of a non-volatile memory device with a vertical structure based on the inventive concept.

[0010] Figure 2A This is a perspective view of an example of a non-volatile memory device with a vertical structure based on the inventive concept.

[0011] Figure 2B It is along Figure 2A A sectional view taken by line XX;

[0012] Figure 3A and Figure 3B It is shown Figure 2B A magnified view of A;

[0013] Figure 4 It is shown Figure 2B A magnified view of B;

[0014] Figure 5 This is a cross-sectional view of an example of a non-volatile memory device with a vertical structure according to the inventive concept;

[0015] Figure 6 It is shown Figure 5 A magnified view of C;

[0016] Figure 7 This is a cross-sectional view of an example of a non-volatile memory device with a vertical structure according to the inventive concept;

[0017] Figure 8 It is shown Figure 7 A magnified view of D;

[0018] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H , Figure 9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Figure 9O , Figure 9P and Figure 9Q This is a cross-sectional view of a non-volatile memory device during the manufacturing process of the non-volatile memory device, and together with an example of a method for manufacturing a non-volatile memory device according to another inventive concept;

[0019] Figure 10AThis is a cross-sectional view of a non-volatile memory device during the manufacturing process of a non-volatile memory device, and illustrates some processes in a method of manufacturing a non-volatile memory device according to another inventive concept.

[0020] Figure 10B It is shown Figure 10A The magnified portion of E; and

[0021] Figure 11A , Figure 11B , Figure 11C and Figure 11D It is a cross-sectional view of a non-volatile memory device during the manufacturing process of the non-volatile memory device, and shows a series of steps in a method of manufacturing a non-volatile memory device according to another inventive concept. Detailed Implementation

[0022] Figure 1 This is an equivalent circuit diagram of the memory cell array MCA of a non-volatile memory device 10 with a vertical structure, based on the inventive concept. Figure 1 This is an equivalent circuit diagram of a NAND flash memory device with a vertical channel structure.

[0023] Reference Figure 1 A memory cell array (MCA) may include a memory cell string (MS). The MCA includes bit lines BL (e.g., bit lines BL1, BL2, ..., BLm), word lines WL (e.g., word lines WL1, WL2, ..., WLn-1, and WLn), at least one string select line SSL, at least one ground select line GSL, and a common-source line CSL. The memory cell string (MS) is located between the bit lines BL (e.g., bit lines BL1, BL2, ..., BLm) and the common-source line CSL.

[0024] Each memory cell string (MS) may include a string select transistor (SST), a ground select transistor (GST), and memory cell transistors MC1, MC2, ..., MCn-1 and MCn. The drain region of the string select transistor (SST) is connected to bit lines (e.g., bit lines BL1, BL2, ..., BLm), and the source region of the ground select transistor (GST) is connected to the common-source line (CSL). The common-source line (CSL) is the region connecting the source region of the ground select transistor (GST).

[0025] The serial select transistor SST can be connected to the serial select line SSL, and the ground select transistor GST can be connected to the ground select line GSL. Furthermore, the memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to the word lines WL (e.g., word lines WL1, WL2, ..., WLn-1 and WLn), respectively.

[0026] The memory cell array MCA can be arranged in three dimensions. The memory cell transistors MC1, MC2, ..., MCn-1 and MCn forming the memory cell string MS can have a structure in which the memory cell transistors MC1, MC2, ..., MCn-1 and MCn are connected in series with each other relative to the main surface of the substrate 101 (see reference). Figures 2A to 11D Therefore, the channel structures 130, 230, and 330 of the series select transistor SST, the ground select transistor GST, and the memory cell transistors MC1, MC2, ..., MCn-1 and MCn (refer to...) Figures 2A to 11D It can extend in a direction substantially perpendicular to the main surface of the substrate 101.

[0027] Figure 2A This is a perspective view of an example of a non-volatile memory device 10 with a vertical structure according to the inventive concept. Figure 2B It is along Figure 2A A sectional view taken from line XX. Figure 2A Not shown Figure 2B Some of the components shown include, for example, bit line 193 and bit line contact plug 195. Figure 3A and Figure 3B It is shown Figure 2B The enlarged portion of the diagram, A. Figure 3A and Figure 3B The same part is shown, namely part A, but for convenience, Figure 3B The third structure SS3 is not shown. Figure 4 It is shown Figure 2B The enlarged portion of the image, B.

[0028] Reference Figure 1 , Figure 2A and Figure 2B The non-volatile memory device 100 may include a memory cell string MS, a gate electrode 150, and an interlayer insulating layer 160 on a substrate 101.

[0029] The main surface of substrate 101 may extend in a first direction (x-direction) and a second direction (y-direction). Substrate 101 may include semiconductor materials such as Group IV semiconductors, III-V compound semiconductors, or II-VI oxide semiconductors. For example, Group IV semiconductors may include silicon (Si), germanium (Ge), or SiGe. Substrate 101 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. Substrate 101 may be a bulk wafer or an epitaxial layer. Cell regions may be defined on substrate 101. Memory cell strings (MS) are arranged in the cell regions or in peripheral regions outside the cell regions.

[0030] The lower insulating layer 160M can be formed in the cell region of the substrate 101. The lower insulating layer 160M can have a thickness smaller than that of the interlayer insulating layer 160, but the inventive concept is not limited thereto. In some examples of the inventive concept, the lower insulating layer 160M can be a buffer layer such as an intermediate temperature oxide (MTO) layer and can insulate the gate electrode 150 from the substrate 101.

[0031] A multilayer structure SS can be formed on a lower insulating layer 160M. In the multilayer structure SS, gate electrodes 150 and interlayer insulating layers 160 are alternately stacked in a third direction (z-direction) perpendicular to the main surface of the substrate 101. Two adjacent gate electrodes 150 in each pair are spaced apart from each other in the third direction, and each interlayer insulating layer 160 can be placed between the two adjacent gate electrodes 150. The number of gate electrodes 150 is not limited to this. Figure 2A and Figure 2B The quantities shown are as follows. In this example, the two gate electrodes 151 and 152 at the bottom of the multilayer structure SS can constitute a ground selection line GSL, which forms a reference. Figure 1 The described ground-select transistor GST. Furthermore, the gate electrodes 158 and 159 at the top of the multilayer structure SS can form a series-select line SSL, which forms a reference. Figure 1 The described string selection transistor (SST) may have gate electrodes 153 to 157 between the lower gate electrodes 151 and 152 and the upper gate electrodes 158 and 159 as references. Figure 1 The word lines WL of the memory cell transistors MC1, MC2, ..., MCn-1 and MCn are described. The number of gate electrodes 150 can be varied according to the capacity of the memory cell string MS.

[0032] The gate electrode 150 may include a metal layer such as tungsten (W). Although not shown, the gate electrode 150 may also include a diffusion barrier (not shown), which may include, for example, tungsten nitride (WN), tantalum nitride (TaN), and / or titanium nitride (TiN). The interlayer insulating layers 160 may all include silicon oxide (SiO2). x ) or silicon nitride (SiN) y ).

[0033] The memory cell string MS can extend through the multilayer structure SS in a third direction (z-direction) perpendicular to the main surface of the substrate 101. The memory cell string MS can be arranged in a zigzag pattern. For example, each column of the memory cell string MS in the second direction (y-direction) can be offset from each column of the memory cell string MS adjacent to it in the first direction (x-direction) along the second direction. Figure 2AThe diagram illustrates the offset of two columns of memory cell strings MS. However, the inventive concept is not limited to this. The memory cell strings MS can be arranged in various ways. In some examples of the inventive concept, the memory cell strings MS can be arranged in a single column in the second direction (y-direction) or offset in a zigzag pattern across at least three columns. Furthermore, the memory cell strings MS are not limited to... Figure 2A It can take the form of a z-shape and can have a matrix structure in which the memory cell strings MS are arranged side by side in the first direction (x direction) and the second direction (y direction).

[0034] Each memory cell string (MS) may include a channel structure 130, a gate dielectric layer 140, a buried insulating layer 175, and a gate electrode 150 arranged along the peripheral side surface of the gate dielectric layer 140. The portion of each memory cell string (MS) consisting of the channel structure 130, the gate dielectric layer 140, and the buried insulating layer 175 may be in the form of a columnar structure.

[0035] The channel structure 130, the gate dielectric layer 140, and the buried insulating layer 175 (i.e., columnar structure) can extend through the multilayer structure SS in a third direction (z-direction) perpendicular to the main surface of the substrate 101 and can be formed in an opening H1 exposing the lower insulating layer 160M. The opening H1 can include a first opening region H11, a second opening region H12, and a third opening region H13. The first opening region H11 extends from the exposed portion of the lower insulating layer 160M through at least one layer of the multilayer structure SS with a first width H1W. The second opening region H12 extends through the multilayer structure SS over the first opening region H11 with a second width H2W (less than the first width H1W). The third opening region H13 extends from the upper surface of the multilayer structure SS through the multilayer structure SS with a third width H3W (less than or equal to the first width H1W).

[0036] That is, the multilayer structure SS may include a first structure SS1 having a first opening region H11, a second structure SS2 having a second opening region H12, and a third structure SS3 having a third opening region H13. For example, the first structure SS1 may include four consecutive layers starting from the exposed portion of the lower insulating layer 160M, namely, gate electrodes 151 and 152 and interlayer insulating layers 161 and 162 at the lower part of the multilayer structure SS, and the first structure SS1 may include a first opening region H11 extending through these four consecutive layers. Therefore, the columnar structure may have a first portion extending vertically through the lower stack members (e.g., gate electrodes 151 and 152 and interlayer insulating layers 161 and 162 at the lower part of the multilayer structure SS) and a second portion extending vertically from the first portion to the upper surface of the upper stack members (e.g., gate electrodes 153 to 159 and interlayer insulating layers 163 to 169 at the upper part of the multilayer structure SS) through the upper stack members (e.g., gate electrodes 153 to 159 and interlayer insulating layers 163 to 169 at the upper part of the multilayer structure SS). However, the structure of the first structure SS1 is not limited to this; the first structure SS1 may include one, two, three or more layers.

[0037] Furthermore, the third structure SS3 may include two layers from the upper surface of the multilayer structure SS, namely, the interlayer insulating layer 169 and the gate electrode 159, and may also include a third opening region H13 extending through these two layers. The second structure SS2 may include gate electrodes 153 to 158 and interlayer insulating layers 163 to 168 between the first structure SS1 and the third structure SS3, and may also include a second opening region H12 extending through the gate electrodes 153 to 158 and the interlayer insulating layers 163 to 168.

[0038] The gate electrodes 150 of the first structure SS1 to the third structure SS3 can have the same thickness T1 and can include the same material. Furthermore, the interlayer insulating layers 160 of the first structure SS1 to the third structure SS3 can have the same thickness T2 and can include the same material.

[0039] The first opening region H11 can be formed by a separate etching process performed before the etching processes that form the second opening region H12 and the third opening region H13. That is, the first opening region H11 can be formed by etching the first structure SS1 before forming the second structure SS2 and the third structure SS3. Subsequently, the first opening region H11 can be filled with the material that forms the multilayer structure SS and a material with etching selectivity, and can be used as a defining etching stop structure 122 (see reference) during the etching processes that form the second opening region H12 and the third opening region H13. Figure 9D and Figure 9E The space of the first opening region H11. The etch stop structure 122 (refer to) in the first opening region H11. Figure 9D and Figure 9EThis prevents the substrate 101 from being over-etched, thus preventing the dispersion of the opening H1 and the bypassing of the current path. The bypassing of the current path can occur due to over-etching of the substrate 101.

[0040] The first structure SS1 may have a height SS1H, which is sufficient to allow the etch stop structure 122 (refer to) to fill the first opening region H11. Figure 9D and Figure 9E To prevent over-etching, the height SS1H of the first structure SS1 is determined by the number of gate electrodes 150 and interlayer insulating layers 160 included in the first structure SS1. Therefore, the first structure SS1 can be larger than any arbitrarily formed etch stop structure 122 (see reference). Figure 9D and Figure 9E It has small manufacturing tolerances and can correspond to the structure of the initial design.

[0041] Furthermore, the etching process forming the first opening region H11 can target the first structure SS1 with a relatively low first height SS1H and can be performed as a separate etching process. Therefore, compared to an opening formed by etching the multilayer structure SS, the first width H1W of the first opening region H11 can be defined to correspond to the initial design. Therefore, the first width H1W of the first opening region H11 can be relatively uniform, and the inner surface of the first opening region H11 can be substantially or almost perpendicular to the main surface of the substrate 101. Therefore, specifically referring to… Figure 4 The gate electrode 153 of the second structure SS2, which is in contact with the first structure SS1, may have a lower surface 153B1 exposed by the first opening region H11.

[0042] Backward reference Figure 3A The first height SS1H of the first opening region H11 relative to the first width H1W can be less than or equal to 1. Conversely, the second height SS2H of the second opening region H12, which extends through the largest portion of the multilayer structure SS, relative to the second width H2W, can be equal to or greater than 1.

[0043] The second structure SS2 can be located on the first structure SS1, on which the first opening region H11 has been formed. Therefore, the gate electrode 153 in contact with the first structure SS1 can have the following structure: the horizontal level 153B1L of the lower surface 153B1 exposed by the first opening region H11 is substantially the same as the horizontal level 153B2L of the interface 153B2 between the first structure SS1 and the second structure SS2.

[0044] As described above, the etch stop structure 122 formed in the first opening region H11 (refer to) Figure 9D and Figure 9EThis can be used as an etch stop layer during the etching process that forms the second opening region H12 and the third opening region H13, and can subsequently be removed. The etch stop structure 122 (see reference) has been removed. Figure 9D and Figure 9E The first opening region H11 can be adjacent to the second opening region H12 and the third opening region H13 and be used as part of the opening H1.

[0045] In this configuration, as the opening H1 extends through the multilayer structure SS, the width of the opening H1 at the upper part of the multilayer structure SS can be relatively narrow. That is, the opening H1 can include a third opening region H13 and a second opening region H12 on the first opening region H11. The third opening region H13 has a third width H3W (increased) larger than the first width H1W of the first opening region H1, and the second opening region H12 has a second width H2W smaller than the first width H1W. The first opening region H11 forms a space with sufficient first width H1W at the lower part of the second opening region H12, thus ensuring sufficient etching process allowance for forming the contact hole CH1 in the opening H1 for electrical connection with the substrate 101.

[0046] Reference Figures 9A to 9Q To describe more specifically the etch stop structure 122 in the first opening region H11 and the process for forming the first opening region H11.

[0047] The gate dielectric layer 140 may cover the inner and lower surfaces of the respective sides and bottom of the opening H1. The gate dielectric layer 140 may be located between the channel structure 130 and the gate electrode 150. (Refer to...) Figure 3A and Figure 3B Since the first width H1W of the first opening region H11 is greater than the second width H2W of the second opening region H12, the distance 140W1 (or the spacing between opposite walls) between the inner surfaces of the gate dielectric layer 140 in the first opening region H11 can be greater than the distance 140W2 (or the spacing between opposite walls) between the inner surfaces of the gate dielectric layer 140 in the second opening region H12.

[0048] Furthermore, the first portion of the columnar structure occupying the first opening region H11 contacts the lower layer (e.g., gate electrodes 151 and 152 and insulating layers 161 and 162) and has a rectangular cross-section in a vertical plane extending perpendicularly to the main surface of the substrate. The second portion of the columnar structure occupying the second opening region H11 contacts the upper layer (e.g., gate electrodes 153 to 159 and insulating layers 163 to 169) and has a cross-section in the vertical plane that gradually decreases in a downward direction from the uppermost surface of the multilayer structure SS to the first portion of the columnar structure occupying the first opening region H11.

[0049] In some examples of the inventive concept, the gate dielectric layer 140 may include one of an oxide-nitride-oxide (ONO) layer, an oxide-nitride-aluminum oxide (ONA) layer, and an oxide-nitride-oxide-aluminum oxide (ONOA) layer.

[0050] In addition, refer to Figure 4 The gate dielectric layer 140 may have a structure in which a tunneling insulating layer 142, a charge storage layer 144, and a barrier insulating layer 146 are sequentially stacked from the left side wall of the channel structure 130. Therefore, the gate dielectric layer 140 may be referred to as a gate dielectric to describe an example of dielectric materials with different layers disposed in the opening H1.

[0051] The tunneling insulating layer 142 allows charges to tunnel through the charge storage layer 144 via Fowler-Nordheim (FN) tunneling. The tunneling insulating layer 142 may include SiO₂. x Si x N y Silicon oxynitride (SiON) and hafnium oxide (HfO) x Hafnium silicon oxide (HfSi) x O y ), aluminum oxide (Al) x O y ) and zirconium oxide (ZrO) x One or more of the single or multiple layers in )

[0052] The charge storage layer 144 can be a charge trapping layer or a floating gate conductive layer. When the charge storage layer 144 is a floating gate conductive layer, it can be formed by depositing polycrystalline silicon using silane (SiH4) or silane (Si2H6) and phosphine (PH3) via chemical vapor deposition (CVD), such as low-pressure chemical vapor deposition (LPCVD). When the charge storage layer 144 is a charge trapping layer, it can include SiO2. x Si x N y SiON, HfO x ZrO x tantalum oxide (Ta x O y Titanium oxide (TiO) x ), Hafnium aluminum oxide (HfAl) x O y ), Hafnium tantalum oxide (HfTa) x O y ), HfSi x O y Aluminum nitride (Al) x N y ) and aluminum gallium nitride (AlGa x N yAt least one of the following.

[0053] In some examples of the inventive concept, the charge storage layer 144 may include quantum dots or nanocrystals. Quantum dots or nanocrystals may include fine particles of conductors, such as metals or semiconductors.

[0054] The barrier insulating layer 146 may include SiO x Si x N y It is at least one of SiON and high-k dielectric materials. The high-k dielectric material can be a dielectric material with a dielectric constant greater than that of the oxide layer.

[0055] In some examples of the inventive concept, the barrier insulating layer 146 may comprise a material having a dielectric constant greater than that of the tunneling insulating layer 142. For example, the barrier insulating layer 146 may comprise Al. x O y Ta x O y TiO x Yttrium oxide (Y) x O y ZrO x Zirconium oxide silicon (ZrSi) x O y ), HfO x HfSi x O y Lanthanum oxide (La) x O y ), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ),HfAl x O y and praseodymium oxide (Pr x O y At least one of the following.

[0056] The channel structure 130 may extend on the surfaces defining the sides and bottom of the opening H1 and on the gate dielectric layer 140. The channel structure 130 may be annular in the opening H1. However, the inventive concept is not limited thereto. The channel structure 130 may have a cylindrical shape or a prism shape. (See also...) Figure 3A and Figure 3B Because the first width H1W of the first opening region H11 is greater than the second width H2W of the second opening region H12, the distance 130W1 (or the spacing between opposite sidewalls) between the inner surfaces of the channel structures 130 in the first opening region H11 can be greater than the distance 130W2 (or the spacing between opposite sidewalls) between the inner surfaces of the channel structures 130 in the second opening region H12.

[0057] The channel structure 130 can extend through the lower insulating layer 160M and thus can be electrically connected to the substrate 101. For example, as shown in the figures, the channel structure 130 includes a contact portion 132 protruding from the lower surface of the channel structure 130 and can be connected to the substrate 101 through the contact portion 132.

[0058] In some examples of the inventive concept, the channel structure 130 may include a first channel layer 130a and a second channel layer 130b. The first channel layer 130a may cover the gate dielectric layer 140, and the second channel layer 130b may cover the first channel layer 130a.

[0059] In some examples of the inventive concept, the second channel layer 130b may include a contact portion 132 extending through the first channel layer 130a, the gate dielectric layer 140 and the lower insulating layer 160M and thus connected to the substrate 101.

[0060] For example, both the first channel layer 130a and the second channel layer 130b may comprise semiconductor materials such as polycrystalline silicon or monocrystalline silicon. The first channel layer 130a and the second channel layer 130b may comprise the same material. However, the inventive concept is not limited thereto.

[0061] In some embodiments of the inventive concept, both the first channel layer 130a and the second channel layer 130b may comprise polysilicon doped with n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb) or p-type impurities such as Al, boron (B), indium (In), or potassium (K). In other embodiments of the inventive concept, both the first channel layer 130a and the second channel layer 130b may comprise undoped polysilicon.

[0062] The buried insulating layer 175 may extend within the trench structure 130 above the sides and bottom of the opening H1. In this case, the buried insulating layer 175 may include a first void V1 isolated within the first opening region H11. The first void V1 in the first opening region H11 may have a shape with an aspect ratio relatively close to 1, depending on the shape of the first opening region H11. Although a second void V2 may be formed in the second opening region H12 and the third opening region H13, because the second void V2 extends in a direction perpendicular to the substrate 101, the second void V2 may have a shape with an aspect ratio much larger than 1.

[0063] A conductive layer 190 may be disposed on the upper surface of the channel structure 130, the gate dielectric layer 140, and the buried insulating layer 175. The conductive layer 190 may be electrically connected to the channel structure 130. The conductive layer 190 may include, for example, doped polysilicon. The conductive layer 190 may be used as a reference. Figure 1 The description refers to the drain region of the string selection transistor SST.

[0064] Impurity region 105 may be located within substrate 101. Impurity region 105 may be located on the main surface of substrate 101 and extend in a second direction (y direction). Figure 2A and Figure 2B Only one impurity region 105 is shown, but multiple impurity regions may exist between adjacent channel structures 130 in the first direction (x direction). In some examples of the inventive concept, the impurity region 105 may be a source region and may form a PN junction with other regions of the substrate 101.

[0065] The common source electrode structure 170 can extend into the impurity region 105. In some examples of the inventive concept, the common source electrode structure 170 may include a common source electrode 172 and a common source electrode spacer 174.

[0066] As shown, the memory cell string MS is arranged symmetrically about the common-source pole structure 170. However, the inventive concept is not limited thereto. In some examples of the inventive concept, adjacent memory cell strings MS can be arranged asymmetrically about the common-source pole structure 170.

[0067] The common source electrode 172 can be disposed in the impurity region 105 of the substrate 101. For example, in some portions of the impurity region 105, the common source electrode 172 can extend in the second direction (y direction). In some cases, the common source electrode 172 can be formed over the entire upper portion of the impurity region 105 along the second direction (y direction).

[0068] In some examples of the inventive concept, the common source electrode 172 may comprise a metal such as tungsten (W), Al, copper (Cu), Ti, or Ta. In other examples of the inventive concept, the common source electrode 172 may comprise a conductive material such as impurity-doped polycrystalline silicon or a metal silicide such as nickel silicide, titanium silicide, tungsten silicide, or cobalt silicide.

[0069] Common source electrode spacer 174, including insulating material, can be disposed on both sidewalls of common source electrode 172. Common source electrode spacer 174 can be disposed on the sidewall of gate electrode 150 and serve as an isolation layer that electrically insulates gate electrode 150 and common source electrode 172 from each other.

[0070] The common source electrode structure 170 can extend through the lower insulating layer 160M and contact the substrate 101. Therefore, the lower surface of the common source electrode structure 170 can be at a lower level than the main surface of the substrate 101.

[0071] The upper insulating layer 181 can be disposed on the multilayer structure SS and the conductive layer 190. The upper surface of the upper insulating layer 181 and the upper surface of the common source line 172 can be located at substantially the same level.

[0072] A common source electrode buried insulation layer 183 covering at least some portions of the upper surface of the common source electrode 172 may be disposed on the upper insulation layer 181. The common source electrode buried insulation layer 183 may be placed between the common source electrode 172 extending in the second direction (y direction) and the bit line 193 extending above the common source electrode 172 in the first direction (x direction), and may serve as an isolation layer that electrically insulates the common source electrode 172 and the bit line 193 from each other.

[0073] Bit lines 193, which extend in the first direction (x direction) and have a linear pattern, can be disposed on the common source electrode buried insulation layer 183. Bit lines 193 can be electrically connected to the conductive layer 190 through bit line contact plugs 195 extending through the upper insulation layer 181 and the common source electrode buried insulation layer 183.

[0074] Figure 5 This is a cross-sectional view of an example of a non-volatile memory device 200 having a vertical structure according to the inventive concept. Figure 6 It is shown Figure 5 The enlarged portion of Figure C is shown in the figure. The same reference numerals in the figures indicate the same elements, and repeated descriptions thereof will be omitted.

[0075] Reference Figure 5 and Figure 6 The opening H2 can be formed to expose the lower insulating layer 160M by extending through the multilayer structure SS in a third direction (z-direction) perpendicular to the main surface of the substrate 101. The channel structure 230, the gate dielectric layer 240, and the buried insulating layer 275 can be formed in the opening H2. A first opening region H21 can be formed, extending from the exposed portion of the lower insulating layer 160M through at least one layer of the multilayer structure SS with a first width. Above the first opening region H21, a second opening region H22 and a third opening region H23 can be further formed, the second opening region H22 extending through the multilayer structure SS with a second width smaller than the first width, and the third opening region H23 extending from the upper surface of the multilayer structure SS through the multilayer structure SS with a third width equal to or greater than the first width.

[0076] The gate electrodes 250 can be sequentially stacked along the side of the opening H2 in a third direction (z-direction) perpendicular to the substrate 101. In this case, the bottom surface of the gate electrode 253 located next to the first opening region H21 can have a rounded peripheral surface R. As a result, the columnar structure occupying the opening H2 has a chamfer along the outer peripheral portion of the columnar structure, where the first portion of the columnar structure occupying the first opening region H21 intersects with the second portion of the columnar structure occupying the second opening region H22 at that outer peripheral portion.

[0077] More specifically, the area where the lower surface 253B exposed by the first opening region H21 contacts the side surface 253S exposed by the second opening region H22 can have a rounded peripheral surface R. This structure can be formed by a process for forming the first opening region H21 performed prior to a separate etching process.

[0078] That is, when performing the etching process on the second opening region H22 and the third opening region H23, the lower surface 253B of the gate electrode 253, which is exposed by the pre-formed first opening region H21, can be exposed by the etchant. More specifically, the portion of the lower surface 253B of the gate electrode 253 adjacent to its side surface 253S can begin to be exposed by the etchant. Therefore, the edge of the lower surface 253B of the gate electrode 253 that contacts the side surface 253S of the gate electrode 253 can be rounded. (Refer to...) Figures 10A to 10B The process for forming the peripheral surface R is described in more detail.

[0079] Figure 7 This is a cross-sectional view of an example of a non-volatile memory device 300 with a vertical structure according to the inventive concept. Figure 8 It is shown Figure 7 The enlarged portion of the image, D.

[0080] Reference Figure 7 and Figure 8 The channel structure 330 may be disposed on the gate dielectric layer (also referred to as the gate insulating layer) 340 within the opening H3. The opening H3 includes a first opening portion H31, a second opening portion H32, and a third opening portion H33 (also referred to as the first opening region H31, the second opening region H32, and the third opening region H33). The channel structure 330 may extend through the lower insulating layer 160M at the bottom of the opening H3 and thus may be electrically connected to the substrate 101. For example, as shown, the channel structure 330 may include a contact portion 332 protruding from the lower surface of the channel structure 330 and may be electrically connected to the substrate 101 through the contact portion 332.

[0081] In this configuration, the channel structure 330 in the first opening portion H31 can have a bulb shape with its width increasing towards the portion of the channel structure 330 adjacent to the lower insulating layer 160M. More specifically, the inner surface of the channel structure 330 in the first opening portion H31 may include a first inner surface region CHI1 adjacent to the lower insulating layer 160M and a second inner surface region CHI2 located on the first inner surface region CHI1. In this configuration, the width CHI1W of the channel structure 330 in the first inner surface region CHI1 can be greater than the width CHI2W of the channel structure 330 in the second inner surface region CHI2. That is, the second inner surface region CHI2 can be recessed in the lateral direction.

[0082] Therefore, both the trench structure 330 (specifically, layer 330b of the trench structure 330) and the buried insulation layer 375 have a lowermost portion that extends radially outward.

[0083] The above structure can be formed by removing the gate dielectric layer 340 adjacent to the contact hole CH3, so as to ensure the etching allowance of the contact hole CH3 before forming the contact hole CH3 exposed substrate 101.

[0084] Figures 9A to 9Q This is a cross-sectional view of a series of steps in a method for manufacturing a non-volatile memory device 100 according to the inventive concept.

[0085] Reference Figure 9A A lower insulating layer 160M is formed on a substrate 101, and at least one first sacrificial layer 111 and 112 and at least one interlayer insulating layer 161 and 162 for forming the first structure may be alternately stacked on the substrate 101 starting from the lower insulating layer 160M.

[0086] The first sacrificial layers 111 and 112 may include materials that are etch-selective to the interlayer insulating layers 161 and 162. For example, the first sacrificial layers 111 and 112 may be etched with certain etchants at an etch rate greater than the etch rate at which the interlayer insulating layers 161 and 162 are etched. That is, the materials included in the first sacrificial layers 111 and 112 may be etched with minimal etching of the interlayer insulating layers 161 and 162. For example, the interlayer insulating layers 161 and 162 may be at least one of silicon oxide and silicon nitride layers, and the first sacrificial layers 111 and 112 may be selected from silicon layers, silicon oxide layers, silicon carbide layers, and silicon nitride layers, and may include different materials that are etch-selective to the interlayer insulating layers 161 and 162.

[0087] Reference Figure 9B A first etching process can be performed to form a first opening region H11 extending through the first sacrificial layers 111 and 112 and the interlayer insulating layers 161 and 162. The first sacrificial layers 111 and 112 and the interlayer insulating layers 161 and 162 are alternately stacked on the upper surface 160MT of the lower insulating layer 160M and expose the upper surface 160MT of the lower insulating layer 160M. In this case, the first opening region H11 may have a uniform first width H1W, but the inventive concept is not limited thereto. The side profile of the first opening region H11 has a certain slope, so the first width H1W may vary slightly depending on the height.

[0088] The first etching process can be an anisotropic etching process. For example, the first etching process can be any of physical etching such as sputtering etching, chemical etching such as reactive radical etching, and physicochemical etching such as reactive ion etching (RIE), magnetically enhanced RIE (MERIE), transformer-coupled plasma (TCP) etching, or inductively coupled plasma (ICP) etching.

[0089] More specifically, a first etching process can be performed by forming a mask pattern (not shown) to define the location of the first opening region H11 on the alternately stacked first sacrificial layers 111 and 112 and interlayer insulating layers 161 and 162, and by using the same mask pattern as an etching mask while using an etchant to etch the first sacrificial layers 111 and 112 and interlayer insulating layers 161 and 162.

[0090] Reference Figure 9C A second sacrificial layer 121 filling the first opening region H11 can be formed on the first sacrificial layers 111 and 112 and the interlayer insulating layers 161 and 162. The second sacrificial layer 121 can be etch-selective with respect to the interlayer insulating layers 161 and 162 and can include a material etch-selective with respect to the first sacrificial layers 111 and 112. For example, when using a first etchant, the etching rate of the second sacrificial layer 121 can be less than the etching rate of the first sacrificial layers 111 and 112 with respect to the interlayer insulating layers 161 and 162, and when using a second etchant, the etching rate of the material included in the second sacrificial layer 121 can be greater than the etching rate of the first sacrificial layers 111 and 112 with respect to the interlayer insulating layers 161 and 162. More specifically, when the first sacrificial layers 111 and 112 or the interlayer insulating layers 161 and 162 are etched with the first etchant, the second sacrificial layer 121 is etched to a minimum, and when the second sacrificial layer 121 is etched with the second etchant, the first sacrificial layers 111 and 112 and the interlayer insulating layers 161 and 162 can be etched to a minimum. In some examples of the inventive concept, the second sacrificial layer 121 may comprise polysilicon.

[0091] Reference Figure 9D Planarization processes that can be performed, such as chemical mechanical polishing (CMP) or etching-back processes, enable... Figure 9C The second sacrificial layer 121 remains only in the first opening region H11. The upper surface of the interlayer insulating layer 162 can be exposed by a planarization process.

[0092] Figure 9C The second sacrificial layer 121 that fills the first opening region H11 can be used as an etch stop structure 122.

[0093] Reference Figure 9EThe first sacrificial layers 113 to 119 and the interlayer insulating layers 163 to 169 can be alternately stacked on the etch stop structure 122 and the interlayer insulating layers 161 and 162, depending on the number of gate electrodes required in the final device.

[0094] Subsequently, a second etching process can be performed to form the rear opening region H1K. The rear opening region H1K extends through the alternately stacked first sacrificial layers 113 to 119 and interlayer insulating layers 163 to 169 and exposes the upper surface 122R of the etch stop structure 122. The etch stop structure 122 can prevent the substrate 101 from being exposed and the contact holes from dispersing during the second etching process. The uppermost width H3W of the rear opening region H1K can be equal to or greater than the first width H1W of the first opening region H11. The second width H2W of the rear opening region H1K can be smaller than the first width H1W of the first opening region H11 at the boundary between the rear opening region H1K and the first opening region H11.

[0095] Specifically, a second etching process can be performed by forming a mask pattern (not shown) defining the location of the back opening region H1K on the alternately stacked first sacrificial layers 113 to 119 and interlayer insulating layers 163 to 169, and by using the same mask pattern as an etching mask while using an etchant to etch the first sacrificial layers 113 to 119 and interlayer insulating layers 163 to 169.

[0096] Rear opening region H1K and reference Figures 2A to 4 The second opening region H12 and the third opening region H13 are the same as described, and for convenience, they are referred to as the rear opening region H1K in the description of the method of manufacturing a non-volatile memory device.

[0097] Reference Figure 9F The etch stop structure 122 exposed by the rear opening region H1K can be removed. Therefore, an opening H1 including the first opening region H11 and the rear opening region H1K can be formed. The upper surface of the lower insulating layer 160M can be exposed through the opening H1.

[0098] Reference Figure 9G A gate dielectric layer 140 can be uniformly formed along the surface defining the side and bottom of the opening H1. (See reference...) Figure 3A and Figure 3B The gate dielectric layer 140 may include a barrier insulating layer ( Figure 4 142), charge storage layer ( Figure 4 144) and tunnel insulation layer ( Figure 4(146 in the text). In some examples of the inventive concept, each of the barrier insulating layer, charge storage layer, and tunneling insulating layer can be formed by, for example, CVD, physical vapor deposition (PVD), metal-organic CVD (MOCVD), atomic layer deposition (ALD), or metal-organic ALD (MOALD). However, the inventive concept is not limited thereto.

[0099] Reference Figure 9H A first channel layer 130a can be formed on the gate dielectric layer 140. The first channel layer 130a may comprise a semiconductor material such as polycrystalline silicon or monocrystalline silicon. The semiconductor material may be undoped or may comprise p-type or n-type impurities. In some examples of the inventive concept, the first channel layer 130a may be formed by ALD or CVD, etc.

[0100] Reference Figure 9I A spacer layer 135 can be formed on the first channel layer 130a. In some examples of the inventive concept, the spacer layer 135 can be, for example, a silicon oxide layer or a silicon nitride layer, or the spacer layer 135 can be formed by ALD or CVD. The spacer layer 135 can be used as a mask for etching the lower surface of the first channel layer 130a and the gate dielectric layer 140, and can prevent the first channel layer 130a from being damaged during the etching process.

[0101] In the accompanying drawings, spacer layer 135 is shown covering the entire first channel layer 130a. However, the inventive concept is not limited thereto. For example, with Figure 9I Unlike the illustration, spacer layer 135 may only cover the side surface of the first channel layer 130a.

[0102] Reference Figure 9J The lower surface of the lower insulating layer 160M, the first channel layer 130a, and the gate dielectric layer 140 can be anisotropically etched using spacer layer 135 as a mask. Contact holes CH1 exposing the substrate 101 can be formed using anisotropic etching. During the anisotropic etching process, the substrate 101 can be over-etched, thus recessed to a certain depth. When the substrate 101 is recessed, the second channel layer (…) fills the recess of the substrate 101… Figure 9L The contact area of ​​130b) that contacts the substrate 101 increases during subsequent processes, thus the channel resistance can decrease.

[0103] Reference Figure 9K The spacer layer 135 retained on the sidewall of the first channel layer 130a can be removed. This can be done, for example, by a wet cleaning process. Figure 9J The spacer layer 135. A wet cleaning process can be performed using solutions of, for example, fluorine and a mixture of ammonia and hydrogen peroxide. The spacer layer 135 can be removed by a separate process or cleaning process performed before the formation of the second channel layer 130b.

[0104] Reference Figure 9L A second channel layer 130b can be formed on the first channel layer 130a exposed by removing the spacer layer 135. The first channel layer 130a and the second channel layer 130b can together form the channel structure 130. The contact hole CH1 can be filled with the second channel layer 130b, therefore, the channel structure 130 can include a contact portion 132. The channel structure 130 can be electrically connected to the substrate 101 through the contact portion 132. The second channel layer 130b can include the same material as the first channel layer 130a, and can include a semiconductor material such as polycrystalline silicon or monocrystalline silicon.

[0105] Reference Figure 9M The opening H1, which remains after the formation of the channel structure 130, can be filled with a buried insulating layer 175. Optionally, prior to the formation of the buried insulating layer 175, a hydrogen annealing process can be performed to heat-treat the structure in a gaseous atmosphere including hydrogen or deuterium to form the channel structure 130. Most crystal defects occurring in the channel structure 130 can be eliminated in the hydrogen annealing process. In this case, the first void V1 and the second void V2 can be formed in the first opening region H11 and the rear opening region H1K of the buried insulating layer 175, respectively. However, the inventive concept is not limited to this. Therefore, depending on manufacturing tolerances, the second void V2 may not be formed.

[0106] Subsequently, in order to remove the semiconductor material, insulating material, etc. that unnecessarily cover the uppermost interlayer insulating layer 169 among the interlayer insulating layers 161 to 169, a planarization process such as CMP or etch-back process can be performed until the upper surface of the interlayer insulating layer 169 is exposed.

[0107] Furthermore, a conductive layer 190 can be formed to cover the upper surface of each of the channel structure 130, the gate dielectric layer 140, and the buried insulating layer 175. In some embodiments of the inventive concept, the conductive layer 190 can be buried in the third opening region H13 after the third opening region H13 is formed. In some embodiments of the inventive concept, the conductive layer 190 may comprise polysilicon doped with n-type impurities such as P, As, or Sb. Therefore, a memory cell string MS can be formed.

[0108] Reference Figure 9N An upper insulating layer 181 can be formed to cover the upper surface of the conductive layer 190 and the upper surface of the interlayer insulating layer 169. The upper insulating layer 181 can protect the conductive layer 190 from damage or contamination that may occur in subsequent processes.

[0109] An opening HC for exposing the substrate 101 can be formed between memory cell strings MS by anisotropic etching of the upper insulating layer 181, the interlayer insulating layer 160 and the first sacrificial layer 110.

[0110] Reference Figure 9O Remove HC exposed through the opening Figure 9N The first sacrificial layer 110 shown can also form a side opening HCS defined between the interlayer insulating layers 160. The first sacrificial layer 110 can be removed, for example, by a full etch-back process. Some sides of the gate dielectric layer 140 can be exposed through the side opening HCS.

[0111] The side opening HCS can be formed by horizontally etching the first sacrificial layer 110 using an etchant that hardly etches the interlayer insulating layer 160. The etching process can be, for example, a wet etching process, a chemical dry etching process, or a dry evaporation etching process. The etching process can be an isotropic etching process.

[0112] Reference Figure 9P It can be filled with a conductive material (not shown). Figure 9O The side opening HCS. The conductive material can be, for example, a metal called W. After filling the side opening HCS with the conductive material, the conductive material in the opening HC can be removed so that only W remains. Figure 9O Conductive material in the side-opening HCS.

[0113] Reference Figure 9Q ,pass Figure 9P The opening HC in the middle injects impurities into the substrate 101, thereby forming the impurity region 105.

[0114] Subsequently, after forming an insulating layer along the opening HC and the upper surface of the upper insulating layer 181, a common source electrode spacer 174 can be formed by performing an anisotropic etching process. The impurity region 105 formed on the substrate 101 can be exposed by performing an etching process.

[0115] A conductive layer (not shown) including W, Ta, Co, tungsten silicide, tantalum silicide or cobalt silicide is formed in the opening HC where the common source electrode spacer 174 is formed. Then a planarization process is performed on the conductive layer until the upper surface of the upper insulating layer 181 is exposed, thereby forming the common source electrode 172.

[0116] Backward reference Figure 2BA common-source electrode buried insulating layer 183 is formed, covering the common-source electrode structure 170 and the upper insulating layer 181. Furthermore, a bit line contact plug 195 can be formed. The bit line contact plug 195 can extend through the common-source electrode buried insulating layer 183 and the upper insulating layer 181 by performing photolithography and etching processes, and thus contact the conductive layer 190. A bit line 193 connecting to the bit line contact plug 195 can be formed on the common-source electrode buried insulating layer 183. Therefore, a reference can be manufactured. Figures 2A to 4 The non-volatile memory device 100 is described.

[0117] Figure 10A This is a cross-sectional view illustrating some processes in a method of manufacturing a non-volatile memory device 200 according to another example of the inventive concept. Figure 10B It is shown Figure 10A The diagram shows the magnified portion of E. The method for manufacturing the non-volatile memory device 200 is similar to that described in the reference diagram. Figures 9A to 9Q The method described. However, as referenced... Figure 9F As described, during the etching process that etches the etch stop structure in the first opening region H21, the etchant penetrates from the portion of the lower surface 213B adjacent to the side surface 213S of the sacrificial layer 213, exposing the lower surface 213B of the sacrificial layer 213 to the first opening region H21. Therefore, the angle where the lower surface 213B and the side surface 213S of the sacrificial layer 213 intersect can be etched into a rounded shape.

[0118] It can be done by executing the same method. Figures 9G to 9Q The subsequent processes are used to manufacture reference. Figure 5 and Figure 6 The non-volatile memory device 200 is described.

[0119] Figures 11A to 11D This is a cross-sectional view illustrating some processes for describing a method of manufacturing a non-volatile memory device 300, according to another example of the inventive concept. The method of manufacturing the non-volatile memory device 300 is similar to that described in reference to [reference missing]. Figures 9A to 9Q The method described. (Refer to...) Figure 9K and Figure 11A After forming the contact hole CH3 exposing the substrate 101, an etching process can be performed to further etch the lower sidewalls of the gate insulating layer 340, the first channel layer 330a, and the spacer layer 335. This additional etching process can be an isotropic etching process. Therefore, the inner surface of the gate insulating layer 340 can be recessed in the lateral direction.

[0120] Reference Figure 11B It can remove the material remaining on the sidewall of the first channel layer 330a. Figure 11A The spacer layer 335 can be removed by, for example, a wet cleaning process.

[0121] Reference Figure 11C A second channel layer 330b can be formed on the first channel layer 330a exposed by removing the spacer layer 335. In this case, the inner surface of the second channel layer 330b can have a bulb shape that is wider at the bottom than at the top.

[0122] Reference Figure 11D The opening H3 remaining after the formation of the trench structure 330 can be filled with a buried insulating layer 375. In this case, a first void V4 and a second void V2 can be formed in the first opening region H11 and the rear opening region H1K in the buried insulating layer 375, respectively. However, the inventive concept is not limited to this. Depending on manufacturing tolerances, the second void V2 may not be formed.

[0123] It can be done by executing the same method. Figures 9N to 9Q The subsequent processes in the process are used to manufacture reference. Figure 7 and Figure 8 The non-volatile memory device 300 is described.

[0124] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made to these examples without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A nonvolatile memory device, comprising: a semiconductor layer; a lower insulating layer disposed on the semiconductor layer; a multilayer structure of a plurality of layers including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multilayer structure having an opening including a first portion and a second portion; a gate dielectric extending along sides and a bottom of the opening; and a channel structure disposed on the gate dielectric within the opening and extending along the sides and the bottom of the opening, the channel structure extending through the lower insulating layer and electrically connected to the semiconductor layer, wherein the first portion extends vertically from a bottom surface of the lower insulating layer to at least one layer of the multilayer structure, the second portion is located on the first portion and extends vertically through the multilayer structure, the first portion of the opening has a first width, and the second portion of the opening has a second width smaller than the first width, the multilayer structure includes a first structure including the first portion of the opening and a second structure including the second portion of the opening, a height of the first portion of the opening is less than or equal to 1 with respect to the first width, and a height of the second portion of the opening is equal to or greater than 1 with respect to the second width, and the lower insulating layer includes only one insulating layer disposed between a lowermost gate electrode in the first structure and the semiconductor layer by a deposition process. a distance between outer surfaces of the gate dielectric in the first portion of the opening is greater than a distance between outer surfaces of the gate dielectric in the second portion of the opening.

2. The nonvolatile memory device of claim 1, wherein, no insulating layer other than the lower insulating layer is disposed between the semiconductor layer and the lowermost gate electrode.

3. The nonvolatile memory device of claim 1, wherein, the channel structure includes a contact portion extending through the lower insulating layer and in contact with the semiconductor layer.

4. The nonvolatile memory device of claim 1, wherein, a thickness of the lower insulating layer is smaller than a thickness of each of the interlayer insulating layers.

5. The nonvolatile memory device of claim 1, wherein, a buried insulating layer disposed on the channel structure within the opening, wherein the buried insulating layer has a void in the buried insulating layer, the void being located within the first portion of the opening.

6. The nonvolatile memory device of claim 1, further comprising: the opening has a third portion extending from an upper surface of the multilayer structure, and 7. The nonvolatile memory device of claim 1, wherein, the third portion of the opening has a third width equal to or greater than the first width. a distance between inner surfaces of the gate dielectric in the first portion of the opening is greater than a distance between inner surfaces of the gate dielectric in the second portion of the opening.

8. The nonvolatile memory device of claim 1, wherein, a distance between inner surfaces of the channel structure in the first portion of the opening is greater than a distance between inner surfaces of the channel structure in the second portion of the opening.

9. The nonvolatile memory device of claim 1, wherein, the channel structure in the first portion of the opening has a first region adjacent to the lower insulating layer and a second region on the first region, and 10. The nonvolatile memory device of claim 1, wherein, a distance between inner surfaces of the channel structure in the first region is greater than a distance between inner surfaces of the channel structure in the second region. 11.A nonvolatile memory device, comprising: a semiconductor layer; a lower insulating layer disposed on the semiconductor layer; a multilayer structure including a first structure and a second structure on the first structure, the first structure and the second structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, the multilayer structure including an opening therein; a gate dielectric extending along sides and a bottom of the opening; and a channel structure disposed on the gate dielectric and on the sides and the bottom of the opening, and extending through the lower insulating layer and electrically connected to the semiconductor layer, ​ ​ The opening includes a first portion extending vertically through the lower insulating layer and further extending to at least one layer of the first structure, and a second portion extending vertically through the second structure, The first portion of the opening has a first width, and the second portion of the opening has a second width smaller than the first width, A height of the first portion of the opening is smaller than or equal to 1 with respect to the first width, and a height of the second portion of the opening is equal to or greater than 1 with respect to the second width, and The lower insulating layer includes only one insulating layer by a deposition process, the one insulating layer being disposed between the lowermost gate electrode and the semiconductor layer.

12. The nonvolatile memory device of claim 11, wherein, A distance between outer surfaces of the gate dielectric in the first portion of the opening is greater than a distance between outer surfaces of the gate dielectric in the second portion of the opening.

13. The nonvolatile memory device of claim 11, wherein, The channel structure includes a contact portion extending through the lower insulating layer and being in contact with the semiconductor layer.

14. The nonvolatile memory device of claim 11, wherein, No insulating layer other than the lower insulating layer is disposed between the semiconductor layer and the lowermost gate electrode.

15. The nonvolatile memory device of claim 11, wherein, A height of the second structure is greater than a height of the first structure, The height of the first structure is a vertical distance between an upper surface of the lower insulating layer and an upper surface of an uppermost layer of the first structure, and The height of the second structure is a vertical distance between the upper surface of the uppermost layer of the first structure and an upper surface of an uppermost layer of the second structure.

16. A nonvolatile memory device, comprising: a semiconductor layer; a lower insulating layer disposed on an upper surface of the semiconductor layer; a lower stack of a plurality of layers disposed on the lower insulating layer and including a lower gate electrode and a lower interlayer insulating layer disposed on the lower gate electrode; an upper stack of a plurality of layers disposed on the lower stack of a plurality of layers and including an upper gate electrode and an upper interlayer insulating layer alternately stacked in a vertical direction; and a pillar structure having a first portion extending vertically through at least one layer of the lower stack of a plurality of layers and the lower insulating layer and a second portion extending vertically through the upper stack of a plurality of layers, wherein the pillar structure includes a gate dielectric facing the lower stack of a plurality of layers and the upper stack of a plurality of layers and a vertical channel extending through the lower insulating layer, the gate dielectric being interposed between the vertical channel and the lower stack and the upper stack, a first width of the first portion of the pillar structure is greater than a second width of the second portion of the pillar structure, a height of the first portion is smaller than or equal to 1 with respect to the first width, a height of the second portion is equal to or greater than 1 with respect to the second width, and the lower insulating layer includes only one insulating layer by a deposition process, the one insulating layer being disposed between the lower stack and the semiconductor layer.

17. The nonvolatile memory device of claim 16, wherein, The first portion is disposed in a first opening portion extending through the lower stack, and the second portion is disposed in a second opening portion extending through the upper stack.

18. The nonvolatile memory device of claim 16, wherein, A distance between outer surfaces of the gate dielectric in the first portion of the pillar structure is greater than a distance between outer surfaces of the gate dielectric in the second portion of the pillar structure.

19. The nonvolatile memory device of claim 16, wherein, No insulating layer other than the lower insulating layer is disposed between the semiconductor layer and the lower stack.

20. The nonvolatile memory device of claim 16, wherein, The first portion of the pillar structure contacts the lower stack of a plurality of layers and has a rectangular cross-sectional shape, and The second part of the columnar structure contacts the upper stack of multiple layers and has a gradually tapering cross-sectional shape from the upper surface of the upper stack of multiple layers to the first part of the columnar structure.

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