A method of forming a planar flash memory device

Abstract

This application provides a method for forming a planar flash memory device. The method includes: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region; forming a first trench in the semiconductor substrate between the first region and the second region; forming a plurality of second trenches in the semiconductor substrate of the first region; depositing an isolation material in the first trenches and the second trenches and on the surface of the semiconductor substrate, the surface of the isolation material being higher than the surface of the semiconductor substrate by a predetermined height, the predetermined height being the effective field height of the planar flash memory device; forming a sacrificial layer on the surface of the first isolation structure and the surface of the second isolation structure; forming a dielectric layer on the surface of the semiconductor substrate with a surface coplanar with the sacrificial layer; and removing the sacrificial layer. The effective field height of the planar flash memory device is formed by a chemical mechanical polishing process, which can improve the uniformity of the effective field height and improve the surface morphology of the isolation structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a method for forming a planar flash memory device. Background Technology

[0002] The main feature of flash memory is that it can retain stored information for a long time without power, and it has the advantages of high integration, fast access speed, and easy erasure and rewriting. Therefore, it has been widely used in many fields such as microcomputers and automation control.

[0003] Depending on their structure, flash memory devices can be divided into two types: NOR Flash and NAND Flash. NAND flash memory devices have advantages such as higher cell density, higher storage density, and faster write and erase speeds, and have gradually become the most commonly used structure in flash memory devices.

[0004] The effective field height of the current planar NAND flash memory device storage area is significantly affected by the process route, which greatly affects the consistency of the write and erase voltages of the working cells and the response speed during the corresponding period.

[0005] Therefore, it is necessary to provide a more effective and reliable technical solution. Summary of the Invention

[0006] This application provides a method for forming a planar flash memory device, which can improve the uniformity of the effective field height in the storage area and improve the surface morphology of the effective field in the storage area.

[0007] This application provides a method for forming a planar flash memory device, comprising: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region, the first region being a storage region and the second region being a peripheral circuit region; forming a first trench in the semiconductor substrate between the first region and the second region, the depth of the second trench being less than the depth of the first trench and the width of the second trench being less than the width of the first trench; forming a plurality of second trenches in the semiconductor substrate in the first region; depositing an isolation material in the first trench and the second trenches and on the surface of the semiconductor substrate, the surface of the isolation material being higher than the surface of the semiconductor substrate by a predetermined height, wherein the isolation material at corresponding positions of the first trench and the second trench respectively forms a first isolation structure and a second isolation structure, wherein the predetermined height is the effective field height of the planar flash memory device; forming a sacrificial layer on the surface of the first isolation structure and the surface of the second isolation structure; forming a dielectric layer on the surface of the semiconductor substrate with a surface coplanar with the sacrificial layer; and removing the sacrificial layer.

[0008] In some embodiments of this application, a method for forming a first trench in a semiconductor substrate between the first region and the second region includes: forming a patterned first photoresist layer on the surface of the semiconductor substrate, the patterned first photoresist layer defining the location of the first trench; dry etching the semiconductor substrate using the patterned first photoresist layer as a mask to form the first trench; and removing the patterned first photoresist layer.

[0009] In some embodiments of this application, a method for forming a plurality of second trenches in a semiconductor substrate in the first region includes: forming a patterned second photoresist layer on the surface of the semiconductor substrate and in the first trenches, the patterned second photoresist layer defining the positions of the plurality of second trenches in the first region; dry etching the semiconductor substrate in the first region using the patterned second photoresist layer as a mask to form the plurality of second trenches; and removing the patterned second photoresist layer.

[0010] In some embodiments of this application, after the formation of the first trench and the plurality of second trenches and before the formation of the first isolation structure and the second isolation structure, the method further includes: using an annealing process on the semiconductor substrate to repair lattice damage on the surfaces of the first trench and the plurality of second trenches caused by etching.

[0011] In some embodiments of this application, the method of depositing an isolation material in the first trench and the second trench and on the surface of a semiconductor substrate, wherein the surface of the isolation material is higher than the surface of the semiconductor substrate by a predetermined height, includes: depositing an isolation material layer on the surface of the semiconductor substrate and in the first trench and the plurality of second trenches; planarizing the isolation material layer using a chemical mechanical polishing process and making the surface of the isolation material layer higher than the surface of the semiconductor substrate by a predetermined height, wherein the isolation material layers at corresponding positions in the first trench and the second trench respectively form a first isolation structure and a second isolation structure.

[0012] In some embodiments of this application, the method of forming a sacrificial layer on the surface of the first isolation structure and the surface of the second isolation structure includes: forming a sacrificial layer on the surface of the isolation material layer; etching away the sacrificial layer and the isolation material layer located outside the corresponding positions of the first isolation structure and the plurality of second isolation structures to expose the surface of the semiconductor substrate.

[0013] In some embodiments of this application, a method for forming a dielectric layer on the surface of the semiconductor substrate with a surface coplanar with the sacrificial layer includes: forming a dielectric layer on the surface of the semiconductor substrate and the surface of the sacrificial layer with a surface higher than the surface of the sacrificial layer; and polishing the dielectric layer using a chemical mechanical polishing process to expose the sacrificial layer.

[0014] In some embodiments of this application, the height of the surfaces of the first isolation structure and the plurality of second isolation structures above the surface of the semiconductor substrate is 50 angstroms to 150 angstroms.

[0015] In some embodiments of this application, the material of the sacrificial layer is an organic dielectric layer material.

[0016] In some embodiments of this application, the method for removing the sacrificial layer includes an ashing process.

[0017] The method for forming a planar flash memory device described in this application involves forming the effective field of the storage area through a chemical mechanical polishing process, which can improve the height uniformity of the effective field of the storage area and improve the surface morphology of the effective field of the storage area. Attached Figure Description

[0018] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0019] in:

[0020] Figures 1 to 6 This is a schematic diagram of the steps in a method for forming a semiconductor structure.

[0021] Figure 7 This is a flowchart of the method for forming a semiconductor structure according to an embodiment of this application;

[0022] Figures 8 to 21 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0023] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0024] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0025] Figures 1 to 6 This is a schematic diagram of the steps in a method for forming a semiconductor structure.

[0026] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a first region 101 and a second region 102. The first region 101 is a storage region for forming a memory; the second region 102 is a peripheral circuit region for forming peripheral circuits.

[0027] refer to Figure 2 As shown, a dielectric layer 110 and a hard mask layer 120 are sequentially formed on the surface of the semiconductor substrate 100. The dielectric layer 110 is the material for subsequent fabrication of memory devices, and the hard mask layer 120 is used to protect the dielectric layer 110.

[0028] refer to Figure 3 As shown, a first trench 130 is formed in the hard mask layer 120, the dielectric layer 110, and the semiconductor substrate 100 between the first region 101 and the second region 102 (that is, at the position where the first region 101 and the second region 102 are adjacent). The first trench 130 is used to form an isolation structure that isolates the first region 101 and the second region 102.

[0029] refer to Figure 4 As shown, a plurality of second trenches 140 are formed in the hard mask layer 120, dielectric layer 110, and semiconductor substrate 100 of the first region 101. In conventional processes, the plurality of second trenches 140 are formed simultaneously by etching in the semiconductor substrate 100 and the dielectric layer 110. This results in a high depth-to-width ratio of the plurality of second trenches 140, which easily leads to bit line tilting at small linewidth process nodes (that is, the dielectric layer 110 and semiconductor substrate 100 separated by the plurality of second trenches 140 are prone to tilting). This not only seriously affects the uniformity of the subsequent effective field height, especially the uniformity on the same cross section, but also generates a large number of physical defects in subsequent processes, affecting device performance.

[0030] refer to Figure 5 As shown, the first trench 130 and the second trench 140 are filled with insulating material to form a first insulating structure 131 and a second insulating structure 141 with surfaces higher than the surface of the hard mask layer 120, respectively.

[0031] refer to Figure 6 As shown, the hard mask layer 120 is removed, and the surfaces of the first isolation structure 131 and the second isolation structure 141 are made slightly higher than the surface of the semiconductor substrate 100 (wherein, the portion of the first isolation structure 131 and the second isolation structure 141 that is higher than the surface of the semiconductor substrate 100 is called the effective field). Figure 6As shown, in order to protect the morphology of the dielectric layer 110, the hard mask layer 120 and the excess isolation material on the surface of the dielectric layer 110 need to be removed by wet etching in the last step. The wet etching process not only causes excessive etching in the morphological depressions between the dielectric layers when the effective field is finally formed, affecting the control of shape and height uniformity, but also causes the device to form gap-like physical defects due to the difference in the etching rate of the isolation material.

[0032] In summary, in planar NAND flash memory devices manufactured using conventional processes, the uniformity of the effective field height in the storage region is significantly affected by the process route. This greatly impacts the consistency of write and erase voltages of the working cells and the response speed during these processes. This uniformity difference manifests primarily in: significant variations in the effective field height and surface morphology of adjacent cells on the same cross-section; and significant variations in the effective field height and surface morphology within the wafer plane (i.e., the effective field itself). Therefore, developing a novel process route to address the uniformity issue of the effective field height in memory is essential. This can not only effectively improve problems such as mutual interference between NAND memory cells and inconsistent activation rates, but also fundamentally enhance the reliability of the memory device.

[0033] To address the aforementioned issues, this application provides a method for forming a planar flash memory device, wherein the effective field of the storage area is formed through a chemical mechanical polishing process, which can improve the height uniformity of the effective field of the storage area and improve the surface morphology of the effective field of the storage area.

[0034] Figure 7 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of this application.

[0035] Embodiments of this application provide a method for forming a planar flash memory device, with reference to... Figure 7 As shown, it includes:

[0036] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a first region and a second region;

[0037] Step S2: Form a first trench in the semiconductor substrate between the first region and the second region;

[0038] Step S3: Form a plurality of second trenches in the semiconductor substrate of the first region;

[0039] Step S4: Fill the first trench and the second trench with isolation material to form a first isolation structure and a second isolation structure with surfaces higher than the surface of the semiconductor substrate, respectively;

[0040] Step S5: Form a sacrificial layer on the surface of the first isolation structure and the surface of the second isolation structure;

[0041] Step S6: Form a dielectric layer on the surface of the semiconductor substrate with a surface coplanar with the sacrificial layer;

[0042] Step S7: Remove the sacrificial layer.

[0043] Figures 8 to 21 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application.

[0044] refer to Figure 7 and Figure 8 As shown, in step S1, a semiconductor substrate 200 is provided, the semiconductor substrate 200 including a first region 201 and a second region 202. In some embodiments of this application, the first region 201 is a storage region for forming a storage circuit; the second region 202 is a peripheral circuit region for forming a peripheral circuit.

[0045] In some embodiments of this application, the semiconductor substrate 200 is made of (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. Furthermore, the semiconductor substrate 200 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of this application, the semiconductor substrate 200 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0046] refer to Figure 7 and Figures 9 to 11 As shown, in step S2, a first trench 210 is formed in the semiconductor substrate 100 between the first region 201 and the second region 202 (that is, at the position where the first region 201 and the second region 202 are adjacent). The first trench 210 isolates the first region 201 and the second region 202, and is used to form a first isolation structure that isolates the first region 201 and the second region 202.

[0047] refer to Figure 9 As shown, a patterned first photoresist layer 211 is formed on the surface of the semiconductor substrate 200, and the patterned first photoresist layer 211 defines the position of the first trench 210.

[0048] In some embodiments of this application, the method for forming the patterned first photoresist layer 211 includes: spin-coating a first photoresist layer on the surface of the semiconductor substrate 200; and exposing and developing the first photoresist layer to form the patterned first photoresist layer 211.

[0049] refer to Figure 10 As shown, the semiconductor substrate 100 is dry-etched using the patterned first photoresist layer 211 as a mask to form the first trench 210. Dry etching has the advantage of easier control of the etching direction compared to wet etching, avoiding the etching through between adjacent first and second trenches. The etching gas used in the dry etching is, for example, a fluorocarbon compound such as CF4 or CF2H2. The etching time for the dry etching is, for example, 100 to 200 seconds.

[0050] refer to Figure 11 As shown, the patterned first photoresist layer 211 is removed. The method for removing the patterned first photoresist layer 211 is, for example, an ashing process.

[0051] In some embodiments of this application, the aspect ratio of the first trench 210 is, for example, 5 to 12, the depth of the first trench is, for example, 2500-3500 angstroms, and the width of the first trench is, for example, 300-500 angstroms.

[0052] refer to Figure 7 and Figures 12 to 14 As shown, in step S3, a plurality of second trenches 220 are formed in the semiconductor substrate 200 of the first region 201. The plurality of second trenches 220 are used to form a second isolation structure, which is used to isolate adjacent memory devices. It should be noted that this embodiment only uses two second trenches 220 as an example, but the number of second trenches 220 is not limited. The number and size of the second trenches 220 can be set according to actual needs.

[0053] In some embodiments of this application, the depth of the second trench 220 is less than the depth of the first trench 210, and the width of the second trench 220 is less than the width of the first trench 310.

[0054] In some embodiments of this application, the aspect ratio of the second trench 220 is, for example, 6 to 16, the depth of the second trench is, for example, 1500-2500 angstroms, and the width of the second trench is, for example, 150-250 angstroms.

[0055] refer to Figure 12 As shown, a patterned second photoresist layer 221 is formed on the surface of the semiconductor substrate 200 and in the first trench 210, and the patterned second photoresist layer 221 defines the positions of the plurality of second trenches 220 in the first region.

[0056] In some embodiments of this application, the method for forming the patterned second photoresist layer 221 includes: spin-coating the second photoresist layer on the surface of the semiconductor substrate 200 and the first trench 210; and exposing and developing the second photoresist layer to form the patterned second photoresist layer 221.

[0057] refer to Figure 13 As shown, the semiconductor substrate 200 of the first region 201 is dry-etched using the patterned second photoresist layer 221 as a mask to form the plurality of second trenches 220. The dry etching method has the advantage of easier control of the etching direction compared to wet etching, avoiding the etching through between adjacent first trenches. The etching gas used in the dry etching is, for example, a fluorocarbon compound such as CF4 or CF2H2. The etching time for the dry etching is, for example, 100 to 200 seconds.

[0058] refer to Figure 14 As shown, the patterned second photoresist layer 221 is removed. The method for removing the patterned second photoresist layer 221 is, for example, an ashing process.

[0059] The embodiments of this application do not limit the order in which the steps of forming the first trench 210 and forming the second trench 220 are performed. That is, the first trench 210 can be formed first, and then the second trench 220 can be formed; the second trench 220 can be formed first, and then the first trench 210 can be formed; or even the first trench 210 and the second trench 220 can be formed simultaneously.

[0060] In some embodiments of this application, after forming the first trench 210 and the plurality of second trenches 220 and before forming the first isolation structure 211 and the second isolation structure 221, the method further includes: performing an annealing process on the semiconductor substrate 200 to repair lattice damage on the surfaces of the first trench 210 and the plurality of second trenches 220 caused by etching.

[0061] Etching processes can damage the surface of the semiconductor substrate, creating lattice damage. This can affect subsequent processes for forming the first and second isolation structures in the first trench 210 and the second trench 220, thus impacting their functionality. Therefore, an annealing process is needed to repair the lattice damage before forming the first and second isolation structures. When repairing the lattice damage using annealing, a thin oxide layer (not shown in the figures for simplicity) is formed on the surface of the semiconductor substrate 200 and the surfaces of the first trench 210 and the second trench 220. The thickness of the oxide layer is, for example, 100 to 200 angstroms.

[0062] In conventional processes, refer to Figure 4 The plurality of second trenches penetrate the entire dielectric layer and extend into the semiconductor substrate, resulting in a high depth-to-width ratio. This leads to bit line tilting at small linewidth process nodes (i.e., the dielectric layer and semiconductor substrate between the plurality of second trenches are prone to tilting). This not only severely affects the uniformity of the subsequent effective field height, especially the uniformity on the same cross-section, but also generates a large number of physical defects in subsequent processes, affecting device performance. In the technical solution of this application, reference is made to... Figure 14 As shown, the plurality of second trenches are located only in the semiconductor substrate, and the aspect ratio of the plurality of second trenches is not high, so the etching process is less challenging and bit line tilting is less likely to occur, thereby improving device reliability.

[0063] refer to Figure 7 and Figures 15 to 16 As shown, in step S4, isolation material is filled into the first trench 210 and the second trench 220 to form a first isolation structure 211 and a second isolation structure 221 with surfaces higher than the surface of the semiconductor substrate 200, respectively. Specifically, isolation material is deposited in the first trench 210 and the second trench 220 and on the surface of the semiconductor substrate 200, wherein the surface of the isolation material is higher than the surface of the semiconductor substrate 200 by a predetermined height. The isolation material at corresponding positions in the first trench 210 and the second trench 220 forms the first isolation structure 211 and the second isolation structure 221, respectively, wherein the predetermined height is the effective field height of the planar flash memory device.

[0064] refer to Figure 15 As shown, an isolation material layer 230 is deposited on the surface of the semiconductor substrate 200 and in the first trench 210 and the plurality of second trenches 220. The material of the isolation material layer 230 is, for example, silicon oxide or silicon nitride. The method for forming the isolation material layer 230 includes chemical vapor deposition or physical vapor deposition.

[0065] refer to Figure 16 As shown, the isolation material layer 230 is planarized using a chemical mechanical polishing process, and the surface of the isolation material layer 230 is made higher than the surface of the semiconductor substrate 200 by a predetermined height. The isolation material layers at corresponding positions of the first trench 210 and the second trench 220 respectively form a first isolation structure 211 and a second isolation structure 221. The predetermined height (i.e., the height by which the first isolation structure 211 and the second isolation structure 221 are higher than the surface of the semiconductor substrate 200) is the effective field height of the planar flash memory device. The effective field height is related to the operating voltage of the memory device.

[0066] In some embodiments of this application, the height of the surfaces of the first isolation structure 211 and the plurality of second isolation structures 221 above the surface of the semiconductor substrate 200 (that is, the height of the effective field) is 50 angstroms to 150 angstroms.

[0067] In conventional processes, refer to Figures 5 to 6 The first and second isolation structures are ultimately formed by etching processes. Therefore, the surface morphology (i.e., the surface of the effective field) of the first and second isolation structures is poor, and the surface height is inconsistent, easily resulting in "V-shaped" or "nipple-shaped" surface morphologies, affecting device performance. In the technical solution of this application, reference is made to... Figures 15 to 16 As shown, the first and second isolation structures are ultimately formed by chemical mechanical polishing. Therefore, the surface morphology (i.e. the surface of the effective field) of the first and second isolation structures is better and the surface height is more consistent, which can avoid the appearance of "V-shaped" or "nipple-shaped" surface morphologies, thereby improving the reliability of the device.

[0068] refer to Figure 7 and Figures 17 to 18 As shown, in step S5, a sacrificial layer 240 is formed on the surface of the first isolation structure 211 and the surface of the second isolation structure 221.

[0069] refer to Figure 17 As shown, a sacrificial layer 240 is formed on the surface of the insulating material layer 230.

[0070] In some embodiments of this application, the sacrificial layer 240 is made of an organic dielectric layer (ODL). This ODL material is easily removed by ashing, eliminating the need for etching processes that are difficult to control in terms of surface morphology, thus ensuring that the surface morphology of the effective field remains unaffected.

[0071] In some embodiments of this application, the method for forming the sacrificial layer 240 on the surface of the insulating material layer 230 includes chemical vapor deposition or physical vapor deposition processes, etc.

[0072] refer to Figure 18 As shown, the sacrificial layer 240 and the isolation material layer 230 located outside the corresponding positions of the first isolation structure 211 and the plurality of second isolation structures 221 are etched away to expose the surface of the semiconductor substrate 200, leaving only the sacrificial layer 240 located on the surface of the first isolation structure 211 and the plurality of second isolation structures 221.

[0073] refer to Figure 7 and Figures 19 to 20As shown, in step S6, a dielectric layer 250 is formed on the surface of the semiconductor substrate 200, the surface of which is coplanar with the sacrificial layer 240.

[0074] refer to Figure 19 As shown, a dielectric layer 250 with a surface area higher than that of the sacrificial layer 240 is formed on the surface of the semiconductor substrate 200 and the surface of the sacrificial layer 240. The material of the dielectric layer 250 is, for example, silicon oxide or polycrystalline silicon. The method for forming the dielectric layer 250 includes chemical vapor deposition or physical vapor deposition.

[0075] refer to Figure 20 As shown, the dielectric layer 250 is ground using a chemical mechanical polishing process until the sacrificial layer 240 is exposed.

[0076] refer to Figure 7 and Figure 21 Step S7: Remove the sacrificial layer 240. The method for removing the sacrificial layer 240 includes, for example, an ashing process. The material of the sacrificial layer 240 is ODL material, which is relatively easy to remove using an ashing process and will not affect the surfaces (i.e., the effective field surfaces) of the first isolation structure 211 and the second isolation structure 221.

[0077] In the technical solution of this application, the dielectric layer 250 is formed by "first forming the sacrificial layer 240 corresponding to the positions of the first isolation structure 211 and the second isolation structure 221, then forming the dielectric layer 250 isolated by the sacrificial layer 240, and finally removing the sacrificial layer 240 to leave the discrete dielectric layer 250", instead of using the conventional method of "first forming the dielectric layer 250 covering the surface of the isolation material layer 230, and then using an etching process to etch out the discrete dielectric layer 250". This avoids the etching process from having any impact on the surfaces (i.e., the effective field surfaces) of the first isolation structure 211 and the second isolation structure 221.

[0078] The technical solution of this application optimizes the process route by changing the traditional method of first forming the bit line morphology and then filling the second isolation structure and forming the effective field height, to first forming the effective field height and then forming the bit line morphology. This optimization of the process route can specifically address the shortcomings of the traditional process. First, when forming the effective field height, the traditional dry etching followed by wet etching method is optimized to use a chemical mechanical polishing process (see reference). Figures 15 to 16 This not only ensures the consistency of the effective field height at different locations within the wafer to the greatest extent possible, but also effectively controls the final morphology of the effective field surface, avoiding the occurrence of "V-shaped" or "nipple-shaped" surface morphologies that could affect device reliability. Secondly, in the new process route, the aspect ratio of the second trench (refer to...) Figure 14 ) and traditional process routes (reference) Figure 4 Compared to the previous method, this significantly reduces the risk of bit line tilting. Furthermore, because the formation of the effective field height is done upstream and a sacrificial layer is formed on top, subsequent processes can minimize their impact. Finally, in the new process route, the bit line is formed by burning off the sacrificial layer with oxygen during an ashing process (see reference). Figure 21 This avoids the damage to the effective field height and bit lines caused by excessive etching, which is a consequence of wet etching.

[0079] The planar flash memory device formation method described in this application uses a chemical mechanical polishing process to form the effective field of the storage area, which can improve the height uniformity of the effective field of the storage area and improve the surface morphology of the effective field of the storage area.

[0080] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0081] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0082] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0083] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0084] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a planar flash memory device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region, the first region being a storage region and the second region being a peripheral circuit region; A first trench is formed in a semiconductor substrate between the first region and the second region; A plurality of second trenches are formed in the semiconductor substrate of the first region, wherein the depth of the second trenches is less than the depth of the first trenches and the width of the second trenches is less than the width of the first trenches. An isolation material is deposited in the first trench and the second trench and on the surface of the semiconductor substrate. The surface of the isolation material is higher than the surface of the semiconductor substrate by a set height. The isolation material at corresponding positions in the first trench and the second trench respectively forms a first isolation structure and a second isolation structure. The set height is the effective field height of the planar flash memory device. A sacrificial layer is formed on the surface of the first isolation structure and the surface of the second isolation structure, and the isolation material on the surface of the semiconductor substrate is removed; A dielectric layer with a surface coplanar with the sacrificial layer is formed on the surface of the semiconductor substrate; Remove the sacrificial layer.

2. The method for forming a flash memory device as described in claim 1, characterized in that, A method for forming a first trench in a semiconductor substrate between the first region and the second region includes: A patterned first photoresist layer is formed on the surface of the semiconductor substrate, and the patterned first photoresist layer defines the location of the first trench; The first trench is formed by dry etching of the semiconductor substrate using the patterned first photoresist layer as a mask. Remove the patterned first photoresist layer.

3. The method for forming a flash memory device as described in claim 1, characterized in that, A method for forming a plurality of second trenches in a semiconductor substrate in the first region includes: A patterned second photoresist layer is formed on the surface of the semiconductor substrate and in the first trench, the patterned second photoresist layer defining the positions of the plurality of second trenches in the first region; The semiconductor substrate is dry-etched using the patterned second photoresist layer as a mask to form the plurality of second trenches; Remove the patterned second photoresist layer.

4. The method for forming a flash memory device as described in claim 1, characterized in that, After forming the first trench and the plurality of second trenches, and before forming the first isolation structure and the second isolation structure, the method further includes performing an annealing process on the semiconductor substrate.

5. The method for forming a flash memory device as described in claim 1, characterized in that, A method for depositing an isolation material in the first trench and the second trench and on the surface of a semiconductor substrate, wherein the surface of the isolation material is higher than the surface of the semiconductor substrate by a predetermined height, includes: An isolation material layer is deposited on the surface of the semiconductor substrate and in the first trench and the plurality of second trenches; The isolation material layer is planarized using a chemical mechanical polishing process, and the surface of the isolation material layer is made higher than the surface of the semiconductor substrate by a set height, wherein the isolation material layers at the corresponding positions of the first trench and the second trench respectively form a first isolation structure and a second isolation structure.

6. The method for forming a flash memory device as described in claim 5, characterized in that, A method for forming a sacrificial layer on the surfaces of the first and second isolation structures includes: A sacrificial layer is formed on the surface of the insulating material layer; Etching removes the sacrificial layer and isolation material layer located outside the corresponding positions of the first isolation structure and the plurality of second isolation structures to expose the surface of the semiconductor substrate.

7. The method for forming a flash memory device as described in claim 1, characterized in that, A method for forming a dielectric layer on the surface of the semiconductor substrate with a surface coplanar with the sacrificial layer includes: A dielectric layer with a surface higher than the surface of the sacrificial layer is formed on the surface of the semiconductor substrate and the surface of the sacrificial layer; The dielectric layer is ground using a chemical mechanical polishing process until the sacrificial layer is exposed.

8. The method for forming a flash memory device as described in claim 1, characterized in that, The height of the surfaces of the first isolation structure and the plurality of second isolation structures above the surface of the semiconductor substrate is 50 to 150 angstroms.

9. The method for forming a flash memory device as described in claim 1, characterized in that, The sacrificial layer is made of an organic dielectric layer material.

10. The method for forming a flash memory device as described in claim 9, characterized in that, The method for removing the sacrificial layer includes an ashing process.

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