Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device, wherein the display substrate comprises a substrate, a pixel definition layer and a first electrode disposed on the substrate, the pixel definition layer comprises an opening, a side wall of the first electrode is in a stepped shape, and the opening exposes the first electrode; the pixel definition layer covers at least part of the side wall of the first electrode, and a surface of the first electrode away from the substrate is orthographically projected on the substrate within an orthographic projection of the opening on the substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and particularly relates to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Micro Organic Light-Emitting Diode (Micro-OLED) is a micro display developed in recent years. Silicon-based OLED is a micro display. Silicon-based OLED can not only realize active addressing of pixels, but also can realize preparation of various functional circuits including time control (TCON) circuit, over-current protection (OCP) circuit and the like on a silicon-based substrate, which is conducive to reducing the system size and realizing light weight. Silicon-based OLED is prepared by using mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit process, has the advantages of small size, high resolution (Pixels Per Inch, PPI), high refresh rate and the like, and is widely applied in the field of Virtual Reality (VR) or Augmented Reality (AR) near-eye display. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the protection scope of the claims.

[0004] In a first aspect, the present disclosure provides a display substrate, comprising: a substrate substrate, and a pixel definition layer and a first electrode disposed on the substrate substrate, the pixel definition layer comprising: an opening, a side wall of the first electrode being stepped, and the opening exposing the first electrode.

[0005] The pixel definition layer covers at least part of the side wall of the first electrode, and a surface of the first electrode away from the substrate substrate is orthographically projected on the substrate substrate within an orthographic projection of the opening on the substrate substrate.

[0006] In an exemplary embodiment, the first structure is located on a side of the second structure away from the substrate substrate.

[0007] An orthographic projection of the second structure on the substrate substrate covers an orthographic projection of the first structure on the substrate substrate, and a thickness of the second structure is greater than a thickness of the first structure.

[0008] The side wall of the second structure is stepped.

[0009] In an exemplary embodiment, the second structure comprises: a first sub-layer, a second sub-layer and a third sub-layer which are sequentially stacked on the substrate substrate; the thickness of the second sub-layer is greater than the thickness of the first sub-layer and greater than the thickness of the third sub-layer;

[0010] The orthogonal projection of the surface of the first sub-layer away from the substrate substrate on the substrate substrate covers the orthogonal projection of the second sub-layer on the substrate substrate, the orthogonal projection of the surface of the second sub-layer close to the substrate substrate on the substrate substrate covers the orthogonal projection of the surface of the second sub-layer away from the substrate substrate on the substrate substrate, and the orthogonal projection of the surface of the second sub-layer away from the substrate substrate covers the orthogonal projection of the third sub-layer on the substrate substrate;

[0011] The sidewall of the second sub-layer is stepped;

[0012] The sidewall of the second sub-layer comprises: a first inclined surface, a step surface and a second inclined surface;

[0013] The step surface is parallel to the substrate substrate, the first inclined surface is located on the side of the step surface away from the substrate substrate, the second inclined surface is located on the side of the step surface close to the substrate substrate, and the step surface connects the first inclined surface and the second inclined surface.

[0014] In an exemplary embodiment, the pixel definition layer comprises: a first inorganic layer and a second inorganic layer which are stacked on the substrate substrate, the first inorganic layer is located on the side of the second inorganic layer close to the substrate substrate, and the orthogonal projection of the second inorganic layer on the substrate substrate covers the orthogonal projection of the first inorganic layer on the substrate substrate;

[0015] The first inorganic layer comprises a first via, the second inorganic layer comprises a second via, the opening comprises the first via and the second via, and the orthogonal projection of the first via on the substrate substrate covers the orthogonal projection of the second via on the substrate substrate.

[0016] In an exemplary embodiment, the orthogonal projection of the first inorganic layer on the substrate substrate at least partially overlaps the orthogonal projection of the step surface of the second sub-layer on the substrate substrate, and does not overlap the orthogonal projection of the first inclined surface of the second sub-layer on the substrate substrate.

[0017] In an exemplary embodiment, the center lines of the first via and the second via coincide and are perpendicular to the substrate substrate;

[0018] The distance between the sidewall of the first inorganic layer close to the center line of the first via hole and the center line of the first via hole is greater than or equal to the distance between the sidewall of the second inorganic layer close to the center line of the first via hole and the center line of the first via hole.

[0019] In an example embodiment, when the distance between the sidewall of the first inorganic layer close to the first electrode and the center line of the first electrode is greater than the distance between the sidewall of the second inorganic layer close to the first electrode and the center line of the first electrode, the orthographic projection of the second inorganic layer on the substrate further partially overlaps with the orthographic projection of the first inclined surface of the second sub-layer on the substrate, and does not overlap with the orthographic projection of the first sub-layer on the substrate.

[0020] In an example embodiment, the pixel definition layer further comprises: a third inorganic layer and a fourth inorganic layer, the third inorganic layer is located on the side of the first inorganic layer close to the substrate, and the fourth inorganic layer is located on the side of the third inorganic layer close to the substrate.

[0021] The orthographic projection of the third inorganic layer on the substrate partially overlaps with the orthographic projection of the first structure on the substrate, the orthographic projection of the fourth inorganic layer on the substrate at least partially overlaps with the orthographic projection of the first sub-layer of the second structure on the substrate, and the orthographic projection of the third inorganic layer and the fourth inorganic layer on the substrate does not overlap with the orthographic projection of the surface of the first electrode away from the substrate on the substrate.

[0022] The third inorganic layer is provided with a third via hole, and the fourth inorganic layer is provided with a fourth via hole; the opening comprises: the first via hole, the second via hole, the third via hole and the fourth via hole.

[0023] The orthographic projection of the second via hole on the substrate covers the orthographic projection of the third via hole on the substrate and the orthographic projection of the fourth via hole on the substrate.

[0024] In an example embodiment, the pixel definition layer further comprises: a first recess, and the sidewall of the first recess is in an undercut structure.

[0025] The orthographic projection of the first recess on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

[0026] In an example embodiment, the third inorganic layer comprises: a bending portion and a flat portion; the bending portion covers the sidewall of the first electrode and is in a stepped structure, and the flat portion is parallel to the substrate.

[0027] The first inorganic layer further comprises a fifth via hole, and the second inorganic layer further comprises a sixth via hole, the fifth via hole exposes the third inorganic layer, the first recess comprises the fifth via hole and the sixth via hole, a center line of the fifth via hole coincides with a center line of the sixth via hole, and is perpendicular to the substrate substrate;

[0028] A distance between a side wall of the fifth via hole and the center line of the fifth via hole is greater than a distance between a side wall of the fifth via hole and the center line of the fifth via hole;

[0029] The first inorganic layer on the flat portion is flat away from a surface of the substrate substrate, and the second inorganic layer on the flat portion is flat away from the surface of the substrate substrate.

[0030] In an exemplary embodiment, further comprising: a filling structure disposed in the first recess, a side wall of the filling structure comprises a plurality of second recesses;

[0031] A distance between a surface of the filling structure away from the substrate substrate and the substrate substrate is less than a minimum distance between a surface of the second inorganic layer close to the substrate substrate and the substrate substrate.

[0032] In an exemplary embodiment, the filling structure comprises: a plurality of first filling layers and a plurality of second filling layers stacked, one of the plurality of first filling layers is in contact with the third inorganic layer, and the plurality of first filling layers and the plurality of second filling layers are arranged in an overlapping manner;

[0033] A distance between a side wall of the first filling layer and the center line of the fifth via hole is less than a distance between a side wall of the second filling layer and the center line of the fifth via hole.

[0034] In an exemplary embodiment, a thickness of the first inorganic layer is greater than a thickness of any one of the second inorganic layer, the third inorganic layer and the fourth inorganic layer; a thickness of the second inorganic layer and the third inorganic layer is greater than a thickness of the fourth inorganic layer;

[0035] The first inorganic layer comprises silicon nitride, the second inorganic layer and the fourth inorganic layer comprise silicon oxide, and the third inorganic layer comprises aluminum oxide.

[0036] A thickness of the first filling layer is greater than or equal to a thickness of the second filling layer.

[0037] The first filling layer comprises silicon nitride, and the second filling layer comprises silicon oxide.

[0038] In a second aspect, the disclosure also provides a display device, comprising: the above display substrate.

[0039] In a third aspect, the present disclosure also provides a method for manufacturing a display substrate configured to manufacture the display substrate described above, the method comprising:

[0040] forming a first electrode on a substrate, a sidewall of the first electrode being step-shaped;

[0041] forming a pixel definition layer on the first electrode, the pixel definition layer comprising: an opening exposing the first electrode;

[0042] the pixel definition layer covering at least a part of the sidewall of the first electrode, a surface of the first electrode away from the substrate being orthographically projected on the substrate within an orthographic projection of the opening on the substrate;

[0043] the forming a first electrode on a substrate comprises:

[0044] sequentially depositing a first sub-thin film, a second sub-thin film, a third sub-thin film and a first structure thin film on the substrate, patterning the first sub-thin film, the second sub-thin film, the third sub-thin film and the first structure thin film by a patterning process to form a first original electrode with a slope-shaped sidewall;

[0045] patterning the first original electrode by a patterning process to form the first electrode;

[0046] the forming a pixel definition layer on the first electrode comprises:

[0047] sequentially depositing a fourth inorganic thin film and a third inorganic thin film on the first electrode, patterning the fourth inorganic thin film and the third inorganic thin film by a patterning process to form a fourth inorganic layer and a third inorganic layer of the pixel definition layer; sequentially depositing a first inorganic thin film and a second inorganic thin film on the third inorganic layer, patterning the first inorganic thin film and the second inorganic thin film by a patterning process to form a first inorganic layer and a second inorganic layer of the pixel definition layer;

[0048] Or, a fourth inorganic thin film and a third inorganic thin film are sequentially deposited on the first electrode, the fourth inorganic thin film and the third inorganic thin film are patterned by a patterning process to form a fourth inorganic layer and a third inorganic layer of the pixel definition layer; a plurality of first filling thin films and a plurality of second filling thin films are sequentially deposited on the third inorganic layer, the plurality of first filling thin films and the plurality of second filling thin films are patterned by a patterning process to form a filling structure including a plurality of first filling layers and a plurality of second filling layers; a protective thin film is coated on the third inorganic layer, the protective thin film is processed by a patterning process to form a protective layer surrounding the filling structure, the protective thin film includes a photoresist; a first inorganic thin film and a second inorganic thin film are coated on the third inorganic layer, the first inorganic thin film and the second inorganic thin film are patterned by a patterning process to form a first inorganic layer and a second inorganic layer of the pixel definition layer, and the protective layer is removed.

[0049] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0050] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and serve to explain the principles of the present disclosure, and do not limit the present disclosure.

[0051] Figure 1 Structure diagram of a display substrate provided by an embodiment of the present disclosure Figure 1 ;

[0052] Figure 2 Structure diagram of a display substrate provided by an embodiment of the present disclosure Figure 2 ;

[0053] Figure 3 Circuit principle diagram provided by an exemplary embodiment

[0054] Figure 4 Circuit implementation diagram of a voltage control circuit and a pixel driving circuit

[0055] Figure 5 Structure diagram of an organic light-emitting layer

[0056] Figure 6 Structure diagram of a display substrate provided by an exemplary embodiment Figure 1 ;

[0057] Figure 7 Structure diagram of a display substrate provided by an exemplary embodiment Figure 2 ;

[0058] Figure 8 Diagram after forming a substrate

[0059] Figure 9 This is a schematic diagram after the first primary electrode has been formed;

[0060] Figure 10 This is a schematic diagram after the first electrode has been formed;

[0061] Figure 11 This is a schematic diagram showing the formation of the third inorganic layer;

[0062] Figure 12 for Figure 1 A schematic diagram of the provided display substrate after the second inorganic layer has been formed;

[0063] Figure 13 This is a schematic diagram showing the structure after it has been filled.

[0064] Figure 14 This is a schematic diagram showing the protective layer after it has been formed.

[0065] Figure 15 for Figure 6 A schematic diagram of the provided display substrate after the second inorganic layer has been formed. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0067] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0068] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0069] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of the components are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0070] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0071] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0072] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0073] In this specification, "electrically connected" includes the case where the components are connected together through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having a certain electrical action include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0074] In the present specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus, a state in which the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus, a state in which the angle is 85° or more and 95° or less is also included.

[0075] In the present specification, "film" and "layer" can be exchanged with each other. For example, "conductive layer" can be sometimes replaced with "conductive film". Similarly, "insulating film" can be sometimes replaced with "insulating layer".

[0076] In the present specification, "disposed in the same layer" refers to structures of two (or more) kinds that are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of the precursors for forming the plurality of structures disposed in the same layer are the same, and the finally formed materials can be the same or different.

[0077] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly in the sense, and can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformation due to tolerance, and there can be an inside corner, an arc edge, and deformation, etc.

[0078] In the present disclosure, "about" refers to not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0079] A silicon-based OLED includes a silicon-based backplane integrated with a driving circuit, and a pixel definition layer and an OLED light-emitting element array formed on the silicon-based backplane. The OLED light-emitting element array includes an anode, an organic light-emitting layer, and a cathode. Due to the large thickness of the anode, the step difference of the pixel definition layer located on the anode is large, and when the cathode is subsequently formed, the cathode will be pierced, reducing the reliability of the display product.

[0080] Figure 1 Structure diagram of a display substrate provided by an embodiment of the present disclosure Figure 1 , Figure 2 Structure diagram of a display substrate provided by an embodiment of the present disclosure Figure 2 . As shown in Figure 1 and Figure 2 , the display substrate provided by the embodiment of the present disclosure includes a substrate 10, and a pixel definition layer 20 and a first electrode 30 disposed on the substrate 10. The pixel definition layer 20 includes an opening D1, and the sidewall of the first electrode 30 is in a stepped shape, and the opening D1 exposes the first electrode 30.

[0081] As shown in Figure 1 and Figure 2As shown, the pixel definition layer 20 at least covers part of the sidewall of the first electrode 30, and the orthographic projection of the opening D1 on the substrate 10 covers the orthographic projection of the surface of the first electrode 30 away from the substrate 10 on the substrate 10. For example, the orthographic projection of the surface of the first electrode 30 away from the substrate 10 on the substrate 10 is located within the orthographic projection of the opening D1 on the substrate 10. For example, the distance L1 between the edge of the surface of the first electrode 30 away from the substrate 10 and the center line C1 of the first electrode 30 is less than or equal to the minimum distance L2 between the sidewall of the opening D1 and the center line C1 of the first electrode 30. The center line C1 of the first electrode 30 can be perpendicular to the substrate 10.

[0082] In an exemplary embodiment, the substrate 10 can be a driving backplane.

[0083] In an exemplary embodiment, the display substrate can further include an organic light-emitting layer and a second electrode which are sequentially stacked on the pixel definition layer. The organic light-emitting layer is located between the first electrode and the second electrode and emits light under the joint action of the first electrode and the second electrode.

[0084] In the present disclosure, the distance L1 between the edge of the surface of the first electrode 30 away from the substrate 10 and the center line C1 of the first electrode 30 is less than or equal to the minimum distance L2 between the sidewall of the opening D1 and the center line C1 of the first electrode 30, that is, the orthographic projection of the pixel definition layer 20 and the surface of the first electrode 30 away from the substrate 10 on the substrate 10 do not overlap, and the pixel definition layer 20 only covers the sidewall of the first electrode 30 and does not cover the surface of the first electrode 30 away from the substrate 10. Figure 1 and Figure 2 In the present disclosure, the distance L1 between the edge of the surface of the first electrode 30 away from the substrate 10 and the center line C1 of the first electrode 30 is less than or equal to the minimum distance L2 between the sidewall of the opening D1 and the center line C1 of the first electrode 30, that is, the orthographic projection of the pixel definition layer 20 and the surface of the first electrode 30 away from the substrate 10 on the substrate 10 do not overlap, and the pixel definition layer 20 only covers the sidewall of the first electrode 30 and does not cover the surface of the first electrode 30 away from the substrate 10. Figure 1 and Figure 2 In the present disclosure, the distance L1 between the edge of the surface of the first electrode 30 away from the substrate 10 and the center line C1 of the first electrode 30 is less than or equal to the minimum distance L2 between the sidewall of the opening D1 and the center line C1 of the first electrode 30, that is, the orthographic projection of the pixel definition layer 20 and the surface of the first electrode 30 away from the substrate 10 on the substrate 10 do not overlap, and the pixel definition layer 20 only covers the sidewall of the first electrode 30 and does not cover the surface of the first electrode 30 away from the substrate 10.

[0085] In the present disclosure, the distance L1 between the edge of the surface of the first electrode 30 away from the substrate 10 and the center line C1 of the first electrode 30 is less than or equal to the minimum distance L2 between the sidewall of the opening D1 and the center line C1 of the first electrode 30, that is, the orthographic projection of the pixel definition layer 20 and the surface of the first electrode 30 away from the substrate 10 on the substrate 10 do not overlap, and the pixel definition layer 20 only covers the sidewall of the first electrode 30 and does not cover the surface of the first electrode 30 away from the substrate 10.

[0086] In an exemplary embodiment, as shown in FIG. 1, Figure 1 and Figure 2As shown, the substrate 10 can include a base 11, a transistor 12 disposed in the base 11, and a first conductive pillar 13, a connection electrode 14, and a second conductive pillar 15 disposed in sequence on the base 11. The first conductive pillar 13 is electrically connected to the transistor 12 and the connection electrode 14, respectively, and the second conductive pillar 15 is electrically connected to the connection electrode 14 and the first electrode 30, respectively.

[0087] In an example embodiment, as shown in Figure 1 and Figure 2 , the substrate 10 can further include a first insulating layer 16 between the base 11 and the connection electrode 14, and a second insulating layer 17 between the connection electrode 14 and the first electrode 30.

[0088] In an example embodiment, as shown in Figure 3 and Figure 3 , the first insulating layer 16 is provided with a via hole exposing the transistor 12, and the first conductive pillar 13 is located in the via hole of the first insulating layer.

[0089] In an example embodiment, as shown in Figure 4 and Figure 4 , the second insulating layer 17 is provided with a via hole exposing the connection electrode 14, and the second conductive pillar 15 is located in the via hole of the second insulating layer.

[0090] In an example embodiment, the active layer of the transistor 12 is disposed inside the base 11.

[0091] In an example embodiment, the transistor 12 can be a Metal Oxide Semiconductor (MOS).

[0092] In an example embodiment, the transistor can include an active layer, a gate electrode, a source electrode, a drain electrode, and a gate connection electrode. The source electrode and the drain electrode are connected to the active layer, respectively, and the gate connection electrode is connected to the gate electrode. The transistor can be a bottom gate structure, or can be a top gate structure.

[0093] In an example embodiment, the material of the active layer can include a metal oxide.

[0094] In an example embodiment, the material of the first insulating layer 16 and the second insulating layer 17 includes at least one of an organic material or an inorganic material, for example, silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). The structure of the first insulating layer 16 and the second insulating layer 17 can be a single-layer structure, or can be a multi-layer composite structure.

[0095] In an example embodiment, the material of the first conductive pillar 13 and the second conductive pillar 15 can be tungsten.

[0096] In an exemplary embodiment, the connecting electrode 14 is made of metal, such as silver or aluminum. The structure of the connecting electrode 14 can be a single-layer structure or a multi-layer composite structure.

[0097] In an exemplary embodiment, the display substrate may include a pixel driving circuit, which includes a plurality of transistors 12 located on the substrate 11. The transistors may include at least one of a switching transistor, a driving transistor, a reset transistor, and a compensation transistor.

[0098] Figure 4 This is a schematic diagram of a circuit principle provided for one exemplary implementation. For example... Figure 4 As shown, multiple sub-pixels in the display area are arranged in a regular pattern to form multiple display rows and multiple display columns. Each sub-pixel includes a pixel driving circuit 101 and a light-emitting device 102 connected to the pixel driving circuit 101. The pixel driving circuit 101 includes at least a driving transistor. The control circuit includes at least multiple voltage control circuits 110, each voltage control circuit 110 being connected to multiple pixel driving circuits 101. For example, one voltage control circuit 110 is connected to a pixel driving circuit 101 in a display row, where the first terminals of the driving transistors in the pixel driving circuit 101 of that display row are all connected to the voltage control circuit 110, the second terminal of each driving transistor is connected to the anode of the light-emitting device 102 of that sub-pixel, and the cathode of the light-emitting device 102 is connected to the input terminal of the second power supply signal VSS. The voltage control circuit 110 is connected to the input terminal of the first power supply signal VDD, the input terminal of the initialization signal Vinit, the input terminal of the reset control signal RE, and the input terminal of the light emission control signal EM, respectively. The voltage control circuit 110 is configured to output an initialization signal Vinit to the first terminal of the driving transistor in response to the reset control signal RE, thereby resetting the corresponding light-emitting device 102. The voltage control circuit 110 is also configured to output a first power supply signal VDD to the first terminal of the driving transistor in response to the light-emitting control signal EM, thereby driving the light-emitting device 102 to emit light. By connecting the voltage control circuit 110 to the pixel driving circuits 101 in a display row, the structure of the pixel driving circuits 101 can be simplified, and the area occupied by the pixel driving circuits 101 can be reduced. This allows the display substrate to accommodate more pixel driving circuits 101 and light-emitting devices 102, achieving a high PPI display. The voltage control circuit 110 outputs the initialization signal Vinit to the first terminal of the driving transistor under the control of the reset control signal RE, resetting the corresponding light-emitting device 102. This avoids the influence of the voltage applied to the light-emitting device 102 during the previous frame's illumination on the illumination of the next frame, thus improving image retention.

[0099] In an exemplary embodiment, one voltage control circuit 110 can be connected to the pixel driving circuit 101 in two adjacent sub-pixels in the same display row, or can be connected to the pixel driving circuit 101 in three or more sub-pixels in the same display row.

[0100] Figure 5 A schematic diagram for circuit implementation of the voltage control circuit and the pixel driving circuit. As shown, the light emitting device can include an OLED. The anode of the OLED is connected to the second electrode D of the driving transistor M0, and the cathode of the OLED is connected to the input end of the second power signal VSS. Figure 5

[0101] In an exemplary embodiment, the voltage of the second power signal VSS can be a negative voltage or a ground voltage V GND (typically 0V). The voltage of the initialization signal Vinit can be a ground voltage V GND .

[0102] In an exemplary embodiment, the OLED can be a Micro-OLED or a Mini-OLED, to facilitate the implementation of high PPI display.

[0103] In an exemplary embodiment, the voltage control circuit 110 is connected to two pixel driving circuits 101 in a display row. The pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4 and a storage capacitor Cst, and the voltage control circuit 110 includes a first transistor M1 and a second transistor M2. The driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are transistors prepared in a substrate.

[0104] As shown in FIG. 2, the pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4 and a storage capacitor Cst. The driving transistor M0, the third transistor M3 and the fourth transistor M4 are transistors prepared in a substrate. Figure 5 ​As shown, the control electrode of the first transistor M1 is connected with the input end of the reset control signal RE, configured to receive the reset control signal RE, the first electrode of the first transistor M1 is connected with the input end of the initialization signal Vinit, configured to receive the initialization signal Vinit, and the second electrode of the first transistor M1 is connected with the first electrode S of the corresponding driving transistor M0 and the second electrode of the second transistor M2 respectively. The control electrode of the second transistor M2 is connected with the input end of the light-emitting control signal EM, configured to receive the light-emitting control signal EM, the first electrode of the second transistor M2 is connected with the input end of the first power signal VDD, configured to receive the first power signal VDD, and the second electrode of the second transistor M2 is connected with the first electrode S of the corresponding driving transistor M0 and the second electrode of the first transistor M1 respectively. In the exemplary embodiments, the types of the first transistor M1 and the second transistor M2 can be different, for example, the first transistor M1 is an N-type transistor and the second transistor M2 is a P-type transistor, or the first transistor M1 is a P-type transistor and the second transistor M2 is an N-type transistor. In some possible implementations, the types of the first transistor M1 and the second transistor M2 can be the same, which can be designed and determined according to the actual application environment.

[0105] As Figure 1As shown, the pixel driving circuit 101 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst. The control electrode G of the driving transistor M0, the first electrode S of the driving transistor M0 is connected with the second electrode of the first transistor M1 and the second electrode of the second transistor M2, and the second electrode D of the driving transistor M0 is connected with the anode of the OLED. The control electrode of the third transistor M3 is connected with the input end of the first control electrode scan signal S1 and is configured to receive the first control electrode scan signal S1, the first electrode of the third transistor M3 is connected with the input end of the data signal DA and is configured to receive the data signal DA, and the second electrode of the third transistor M3 is connected with the control electrode G of the driving transistor M0. The control electrode of the fourth transistor M4 is connected with the input end of the second control electrode scan signal S2 and is configured to receive the second control electrode scan signal S2, the first electrode of the fourth transistor M4 is connected with the input end of the data signal DA and is configured to receive the data signal DA, and the second electrode of the fourth transistor M4 is connected with the control electrode G of the driving transistor M0. The first end of the storage capacitor Cst is connected with the control electrode G of the driving transistor M0, and the second end of the storage capacitor Cst is connected with the ground terminal GND. In the exemplary embodiment, the driving transistor M0 can be an N-type transistor, and the types of the third transistor M3 and the fourth transistor M4 can be different, for example, the third transistor M3 is an N-type transistor and the fourth transistor M4 is a P-type transistor. When the voltage of the data signal DA is the voltage corresponding to a high gray scale, the fourth transistor M4 of the P-type is turned on to transmit the data signal DA to the control electrode G of the driving transistor M0, which can avoid the voltage of the data signal DA being affected by the threshold voltage of the third transistor M3 of the N-type. When the voltage of the data signal DA is the voltage corresponding to a low gray scale, the third transistor M3 of the N-type is turned on to transmit the data signal DA to the control electrode G of the driving transistor M0, which can avoid the voltage of the data signal DA being affected by the threshold voltage of the fourth transistor M4 of the P-type. In this way, the voltage range input to the control electrode G of the driving transistor M0 can be improved.

[0106] In the exemplary embodiment, the third transistor M3 is a P-type transistor, and the fourth transistor M4 is an N-type transistor.

[0107] In the exemplary embodiment, the pixel driving circuit can be a 3T1C, 5T1C, or 7T1C circuit structure, or can be a circuit structure with internal compensation or external compensation function.

[0108] Figure 1 A structural schematic diagram of an organic light-emitting layer is shown. As shown, an organic light-emitting layer provided by an exemplary embodiment includes, in sequence from the first electrode to the second electrode, a first light-emitting sub-layer 331, a first charge generation layer 332, a second light-emitting sub-layer 333, a second charge generation layer 334, and a third light-emitting sub-layer 335. Figure 1 As shown, an organic light-emitting layer provided by an exemplary embodiment includes, in sequence from the first electrode to the second electrode, a first light-emitting sub-layer 331, a first charge generation layer 332, a second light-emitting sub-layer 333, a second charge generation layer 334, and a third light-emitting sub-layer 335.

[0109] like Figure 1 As shown, the first light-emitting sublayer 331 emits first-color light and includes a first hole transport layer (HTL) 3311, a first light-emitting material layer (EML) 3312, and a first electron transport layer (ETL) 3313 stacked sequentially. The second light-emitting sublayer 333 emits second-color light and includes a second hole transport layer 3331, a second light-emitting material layer 3332, and a second electron transport layer 3333 stacked sequentially. The third light-emitting sublayer 335 emits third-color light and includes a third hole transport layer 3351, a third light-emitting material layer 3352, and a third electron transport layer 3353 stacked sequentially. A first charge-generating layer 332 is disposed between the first light-emitting sublayer 331 and the second light-emitting sublayer 333 to connect the two sublayers in series and achieve carrier transfer. A second charge-generating layer 334 is disposed between the second light-emitting sublayer 333 and the third light-emitting sublayer 335 to connect the two sublayers in series and achieve carrier transfer. Since the organic light-emitting layer includes a first light-emitting material layer that emits a first color of light, a second light-emitting material layer that emits a second color of light, and a third light-emitting material layer that emits a third color of light, the light ultimately emitted by the organic light-emitting layer is mixed light. For example, the first light-emitting material layer can be configured to be a red light-emitting material layer that emits red light, the second light-emitting material layer to be a green light-emitting material layer that emits green light, and the third light-emitting material layer to be a blue light-emitting material layer that emits blue light, thus the organic light-emitting layer ultimately emits white light.

[0110] In practical implementation, the structure of the organic light-emitting layer can be designed according to actual needs. In each light-emitting sub-layer, a hole injection layer and an electron injection layer can also be set to improve the efficiency of electron and hole injection into the light-emitting material layer. To simplify the structure of the organic light-emitting layer, the first electron transport layer 3313, the first charge generation layer 332, and the second hole transport layer 3331 can be eliminated, that is, the second light-emitting material layer 3332 can be directly set on the first light-emitting material layer 3312.

[0111] In an exemplary embodiment, the organic light-emitting layer may be an organic light-emitting layer that emits a first color light and an organic light-emitting layer that emits a complementary light of the first color light, the two organic light-emitting layers being stacked sequentially relative to the substrate, thereby emitting white light as a whole.

[0112] In an exemplary embodiment, the orthographic projection of the first electrode 30 on the substrate 10 covers the orthographic projection of the organic light-emitting layer on the substrate 10, that is, the cross-sectional area of ​​the first electrode 30 is greater than or equal to the cross-sectional area of ​​the organic light-emitting layer, which can improve the display brightness of the display substrate.

[0113] In an exemplary embodiment, the second electrode may be a planar electrode.

[0114] In an example embodiment, the second electrode is a transmissive electrode for transmitting light emitted by the organic light-emitting layer.

[0115] In an example embodiment, the second electrode is made of indium tin oxide or zinc tin oxide, or other transparent conductive material.

[0116] In an example embodiment, the display substrate further comprises an encapsulation layer and a color film layer on the side of the second electrode away from the substrate.

[0117] In an example embodiment, the encapsulation layer is a laminated structure and comprises a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer.

[0118] In an example embodiment, the first inorganic encapsulation layer is made of silicon nitride. The first inorganic encapsulation layer can prevent damage to the light-emitting structure layer during fabrication of the second inorganic encapsulation layer. The first inorganic encapsulation layer has good encapsulation properties and good adhesion to the second electrode, ensuring the encapsulation effect of the encapsulation layer.

[0119] In an example embodiment, the second inorganic encapsulation layer is made of silicon oxide. The second inorganic encapsulation layer can block water and oxygen from entering the light-emitting structure layer, prolonging the service life of the light-emitting structure layer.

[0120] In an example embodiment, the third organic encapsulation layer is made of parylene. The third organic encapsulation layer has good organic encapsulation properties and good particle coating ability, which can well coat the particles on the film layer to prevent the film layer from being pierced. In addition, the material with organic properties can well release the stress between the inorganic layers, preventing the film layer from generating micro-cracks or peeling due to high stress. The third organic encapsulation layer 43 also has good planarization properties, which can provide a relatively flat substrate for subsequent color film layer fabrication, preventing damage to the second inorganic encapsulation layer during the color film layer process.

[0121] In an example embodiment, the first inorganic encapsulation layer and the second inorganic encapsulation layer are formed by a deposition process, and the deposition density of the first inorganic encapsulation layer is less than that of the second inorganic encapsulation layer.

[0122] In an example embodiment, the color film layer uses white light combined with color film to achieve full-color display, and the white light combined with color film can achieve a high resolution of more than 2000, which can meet the needs of VR / AR.

[0123] In an example embodiment, the display substrate further comprises: a planar layer, a bonding layer and a cover plate. The planar layer is located on the side of the color film layer away from the substrate base plate; the bonding layer is located on the side of the planar layer away from the substrate base plate, and the cover plate is located on the side of the bonding layer away from the substrate base plate.

[0124] In an example embodiment, the material for manufacturing the planar layer can include: poly-p-xylylene; the material for manufacturing the bonding layer can include: silicon dioxide, and the bonding layer manufactured by inorganic material can better adhere to the cover plate. The cover plate can be a glass cover plate.

[0125] In an example embodiment, the display substrate further comprises: a sealant. The cover plate is fixed with the substrate base plate by the sealant. The sealant is arranged between the substrate base plate and the cover plate, which can provide protection against water and oxygen invasion, so that the service life of the silicon-based OLED display substrate is greatly improved. In another example embodiment, the sealant can be arranged on the side surface of the cover plate, and the four side surfaces of the cover plate and the substrate base plate are sealed by the sealant. The end surface of the sealant away from the substrate base plate is located between the surface of the cover plate adjacent to the substrate base plate and the surface of the cover plate away from the substrate base plate. Thus, the sealing effect can be ensured, and the thickness of the display substrate caused by the sealant protruding from the cover plate can be prevented.

[0126] In an example embodiment, as shown in Figure 1 and 2 , the first electrode 30 can include: a first structure 31 and a second structure 32, wherein the first structure 31 is located on the side of the second structure 32 away from the substrate base plate 10. The arrangement of the first structure 31 can improve the conductivity of the first electrode, and the second structure 32 includes a metal material, which can reflect light and increase the utilization rate of light, thereby improving the light emitting performance of the display substrate.

[0127] In an example embodiment, as shown in Figure 1 and 2 , the orthogonal projection of the surface of the second structure 32 away from the substrate base plate 10 on the substrate base plate 10 covers the orthogonal projection of the first structure 31 on the substrate base plate 10, that is, the cross-sectional area of the second structure 32 is greater than that of the first structure 31.

[0128] In an example embodiment, as shown in Figure 1 and 2 , in the direction perpendicular to the substrate base plate 10, the thickness of the second structure 32 can be greater than the thickness of the first structure 31.

[0129] In an example embodiment, as shown in Figure 2 and 2 , the side wall of the second structure 32 is stepped, and the side wall of the first structure 31 is sloped.

[0130] In an exemplary embodiment, as shown in Figure 1 and 2 the included angle between the sidewall of the first structure 31 and the substrate 10 is an acute angle, which may, for example, be greater than or equal to 50 degrees and less than 90 degrees.

[0131] In an exemplary embodiment, the first structure 31 can include a transparent conductive material such as indium tin oxide or zinc tin oxide.

[0132] In an exemplary embodiment, as shown in Figure 1 and 2 the shape of the longitudinal section of the first structure 31 can be rectangular or trapezoidal. Figure 1 and Figure 1 are described taking the shape of the longitudinal section of the first structure 31 as trapezoidal as an example.

[0133] In an exemplary embodiment, as shown in Figure 1 and 2 the second structure 32 can include a plurality of sub-layer structures, for example, three sub-layer structures: a first sub-layer 321, a second sub-layer 322, and a third sub-layer 323, which are sequentially stacked on the substrate 10.

[0134] In an exemplary embodiment, as shown in Figure 1 and 2 the thickness of the second sub-layer 322 can be greater than the thickness of the first sub-layer 321 and greater than the thickness of the third sub-layer 323.

[0135] In an exemplary embodiment, as shown in Figure 1 and 2 the orthogonal projection of the surface of the first sub-layer 321 away from the substrate 10 on the substrate 10 covers the orthogonal projection of the second sub-layer 322 on the substrate 10, the orthogonal projection of the surface of the second sub-layer 322 close to the substrate 10 on the substrate 10 covers the orthogonal projection of the surface of the second sub-layer 322 away from the substrate 10 on the substrate 10, and the surface of the second sub-layer 322 away from the substrate 10 covers the orthogonal projection of the third sub-layer 323 on the substrate 10, i.e., the cross-sectional area of the first sub-layer 321 is greater than the cross-sectional area of the second sub-layer 322, and the cross-sectional area of the second sub-layer 322 is greater than the cross-sectional area of the third sub-layer 323.

[0136] In an exemplary embodiment, as shown in Figure 1 and 2 the shape of the longitudinal section of the first sub-layer 321 and the third sub-layer 323 can be rectangular or trapezoidal.

[0137] In an exemplary embodiment, as shown in Figure 1 and 2As shown, the side wall of the first sub-layer 321 and the side wall of the third sub-layer 323 are ramp-shaped, and the included angle between the side wall of the first sub-layer 321 and the side wall of the third sub-layer 323 and the substrate 10 is an acute angle, which can be greater than or equal to 50 degrees and less than 90 degrees, for example.

[0138] In an example embodiment, as shown in Figure 1 and 2 The included angle between the side wall of the first sub-layer 321 and the substrate 10 can be greater than or equal to the included angle between the side wall of the third sub-layer 323 and the substrate 10.

[0139] In an example embodiment, the first sub-layer 321 can include titanium, the second sub-layer 322 can include aluminum, and the third sub-layer 323 can include titanium.

[0140] In an example embodiment, as shown in Figure 1 and 2 The side wall of the second sub-layer 322 is step-shaped, and the side wall of the second sub-layer 322 includes a first inclined surface S1, a step surface T, and a second inclined surface S2. The step surface T is parallel to the substrate 10, the first inclined surface S1 is located on the side of the step surface T away from the substrate 10, the second inclined surface S2 is located on the side of the step surface T close to the substrate 10, and the step surface T connects the first inclined surface S1 and the second inclined surface S2.

[0141] In an example embodiment, as shown in Figure 1 and 2 The pixel definition layer 20 can include a first inorganic layer 21 and a second inorganic layer 22 stacked on the substrate 10, and the first inorganic layer 21 can be located on the side of the second inorganic layer 22 close to the substrate 10. The orthographic projection of the second inorganic layer 22 on the substrate 10 covers the orthographic projection of the first inorganic layer 21 on the substrate 10.

[0142] In an example embodiment, as shown in Figure 1 and 2 The first inorganic layer 21 can include a first via V1, the second inorganic layer 22 can include a second via V2, and the opening D1 includes the first via V1 and the second via V2.

[0143] In an example embodiment, as shown in Figure 2 and 2As shown, the sidewalls of the first via V1 and the second via V2 are perpendicular to the substrate 10, and the orthographic projection of the first via V1 on the substrate 10 covers the orthographic projection of the second via V2 on the substrate 10. The orthographic projection of the first via V1 on the substrate 10 covering the orthographic projection of the second via V2 on the substrate 10 in the present disclosure can include that the cross-sectional area of the first via V1 is greater than the cross-sectional area of the second via V2, at this time, the sidewall of the via combination of the first via V1 and the second via V2 is an undercut structure, which can make the light-emitting structure layer break and unable to transmit the lateral leakage current, thereby improving the reliability of the display substrate, or can also include that the cross-sectional area of the first via V1 is equal to the cross-sectional area of the second via V2, and the via combination of the first via V1 and the second via V2 is a through hole with a flat sidewall.

[0144] In an example embodiment, as shown in Figure 1 and 2 , the orthographic projection of the first inorganic layer 21 on the substrate 10 at least partially overlaps with the orthographic projection of the step surface T of the second sub-layer 322 on the substrate 10, and does not overlap with the orthographic projection of the first inclined surface S1 of the second sub-layer 322 on the substrate 10, that is, the first inorganic layer 21 only partially covers the second sub-layer.

[0145] In an example embodiment, as shown in Figure 1 and 2 , the center lines of the first via V1 and the second via V2 coincide and are perpendicular to the substrate 10. The center line C2 of the first via V1 coincides with the center line C1 of the first electrode 30, or can not coincide. Figure 2 and Figure 1 is described taking the case that the center line C2 of the first via V1 coincides with the center line C1 of the first electrode 30 as an example.

[0146] In an example embodiment, as shown in Figure 1 and 2 , the distance between the sidewall of the first inorganic layer 21 close to the first electrode 30 and the center line C1 of the first electrode 30 is greater than or equal to the distance between the sidewall of the second inorganic layer 22 close to the first electrode 30 and the center line C1 of the first electrode 30. Figure 2 is described taking the case that the distance between the sidewall of the first inorganic layer 21 close to the first electrode 30 and the center line C1 of the first electrode 30 is greater than the distance between the sidewall of the second inorganic layer 22 close to the first electrode 30 and the center line C1 of the first electrode 30 as an example, Figure 1 is described taking the case that the distance between the sidewall of the first inorganic layer 21 close to the first electrode 30 and the center line C1 of the first electrode 30 is equal to the distance between the sidewall of the second inorganic layer 22 close to the first electrode 30 and the center line C1 of the first electrode 30 as an example.

[0147] In an example embodiment, as shown in Figure 2 When the distance between the first inorganic layer 21 close to the sidewall of the first electrode 30 and the center line C1 of the first electrode 30 is greater than the distance between the second inorganic layer 22 close to the sidewall of the first electrode 30 and the center line C1 of the first electrode 30, the second inorganic layer 22 further overlaps with the first inclined surface S1 of the second sub-layer 322 on the substrate 10, and does not overlap with the first sub-layer 321 on the substrate 10.

[0148] In an example embodiment, as shown in Figure 1 and Figure 2 The pixel definition layer 20 can further include a third inorganic layer 23 and a fourth inorganic layer 24. The third inorganic layer 23 can be located on the side of the first inorganic layer 21 close to the substrate 10, and the fourth inorganic layer 24 can be located on the side of the third inorganic layer 23 close to the substrate 10.

[0149] In an example embodiment, the fourth inorganic layer 24 covers the sidewall of the first electrode 30.

[0150] In an example embodiment, as shown in Figure 1 and Figure 2 The third inorganic layer 23 overlaps with the first structure 31 on the substrate 10.

[0151] In an example embodiment, as shown in Figure 1 and Figure 2 The fourth inorganic layer 24 at least partially overlaps with the first sub-layer 321 of the second structure 32 on the substrate 10.

[0152] In an example embodiment, as shown in Figure 1 and Figure 2 The third inorganic layer 23 and the fourth inorganic layer 24 do not overlap with the surface of the first electrode 30 away from the substrate 10 on the substrate 10.

[0153] In an example embodiment, as shown in Figure 1 and Figure 2 The third inorganic layer 23 and the fourth inorganic layer 24 completely cover the sidewall of the first electrode 30.

[0154] In an example embodiment, as shown in Figure 1 and Figure 2 The third inorganic layer 23 is provided with a third via V3, and the fourth inorganic layer 24 is provided with a fourth via V4. The opening D1 can include the first via V1, the second via V2, the third via V3, and the fourth via V4.

[0155] In an example embodiment, as shown in Figure 1 and Figure 2 the second via V2 covers the orthographic projection of the third via V3 on the substrate 10 and covers the orthographic projection of the fourth via V4 on the substrate 10.

[0156] In an example embodiment, as shown in Figure 1 and Figure 2 The pixel definition layer 20 further comprises a first recess D2, and a sidewall of the first recess D2 is in an undercut structure. The disclosure can make the organic light-emitting layer break at the first recess by setting the first recess in the undercut structure, thereby avoiding the transmission of the lateral leakage current.

[0157] In an example embodiment, as shown in Figure 1 and Figure 2 The orthographic projection of the first recess D2 on the substrate 10 does not overlap the orthographic projection of the first electrode 30 on the substrate 10.

[0158] In an example embodiment, the cross section of the first recess can be any shape such as a square, a circle, or an ellipse, and the disclosure does not make any limitation in this regard.

[0159] In an example embodiment, the first inorganic layer on the flat portion is flat away from the surface of the substrate. The second inorganic layer on the flat portion is also flat away from the surface of the substrate, that is, the height of the undercut structure adjacent to different first electrodes is the same, which can ensure the display effect of the display substrate and improve the reliability of the display substrate.

[0160] In an example embodiment, as shown in Figure 1 and Figure 2 The third inorganic layer 23 comprises a bending portion 231 and a flat portion 232, the bending portion 231 covers the sidewall of the first electrode 30 and is in a stepped shape, and the flat portion 232 is parallel to the substrate 10.

[0161] In an example embodiment, as shown in Figure 1 and Figure 2 The first inorganic layer 21 further comprises a fifth via V5, and the second inorganic layer 22 further comprises a sixth via V6, the fifth via V5 exposes the third inorganic layer 23, and the first recess D2 comprises the fifth via V5 and the sixth via V6.

[0162] In an example embodiment, as shown in Figure 1 and Figure 2 The center line of the fifth via V5 and the center line of the sixth via V6 coincide and are perpendicular to the substrate 10.

[0163] In an example embodiment, as shown in Figure 1 andFigure 2 As shown in FIG. 6, the distance between the side wall of the fifth via V5 away from the center line of the fifth via V5 and the center line C3 of the fifth via V5 is greater than the distance between the side wall of the fifth via V5 and the center line C3 of the fifth via V5.

[0164] In an example embodiment, Figure 1 A structure diagram of a display substrate provided for an example embodiment Figure 2 , Figure 1 A structure diagram of a display substrate provided for an example embodiment Figure 2 . Figure 1 is described by taking an example that the cross-sectional area of the first via is greater than the cross-sectional area of the second via, Figure 2 is described by taking an example that the cross-sectional area of the first via is equal to the cross-sectional area of the second via. As Figure 1 and Figure 2 As shown in FIG. 6, the display substrate can further include a filling structure 40 disposed in the first recess D2, and the side wall of the filling structure 40 includes a plurality of second recesses D3.

[0165] In an example embodiment, as Figure 1 and Figure 2 As shown in FIG. 6, the distance between the side wall of the fifth via V5 away from the center line of the fifth via V5 and the center line C3 of the fifth via V5 is greater than the distance between the side wall of the fifth via V5 and the center line C3 of the fifth via V5.

[0166] In an example embodiment, as Figure 6 and Figure 1 As shown in FIG. 6, the filling structure 40 can include a plurality of first filling layers 41 and a plurality of second filling layers 42 stacked, one of the plurality of first filling layers 41 is in contact with the third inorganic layer 23, and the plurality of first filling layers 41 and the plurality of second filling layers 42 are arranged in an overlapping manner.

[0167] In an example embodiment, as Figure 7 and Figure 2 As shown in FIG. 6, the number of the first filling layers 41 and the second filling layers 42 is equal. Figure 6 and Figure 7 is described by taking an example that the number of the first filling layers 41 and the second filling layers 42 is 3. The present disclosure does not make any limitation in this regard.

[0168] In an example embodiment, as Figure 6 and Figure 7As shown, the distance between the sidewall of the first filling layer 41 and the center line C3 of the fifth via V5 is less than the distance between the sidewall of the second filling layer 42 and the center line C3 of the fifth via V5, i.e., the sidewall of the second groove D3 is in an undercut structure. The disclosure can make the organic light-emitting layer break at the first groove by setting the filling structure including the undercut structure, thereby avoiding the transmission of the lateral leakage current.

[0169] In an example embodiment, the material for manufacturing the first filling layer 41 can be the same as the material for manufacturing the first inorganic layer.

[0170] In an example embodiment, the material for manufacturing the second filling layer 42 can be the same as the material for manufacturing the second inorganic layer.

[0171] In an example embodiment, as shown in Figure 6 , Figure 7 , Figure 6 and Figure 7 , the thickness of the first inorganic layer 21 can be greater than the thickness of any one of the second inorganic layer 22, the third inorganic layer 23 and the fourth inorganic layer 24; the thickness of the second inorganic layer 22 and the third inorganic layer 23 can be greater than the thickness of the fourth inorganic layer 24.

[0172] In an example embodiment, the first inorganic layer 21 can include silicon nitride.

[0173] In an example embodiment, the second inorganic layer 22 and the fourth inorganic layer 24 can include silicon oxide.

[0174] In an example embodiment, the third inorganic layer 23 includes aluminum oxide.

[0175] In an example embodiment, as shown in Figure 6 and Figure 7 , the thickness of the first filling layer 41 can be greater than or equal to the thickness of the second filling layer 42.

[0176] In an example embodiment, the first filling layer 41 can include silicon nitride.

[0177] In an example embodiment, the second filling layer 42 can include silicon oxide.

[0178] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, removing photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate prepared by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0179] In the exemplary embodiments, the display substrate is provided as an example, and the preparation process of the display substrate can include the following operations. Figure 6 In the exemplary embodiments, the display substrate is provided as an example, and the preparation process of the display substrate can include the following operations.

[0180] (1) Forming the substrate 10. In the exemplary embodiments, forming the substrate 10 can include: providing a substrate 11, depositing a first insulating thin film on the substrate, patterning the first insulating thin film by a patterning process to form a first insulating layer 16, depositing a metal conductive thin film on the basis of the pattern formed, patterning the first conductive thin film by a patterning process to form a first conductive column 13, depositing a reflective thin film on the basis of the pattern formed, patterning the reflective thin film by a patterning process to form a connecting electrode 14, depositing a second insulating thin film on the basis of the pattern formed, patterning the second insulating thin film by a patterning process to form a second insulating layer 17, depositing a second conductive thin film on the basis of the pattern formed, patterning the second conductive thin film by a patterning process to form a second conductive column 15, as shown in FIG. 1. Figure 7 Figure 1 A schematic view after forming the substrate.

[0181] In the exemplary embodiments, the substrate 11 can include a transistor 12.

[0182] ​In the example embodiment, the first insulating layer 16 is provided with a via hole exposing the first or second electrode of the transistor. The first conductive pillar 13 is disposed in the via hole of the first insulating layer 16.

[0183] In the example embodiment, the second insulating layer 17 is provided with a via hole exposing the connection electrode 14. The second conductive pillar 15 is disposed in the via hole of the second insulating layer 17.

[0184] (2) Forming a first original electrode. In the example embodiment, forming the first original electrode includes: sequentially depositing a first sub-film, a second sub-film, a third sub-film, and a first structure film on the basis of forming the aforementioned pattern, patterning the first sub-film, the second sub-film, the third sub-film, and the first structure film by a patterning process, and forming the first original electrode 50. Figure 2 A schematic view after forming the first original electrode.

[0185] In the example embodiment, the sidewall of the first original electrode 50 is slope-shaped.

[0186] (3) Forming a first electrode. In the example embodiment, forming the first electrode includes: patterning the first original electrode by a patterning process, and forming the first electrode 30. Figure 6 A schematic view after forming the first electrode.

[0187] In the example embodiment, as shown in FIG. 3B, the first electrode 30 includes: a first structure 31 and a second structure 32 stacked together. The second structure 32 includes: a first sub-layer 321, a second sub-layer 322, and a third sub-layer 323. Figure 7 In the example embodiment, as shown in FIG. 3B, the sidewall of the first structure 31, the first sub-layer 321, and the third sub-layer 323 is slope-shaped. The sidewall of the second sub-layer 322 is step-shaped.

[0188] Figure 6 (4) Forming a third inorganic layer. In the example embodiment, forming the third inorganic layer includes: sequentially depositing a fourth inorganic film and a third inorganic film on the basis of forming the aforementioned pattern, patterning the fourth inorganic film and the third inorganic film by a patterning process, and forming a fourth inorganic layer 24 and the third inorganic layer 23. A schematic view after forming the third inorganic layer.

[0189] Figure 7 In the example embodiment, as shown in FIG. 4B, the third inorganic layer 23 is provided with a third via hole V3 exposing the first electrode 30. The third via hole V3 exposes the upper surface of the first electrode 30 away from the substrate 10.

[0190] In the example embodiment, as shown in FIG. 4B, the third inorganic layer 23 is provided with a third via hole V3 exposing the first electrode 30. The third via hole V3 exposes the upper surface of the first electrode 30 away from the substrate 10. Figure 1 In the example embodiment, as shown in FIG. 4B, the third inorganic layer 23 is provided with a third via hole V3 exposing the first electrode 30. The third via hole V3 exposes the upper surface of the first electrode 30 away from the substrate 10.

[0191] Figure 8 ​​As shown, the fourth inorganic layer 24 is provided with a fourth via V4 exposing the first electrode 30. The fourth via V4 exposes the upper surface of the first electrode 30 away from the substrate 10.

[0192] (5) Forming the second inorganic layer. In an exemplary embodiment, forming the second inorganic layer comprises: sequentially depositing a first inorganic thin film and a second inorganic thin film on the basis of forming the aforementioned pattern, patterning the first inorganic thin film and the second inorganic thin film by a patterning process, forming the first inorganic layer 21 and the second inorganic layer 22. Figure 8 For Figure 9 The display substrate provided forms a schematic diagram after forming the second inorganic layer.

[0193] In an exemplary embodiment, as Figure 10 shown, the first inorganic layer 21 is provided with a first via V1 and a fifth via V5. The first via V1 exposes the upper surface of the first electrode 30 away from the substrate 10, and the fifth via V5 exposes the third inorganic layer.

[0194] In an exemplary embodiment, as Figure 10 shown, the second inorganic layer 22 is provided with a second via V2 and a sixth via V6. The second via V2 exposes the first via V1, and the sixth via V6 exposes the fifth via V5.

[0195] After forming the second inorganic layer, the method for preparing the display substrate can further comprise: on the basis of forming the aforementioned pattern, coating an organic light-emitting thin film, patterning the organic light-emitting thin film by a patterning process, forming an organic light-emitting layer, on the basis of forming the aforementioned pattern, depositing a cathode thin film, patterning the cathode thin film by a patterning process, and forming a second electrode.

[0196] The subsequent process can comprise: sequentially forming an encapsulation layer, a color film layer, a planarization layer, and a cover plate on the second electrode.

[0197] Figure 10 The display substrate provided is the same as Figure 11 The display substrate provided is the same as the steps before forming the third inorganic layer and the steps after forming the second inorganic layer, and the difference is that the steps after the third inorganic layer, Figure 11 The steps before forming the third inorganic layer of the display substrate provided are not repeated. After forming the third inorganic layer, the method for preparing the display substrate can comprise:

[0198] (6) Forming a filling structure. In an exemplary embodiment, forming the filling structure comprises: depositing a plurality of first filling thin films and a plurality of second filling thin films on the basis of forming the aforementioned pattern, patterning the plurality of first filling thin films and the plurality of second filling thin films by a patterning process, and forming a filling structure 40 comprising a plurality of first filling layers 41 and a plurality of second filling layers 42.Figure 11 A schematic view after forming the filling structure.

[0199] (7) Forming a protective layer. In an example embodiment, forming the protective layer comprises: coating a protective film on the basis of forming the aforementioned pattern, processing the protective film through a patterning process, and forming the protective layer 60 surrounding the filling structure. Figure 12 A schematic view after forming the protective layer.

[0200] In an example embodiment, the protective film comprises a photoresist.

[0201] (8) Forming a second inorganic layer. In an example embodiment, forming the second inorganic layer comprises: sequentially depositing a first inorganic film and a second inorganic film on the basis of forming the aforementioned pattern, patterning the first inorganic film and the second inorganic film through a patterning process, forming the first inorganic layer 21 and the second inorganic layer 22, and removing the protective layer to form the pixel definition layer 20. Figure 1 A schematic view after forming the second inorganic layer. Figure 12 Figure 12 Figure 6 Figure 1 Figure 6 Figure 13 Figure 14 Figure 15 Figure 6 A schematic view after forming the second inorganic layer of the display substrate provided.

[0202] In an example embodiment, the protective layer can be removed in a developing process in the patterning process.

[0203] The disclosure also provides a preparation method of a display substrate, configured to prepare a display substrate, the method comprising:

[0204] Step 100, forming a first electrode on a substrate substrate.

[0205] In an example embodiment, the sidewall of the first electrode is stepped.

[0206] Step 200, forming a pixel definition layer on the first electrode.

[0207] In an example embodiment, the pixel definition layer comprises: an opening exposing the first electrode; the pixel definition layer covers at least part of the sidewall of the first electrode, and the orthographic projection of the surface of the first electrode away from the substrate substrate on the substrate substrate is located within the orthographic projection of the opening on the substrate substrate.

[0208] The display substrate is the display substrate provided by any one of the aforementioned embodiments, and has similar principles and effects of implementation, which will not be described here.

[0209] In an example embodiment, step 100 can comprise:

[0210] sequentially depositing a first sub-film, a second sub-film, a third sub-film and a first structure film on the substrate substrate, and patterning the first sub-film, the second sub-film, the third sub-film and the first structure film through a patterning process to form a first original electrode with a slope-shaped sidewall.

[0211] The first electrode is patterned by a patterning process to form a first electrode.

[0212] In an example embodiment, the step 200 can include:

[0213] The fourth inorganic thin film and the third inorganic thin film are deposited on the first electrode in sequence, and the fourth inorganic thin film and the third inorganic thin film are patterned by a patterning process to form a fourth inorganic layer and a third inorganic layer of the pixel definition layer; the first inorganic thin film and the second inorganic thin film are deposited on the third inorganic layer in sequence, and the first inorganic thin film and the second inorganic thin film are patterned by a patterning process to form a first inorganic layer and a second inorganic layer of the pixel definition layer.

[0214] In an example embodiment, the step 200 can include:

[0215] The fourth inorganic thin film and the third inorganic thin film are deposited on the first electrode in sequence, and the fourth inorganic thin film and the third inorganic thin film are patterned by a patterning process to form a fourth inorganic layer and a third inorganic layer of the pixel definition layer; a plurality of first filling thin films and a plurality of second filling thin films are deposited on the third inorganic layer in sequence, and the plurality of first filling thin films and the plurality of second filling thin films are patterned by a patterning process to form a filling structure including a plurality of first filling layers and a plurality of second filling layers; a protective thin film is coated on the third inorganic layer, and the protective thin film is processed by a patterning process to form a protective layer surrounding the filling structure, the protective thin film including a photoresist; a first inorganic thin film and a second inorganic thin film are coated on the third inorganic layer, and the first inorganic thin film and the second inorganic thin film are patterned by a patterning process to form a first inorganic layer and a second inorganic layer of the pixel definition layer, and the protective layer is removed.

[0216] The display device provided by the embodiment of the present disclosure includes a display substrate.

[0217] The display substrate is the display substrate provided by any one of the preceding embodiments, and has similar principles and effects, which will not be described here.

[0218] In an example embodiment, the display device includes a VR device or an AR device.

[0219] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0220] For the sake of clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0221] Although the embodiments of the present disclosure are disclosed as above, the above-described content is merely an embodiment adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art to which the present disclosure belongs can make any modification and change in the form and details thereof without departing from the spirit and scope of the present disclosure, and the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized by, The application relates to a substrate, a pixel definition layer and a first electrode arranged on the substrate, wherein the pixel definition layer comprises an opening, the sidewall of the first electrode is in a stepped shape, and the opening exposes the first electrode. The pixel definition layer covers at least part of the sidewall of the first electrode, and the orthographic projection of the surface of the first electrode away from the substrate on the substrate is within the orthographic projection of the opening on the substrate. The first electrode comprises a first structure and a second structure, and the first structure is arranged on the side of the second structure away from the substrate. The orthographic projection of the surface of the second structure away from the substrate on the substrate covers the orthographic projection of the first structure on the substrate, and the thickness of the second structure is greater than the thickness of the first structure. The sidewall of the second structure is in a stepped shape. The second structure comprises a first sub-layer, a second sub-layer and a third sub-layer arranged on the substrate in sequence, the thickness of the second sub-layer is greater than the thickness of the first sub-layer and the thickness of the third sub-layer.

2. The display substrate of claim 1, wherein, The orthographic projection of the surface of the first sub-layer away from the substrate on the substrate covers the orthographic projection of the second sub-layer on the substrate, the orthographic projection of the surface of the second sub-layer close to the substrate on the substrate covers the orthographic projection of the surface of the second sub-layer away from the substrate on the substrate, and the surface of the second sub-layer away from the substrate covers the orthographic projection of the third sub-layer on the substrate. The sidewall of the second sub-layer is in a stepped shape. The sidewall of the second sub-layer comprises a first inclined surface, a stepped surface and a second inclined surface. The stepped surface is parallel to the substrate, the first inclined surface is arranged on the side of the stepped surface away from the substrate, the second inclined surface is arranged on the side of the stepped surface close to the substrate, and the stepped surface connects the first inclined surface and the second inclined surface. The pixel definition layer comprises a first inorganic layer and a second inorganic layer arranged on the substrate in sequence, the first inorganic layer is arranged on the side of the second inorganic layer close to the substrate, and the orthographic projection of the second inorganic layer on the substrate covers the orthographic projection of the first inorganic layer on the substrate. 3.The display substrate of claim 2, wherein, The first inorganic layer comprises a first via, the second inorganic layer comprises a second via, and the opening comprises the first via and the second via, wherein the orthographic projection of the first via on the substrate covers the orthographic projection of the second via on the substrate. The orthographic projection of the first inorganic layer on the substrate at least partially overlaps the orthographic projection of the stepped surface of the second sub-layer on the substrate, and does not overlap the orthographic projection of the first inclined surface of the second sub-layer on the substrate.

4. The display substrate of claim 3, wherein, The center lines of the first via and the second via coincide and are perpendicular to the substrate.

5. The display substrate of claim 4, wherein, ​ The distance between the first inorganic layer close to the sidewall of the first electrode and the center line of the first electrode is greater than or equal to the distance between the second inorganic layer close to the sidewall of the first electrode and the center line of the first electrode. 6.The display substrate of claim 5, wherein, When the distance between the first inorganic layer close to the sidewall of the first electrode and the center line of the first electrode is greater than the distance between the second inorganic layer close to the sidewall of the first electrode and the center line of the first electrode, the orthographic projection of the second inorganic layer on the substrate further overlaps with the orthographic projection of the first inclined surface of the second sub-layer on the substrate, and does not overlap with the orthographic projection of the first sub-layer on the substrate.

7. The display substrate according to any one of claims 3 to 6, characterized in that, The pixel definition layer further comprises a third inorganic layer and a fourth inorganic layer, the third inorganic layer is located on the side of the first inorganic layer close to the substrate, and the fourth inorganic layer is located on the side of the third inorganic layer close to the substrate. The orthographic projection of the third inorganic layer on the substrate partially overlaps with the orthographic projection of the first structure on the substrate; the orthographic projection of the fourth inorganic layer on the substrate at least partially overlaps with the orthographic projection of the first sub-layer of the second structure on the substrate; the orthographic projection of the third inorganic layer and the fourth inorganic layer on the substrate does not overlap with the orthographic projection of the surface of the first electrode away from the substrate on the substrate; The third inorganic layer is provided with a third via hole, and the fourth inorganic layer is provided with a fourth via hole; the opening comprises: the first via hole, the second via hole, the third via hole and the fourth via hole; The orthographic projection of the second via hole on the substrate covers the orthographic projection of the third via hole on the substrate, and covers the orthographic projection of the fourth via hole on the substrate. 8.The display substrate of claim 7, wherein, The pixel definition layer further comprises a first recess, and the sidewall of the first recess is in an undercut structure. The orthographic projection of the first recess on the substrate does not overlap with the orthographic projection of the first electrode on the substrate. 9.The display substrate of claim 8, wherein, The third inorganic layer comprises a bending part and a flat part; the bending part covers the sidewall of the first electrode and is in a stepped shape, and the flat part is parallel to the substrate; The first inorganic layer further comprises a fifth via hole, and the second inorganic layer further comprises a sixth via hole; the fifth via hole exposes the third inorganic layer; the first recess comprises the fifth via hole and the sixth via hole; the center line of the fifth via hole and the center line of the sixth via hole coincide and are perpendicular to the substrate; The distance between the sidewall of the flat part away from the center line of the fifth via hole and the center line of the fifth via hole is greater than the distance between the sidewall of the fifth via hole and the center line of the fifth via hole; The surface of the first inorganic layer on the flat part away from the substrate is flat, and the surface of the second inorganic layer on the flat part away from the substrate is flat. 10.The display substrate of claim 9, wherein, Further comprising: A filling structure arranged in the first recess, and the sidewall of the filling structure comprises a plurality of second recesses; The distance between the filling structure and the surface of the substrate away from the substrate is less than the minimum distance between the second inorganic layer and the surface of the substrate. 11.The display substrate of claim 10, wherein, The filling structure comprises a plurality of first filling layers and a plurality of second filling layers stacked, one of the plurality of first filling layers is in contact with the third inorganic layer, and the plurality of first filling layers and the plurality of second filling layers are arranged in an overlapping manner. The distance between the sidewall of the first filling layer and the center line of the fifth via is less than the distance between the sidewall of the second filling layer and the center line of the fifth via. 12.The display substrate of claim 11, wherein, The thickness of the first inorganic layer is greater than the thickness of any one of the second inorganic layer, the third inorganic layer and the fourth inorganic layer; the thickness of the second inorganic layer and the third inorganic layer is greater than the thickness of the fourth inorganic layer; The first inorganic layer comprises silicon nitride, the second inorganic layer and the fourth inorganic layer comprise silicon oxide, and the third inorganic layer comprises aluminum oxide. The thickness of the first filling layer is greater than or equal to the thickness of the second filling layer. The first filling layer comprises silicon nitride, and the second filling layer comprises silicon oxide.

13. A display device comprising: Comprise: The display substrate of any one of claims 1-12.

14. A method for preparing a display substrate, characterized in that, The method configured to prepare the display substrate of any one of claims 1-12, the method comprising: forming a first electrode on a substrate, the sidewall of the first electrode being stepped; forming a pixel definition layer on the first electrode, the pixel definition layer comprising: an opening exposing the first electrode; The pixel definition layer covers at least part of the sidewall of the first electrode, and the orthographic projection of the first electrode away from the surface of the substrate on the substrate is located within the orthographic projection of the opening on the substrate. The forming a first electrode on a substrate comprises: sequentially depositing a first sub-film, a second sub-film, a third sub-film and a first structure film on the substrate, and patterning the first sub-film, the second sub-film, the third sub-film and the first structure film by a patterning process to form a first original electrode with a slope-shaped sidewall; patterning the first original electrode by a patterning process to form the first electrode; The forming a pixel definition layer on the first electrode comprises: sequentially depositing a fourth inorganic film and a third inorganic film on the first electrode, and patterning the fourth inorganic film and the third inorganic film by a patterning process to form a fourth inorganic layer and a third inorganic layer of the pixel definition layer; sequentially depositing a first inorganic film and a second inorganic film on the third inorganic layer, and patterning the first inorganic film and the second inorganic film by a patterning process to form a first inorganic layer and a second inorganic layer of the pixel definition layer; Or, a fourth inorganic thin film and a third inorganic thin film are sequentially deposited on the first electrode, the fourth inorganic thin film and the third inorganic thin film are patterned by a patterning process to form a fourth inorganic layer and a third inorganic layer of the pixel definition layer; a plurality of first filling thin films and a plurality of second filling thin films are sequentially deposited on the third inorganic layer, the plurality of first filling thin films and the plurality of second filling thin films are patterned by a patterning process to form a filling structure including a plurality of first filling layers and a plurality of second filling layers; a protective thin film is coated on the third inorganic layer, the protective thin film is processed by a patterning process to form a protective layer surrounding the filling structure, the protective thin film including a photoresist; a first inorganic thin film and a second inorganic thin film are coated on the third inorganic layer, the first inorganic thin film and the second inorganic thin film are patterned by a patterning process to form a first inorganic layer and a second inorganic layer of the pixel definition layer, and the protective layer is removed; The first inorganic layer is located on a side of the second inorganic layer close to the substrate substrate, and the orthographic projection of the second inorganic layer on the substrate substrate covers the orthographic projection of the first inorganic layer on the substrate substrate, the third inorganic layer is located on a side of the first inorganic layer close to the substrate substrate, the fourth inorganic layer is located on a side of the third inorganic layer close to the substrate substrate, and the orthographic projection of the third inorganic layer and the fourth inorganic layer on the substrate substrate does not overlap with the surface of the first electrode away from the substrate substrate in the orthographic projection of the substrate substrate; One of the plurality of first filling layers is in contact with the third inorganic layer, and the plurality of first filling layers and the plurality of second filling layers are arranged in overlapping manner.

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