Probeless testing apparatus for IC chip testing and IC chip testing method

Abstract

The present application provides a kind of IC chip test's probeless test device and IC chip test method, the probeless test device includes including carrier plate, ceramic insert plate being arranged on carrier plate and several copper core balls.The ceramic insert plate has first surface, second surface and several connection points, the second surface of ceramic insert plate faces the carrier plate.Each connection point has several through holes through first and second surface, and the inner side wall surface of each through hole has metallization layer.The metallization layer extends to part of first surface and the second surface, and the extension area of metallization layer in each connection point to the second surface is less than the extension area of metallization layer to the first surface.The copper core ball is arranged between the through hole of each connection point of carrier plate and ceramic insert plate.

Description

TECHNICAL FIELD

[0001] The present invention relates to an IC chip testing technology, and more particularly, to a probeless testing device for IC chip testing and an IC chip testing method. BACKGROUND

[0002] IC chip testing is an important step in the IC manufacturing process to ensure the quality of the shipped chips. In particular, the testing of application specific integrated circuits (ASICs) is required because ASICs are special specification integrated circuits that are fully customized according to product requirements, and thus require custom testing devices.

[0003] Most of the currently available testing devices use testing devices with pogo pins. The ASIC chip is first soldered to a testing socket with pogo pins, and then the pogo pins of the testing socket are inserted into a test board to perform testing. Since the length of the pogo pins is about 4 mm, the distance between the test board and the ASIC chip under test is at least 4 mm, and the contact resistance of about 70 mOhm generated by the pogo pins therebetween causes an IR drop effect, which is one of the factors affecting whether the ASIC chip meets the requirements.

[0004] Therefore, when the industry encounters a bottleneck in the testing debugging phase, it tends to exclude the contact resistance effect. However, in practice, the design of the current testing device still cannot meet the foregoing requirements. SUMMARY

[0005] The present invention is directed to a probeless testing device for IC chip testing, which can further exclude the contact resistance effect in the testing process to obtain accurate testing results.

[0006] The present invention is further directed to an IC chip testing method, which is suitable for the testing of application specific integrated circuits (ASICs).

[0007] According to embodiments of the present application, a probeless test apparatus for IC chip testing includes a load board, a ceramic interposer disposed on the load board, and a Cu core ball. The ceramic interposer has a first surface, a second surface, and a plurality of contact points, each of which has a plurality of through holes penetrating the first and second surfaces, and the second surface of the ceramic interposer faces the load board. An inner sidewall surface of each of the through holes has a metallization layer, and the metallization layer extends to a portion of the first surface and the second surface, and the area of the second surface to which the metallization layer of each of the contact points extends is less than the area of the first surface to which the metallization layer of each of the contact points extends. The Cu core ball is disposed between the load board and the through hole of each of the contact points of the ceramic interposer.

[0008] In the apparatus according to embodiments of the present application, a plurality of contact components can be further included and disposed on the surface of the load board facing the ceramic interposer, wherein each of the contact components is in electrical contact with each of the Cu core balls.

[0009] In the apparatus according to embodiments of the present application, each of the contact components includes a main pad, a shadow pad, a wire, and a solder resist. The shadow pad is spaced apart from the main pad by a distance, and the size of the shadow pad is less than the size of the main pad. The wire connects the shadow pad to the main pad. The solder resist is formed on the surface of the wire.

[0010] In the apparatus according to embodiments of the present application, the shadow pad is in electrical contact with the Cu core ball.

[0011] In the apparatus according to embodiments of the present application, the test apparatus can further include a solder ball formed on the extended portion of the metallization layer of each of the contact points.

[0012] In the apparatus according to embodiments of the present application, the concentration of a surfactant contained in the solder forming the solder ball is inversely proportional to the size of each of the through holes.

[0013] In the apparatus according to embodiments of the present application, the number of the through holes in each of the contact points of the ceramic interposer is more than three.

[0014] In the apparatus according to embodiments of the present application, the ceramic interposer can further include a stiffener disposed on the periphery of the ceramic interposer, and the thickness of the stiffener is greater than the thickness of the portion of the ceramic interposer having the contact points.

[0015] According to an embodiment of the present application, an IC chip testing method using the above-mentioned device includes attaching an IC chip to a metallized layer of a plurality of connection points on a first surface of a ceramic interposer using a first solder paste, performing a first reflow, bonding the ceramic interposer to the IC chip, and partially infiltrating the first solder paste into a through-hole of the ceramic interposer. Then, a plurality of copper core balls are attached to a metallized layer of a plurality of connection points on a second surface of the ceramic interposer using a second solder paste, and a second reflow is performed to bond the ceramic interposer to the copper core balls. Thereafter, the copper core balls are bonded to a carrier.

[0016] In the method according to an embodiment of the present application, the temperature of the above-mentioned second reflow is lower than the temperature of the above-mentioned first reflow.

[0017] In the method according to an embodiment of the present application, the melting point of the above-mentioned first solder paste is higher than the melting point of the above-mentioned second solder paste.

[0018] In the method according to an embodiment of the present application, the method of bonding the above-mentioned copper core balls to a carrier includes attaching the copper core balls bonded to the ceramic interposer to the carrier using a third solder paste, and performing a third reflow.

[0019] Based on the above, the testing device of the present application abandons the existing testing socket device, and instead uses a ceramic interposer and copper core balls. The ceramic interposer has a through-hole, and the solder balls of the IC chip infiltrate into the through-hole and reduce the height thereof, thereby reducing the distance effect of the thickness of the ceramic interposer. Therefore, the IC chip (such as an ASIC) can be bonded to a testing carrier as a complete unit through the combination of the ceramic interposer / copper core balls, so as to eliminate the influence of the contact resistance and achieve the testing verification of "Directly-Mounted Like".

[0020] In order to make the above features and advantages of the present application more apparent, specific embodiments are described in detail below, and the accompanying drawings are referred to as follows. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a cross-sectional view of a probeless testing device for IC chip testing according to a first embodiment of the present application;

[0022] Figure 2 is Figure 1 is a top view of a carrier in the probeless testing device for IC chip testing of

[0023] Figure 3A is Figure 1 is a front view of a connection point of a ceramic interposer in

[0024] Figure 3B is Figure 3AA schematic diagram of the back of the connection point of the ceramic insert plate;

[0025] Figure 3C yes Figure 3A A schematic diagram of the cross-section of the connection point of the ceramic insert plate along line segment II;

[0026] Figure 4 yes Figure 1 A three-dimensional schematic diagram of the ceramic insertion plate in a probeless testing device for IC chip testing;

[0027] Figures 5A to 5E This is a flowchart illustrating an IC chip testing method according to a second embodiment of the present invention.

[0028] Explanation of reference numerals in the attached figures

[0029] 10: Probeless testing device

[0030] 100: Carrier board

[0031] 110: Ceramic Insert Plate

[0032] 112: First Surface

[0033] 114: Second Surface

[0034] 116: Connection point

[0035] 118: Through hole

[0036] 118a: Inner wall surface

[0037] 120: Copper Core Ball

[0038] 122: Welding ball

[0039] 130: IC chip

[0040] 200: Contact component

[0041] 202: Main bonding pad

[0042] 204: Shadow Pad

[0043] 206: Wiring

[0044] 300: Metallization layer

[0045] 300a, 300b: Extension parts

[0046] 400: Reinforcing parts

[0047] 500, 506: Solder

[0048] 502: Sealing pad

[0049] 504: Solder resist layer

[0050] p1, p2: pitch DETAILED DESCRIPTION

[0051] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. The purpose of the embodiments is to explain the present application and is not intended to limit the scope of the present application. Further, the drawings are merely schematic and are not drawn to scale. Wherever possible, the same reference numerals are used throughout the drawings and the description to refer to the same or like parts. In addition, the terms "comprise", "comprising", "include", "including", "have" and "having" as used herein are open-ended terms that are used to indicate the inclusion of something but not to exclude the inclusion of something else. Also, the terms "first", "second", "third", etc. as used herein are used to distinguish between different elements, regions, layers, sections, etc. and are not intended to denote a particular order or sequence. Thus, the use of such terms in the description is merely for distinguishing between similar elements and is not intended to convey a specific order or sequence.

[0052] Figure 1 Fig. 1 is a cross-sectional view of a probeless testing device for IC chip testing according to a first embodiment of the present application.

[0053] Referring to Fig. 1, a probeless testing device 10 for IC chip testing according to a first embodiment of the present application includes a load board 100, a ceramic interposer 110 disposed on the load board 100, and Cu core balls 120. Figure 1 The ceramic interposer 110 has a first surface 112, a second surface 114, and a plurality of connection points 116. Each connection point 116 has a plurality of through holes 118 extending through the first surface 112 and the second surface 114. The thickness of the ceramic interposer 110 can be less than 1 mm, such as less than 0.5 mm or less than 0.3 mm. Figure 1 Although only one through hole 118 is shown in each connection point 116 in Fig. 1, it should be understood that the figure is a cross-sectional view, and thus other through holes not shown in Fig. 1 can exist in different cross-sections. Figure 1A through hole 118 is shown. A copper core ball 120 is disposed between the through hole 118 of each connection point 116 of the ceramic interposer 110 and the carrier 100. In this embodiment, the inner sidewall 118a of each through hole 118 has a metallization layer (not shown) that extends to a portion of the first surface 112 and a portion of the second surface 114. The ceramic has a low warpage rate that is conducive to the function of the copper core ball 120 to provide a good electrical connection between the ceramic interposer 110 and the carrier 100. The copper core ball 120 generally refers to a ball having a core of copper and a surface coated with nickel and solder. Since the core copper material of the copper core ball 120 has a melting point of 1080°C, which is much higher than the reflow temperature, the core copper material does not melt during reflow. Thus, the IC chip 130 and the ceramic interposer 110 can be strongly supported during reflow to avoid the problem of solder collapse during reflow. The distance between the IC chip 130 and the carrier 100 can be reduced to less than 1 mm. Thus, compared to a probe test device, the effect of contact resistance can be greatly reduced.

[0054] In one embodiment, the test device 10 can further include a solder ball 122 formed on the extended portion of the metallization layer of each connection point 116, and the IC chip 130 to be tested is bonded to the ceramic interposer 110, where the solder ball 122 is positioned, for example, between the pads of the IC chip 130 and the connection points 116 of the ceramic interposer 110, to achieve the effect of electrically bonding the IC chip 130 and the ceramic interposer 110 via reflow. Since the solder forming the solder ball 122 penetrates the through hole 118 during reflow, the height of the solder ball 122 after reflow is reduced, the current path is shortened, and the distance effect of the thickness of the ceramic interposer 110 is reduced. That is, the IC chip 130 and the copper core ball 120 are more closely coupled together via the molten solder ball 122, which is conducive to reducing the resistance. The extent to which the solder ball 122 penetrates the through hole 118 can be to completely fill the through hole 118 or to penetrate a portion of the through hole 118.

[0055] Moreover, the concentration of the surfactant contained in the solder used to form the solder balls 122 can be adjusted to accommodate the weight of the IC chip 130 and the structure of the ceramic interposer 110. If the IC chips 130 are of the same weight, the concentration of the surfactant in the solder can be inversely proportional to the size of each via 118. Since the concentration of the surfactant in the solder changes the surface tension of the solder to the structure being soldered, i.e., the higher the concentration of the surfactant in the solder, the better the solderability of the solder; conversely, the lower the concentration of the surfactant in the solder, the worse the solderability of the solder. Thus, when the vias 118 are larger, the solder does not need to be as solderable, so the concentration of the surfactant in the solder can be slightly reduced to ensure that the liquid solder penetrates the vias 118 to fill them but does not run off the bottom; when the vias 118 are smaller, the concentration of the surfactant in the solder can be slightly increased so that the solder can spread and penetrate the vias 118 smoothly, e.g., the concentration of the surfactant in the solder can be increased from 1 wt% to 1.3 wt% or 1.5 wt% to reduce the surface tension. In summary, the present application can achieve the result of having the liquid solder flow into the vias 118 without running off the bottom by balancing the weight of the IC chip 130 and the surface tension of the solder.

[0056] Figure 2 is Figure 1 An upper view of a carrier board in a probeless test apparatus for testing IC chips.

[0057] Referring to Figure 2 The carrier board 100 can be provided with a plurality of contact components 200 on a surface facing the ceramic interposer, and each contact component 200 can be connected to each copper core ball Figure 1118) Electrical contact. In this embodiment, each contact assembly 200 may include a main pad 202, a shadow pad 204, a wire 206, and a solder resist layer (not shown). The shadow pad 204 is spaced apart from the main pad 202, and the size of the shadow pad 204 is smaller than the size of the main pad 202. The wire 206 connects the shadow pad 204 to the main pad 202, so the electrical connection between the shadow pad 204 and the main pad 202 is equivalent to a single pad. The solder resist layer is formed on the surface of the wire 206 to prevent solder from flowing back to the main pad 202 during reflow soldering. In one embodiment, the main pad 202 is, for example, 0.6 mm in size, the pitch p1 between the main pads 202 is, for example, 1.0 mm, the shadow pad 204 is, for example, 0.4 mm in size, and the pitch p2 between the shadow pads 204 is, for example, 1.0 mm; however, the invention is not limited thereto, and the dimensions of the aforementioned structure can be changed according to the design of the IC chip under test. The size of the main pad 202 is the same as or slightly smaller than the pad size on a conventional carrier board. Due to space constraints, the size of the shadow pad 204 is approximately 0.33 times the size of the main pad 202, or the size of each shadow pad 204 is approximately the same as that of a single copper core ball (…). Figure 1 The projected areas of the 118) are similar, so that the shadow pad 204 makes electrical contact with the copper core ball, but the copper core ball does not contact the shadow pad 204 and the main pad 202 in the other contact assembly 200, and there is no residual solder on the main pad 202 after the copper core ball is removed. Therefore, the carrier plate 100 in the probeless test device 10 of this embodiment can be used to match the shadow pad 204 and the main pad 202 in the other contact assembly 200. Figure 1 The invention relates to the testing of ceramic interposers and copper core balls. If the influence of contact resistance is not considered, it can also be used in existing test sockets with probes (not shown), and the size of the main pad 202 can be designed to allow the probes to make appropriate contact. However, the invention is not limited thereto; in another embodiment, the contact assembly of the probeless test device 10 for IC chip testing can omit the aforementioned main pad 202 and wiring 206, retaining only the shadow pad 204.

[0058] For a clearer understanding of the detailed structure of the connection point 116 of the ceramic insert plate 110, please also refer to... Figure 3A , Figure 3B and Figure 3C ,in Figure 3A It's a front view. Figure 3B It's a picture of the back. Figure 3C yes Figure 3A A cross-sectional schematic diagram of line segment II. In the first embodiment, each connection point 116 has several through holes 118 penetrating the first surface 112 and the second surface 114, and the number of through holes 118 in each connection point 116 can be increased or decreased as needed, such as... Figure 3AThe invention has 5 through holes 118, but it is not limited to this; the number of through holes 118 can be 3 or more. Figure 3C In the via 118, the inner wall surface 118a has a metallization layer 300, and the metallization layer 300 extends to a portion of the first surface 112 and a portion of the second surface 114. When the second surface 114 of the ceramic insert plate 110 faces the carrier plate ( Figure 1 If the area of ​​the metallization layer 300 extending to the second surface 114 in connection point 116 is smaller than the area of ​​its extension to the first surface 112 (100%), then the area of ​​the extension portion 300a of the metallization layer 300 in connection point 116 is smaller than the area of ​​its extension portion 300b extending to the first surface 112. On the one hand, Figure 1 Solder balls 122 (with a diameter of, for example, 0.5 mm) can be deposited on the extension 300b of the larger metallization layer 300; on the other hand, Figure 1 The copper core ball 120 (with a diameter of, for example, 0.2 mm) can be bonded to the extension 300a of the smaller metallization layer 300. The through-hole 118 can be a square hole or other shapes, in addition to the round hole shown in the figure.

[0059] Figure 4 yes Figure 1 A three-dimensional schematic diagram of the ceramic insert plate in a probeless testing device used for IC chip testing.

[0060] Please refer to Figure 4 The ceramic insert plate 110 can be made of ceramic with low warpage characteristics (compared to FR4 boards). Compared to boards of the same specifications, the flexural strength of an FR4 PCB board is approximately 441 MPa, while that of a ceramic PCB board is approximately 650 MPa. Furthermore, the ceramic insert plate 110 may include a stiffener 400 to further reduce warpage. The stiffener 400 is disposed around the periphery of the ceramic insert plate 110, and its thickness is greater than the thickness of the portion of the ceramic insert plate 110 with the connection point 116 (e.g., approximately 0.3 mm). If the stiffener 400 and the ceramic insert plate 110 are made of the same material, they can also be manufactured as a single unit.

[0061] Using a 70mm x 70mm, 0.32mm thick ceramic PCB as a control, the deformation of the center under a 100N force simulated by Inventor software is approximately 0.4975mm. Adding a one-piece reinforcing member (100mm x 100mm, 10mm thick) to the perimeter of the aforementioned ceramic PCB, the deformation obtained in the same simulation is approximately 0.06877mm. Therefore, adding a 30mm wide and 10mm thick reinforcing member to the perimeter of the original ceramic PCB can reduce the deformation by approximately 86.2%.

[0062] Figures 5A to 5EThis is a flowchart illustrating an IC chip testing method according to a second embodiment of the present invention, wherein the same element symbols as in the first embodiment are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the first embodiment, and will not be repeated here.

[0063] Please refer to Figure 5A First, solder 500 containing a first solder paste is used, and the concentration of surfactant contained in solder 500 can be adjusted as needed. Solder 500 is then laid on the metallization layer (extension 300b) of the connection point 116 on the first surface 112 of the ceramic insert plate 110.

[0064] Then, please refer to Figure 5B The IC chip 130 is connected by solder ( Figure 5A The first solder paste (500) is attached to the extension portion 300b and a first reflow is performed to bond the ceramic insert plate 110 to the IC chip 130. Part of the first solder paste penetrates into the through-hole 118 of the ceramic insert plate 110, reducing the height of the solder ball 122 after reflow, thus shortening the current path and reducing the distance effect of the ceramic insert plate 110 thickness. A pad 502 and a solder resist layer 504 are typically provided between the IC chip 130 and the solder ball 122.

[0065] Next, please refer to Figure 5C Using solder 506 containing a second solder paste, and flipping the ceramic insert plate 110, the solder 506 is laid on the metallization layer (extension 300a) of the connection point 116 on the second surface 112 of the ceramic insert plate 110.

[0066] Then, please refer to Figure 5D Several copper core balls are placed on the solder 506 of the extension portion 300a and a second soldering is performed to join the ceramic insert plate 110 with the copper core balls 120. During the second soldering, the outer layer of solder (including solder paste) of the copper core balls 120 melts, at which point the solder balls 122 can pass through the through-hole 118 and mate with the outer layer of solder of the copper core balls 120, as if they were interfaceless balls binding. In one embodiment, the temperature of the second soldering is lower than that of the first soldering. In another embodiment, the melting point of the first solder paste is higher than that of the second solder paste.

[0067] Next, please refer to Figure 5EThe copper core ball 120 is joined to the carrier plate 100, for example, the copper core ball 120 joined in the ceramic interposer 110 is attached to the carrier plate 100 using solder with a third solder paste (not shown) and reflowed a third time. Thus, the IC chip 130 / ceramic interposer 110 / copper core ball 120 combination is joined to the carrier plate 100 as a complete unit for "directly-mounted like" test verification purposes. Subsequently, the carrier plate 100 with the copper core ball 120, ceramic interposer 110, and IC chip 130 thereon can be separated by de-soldering. Since the contact assembly (200) on the carrier plate 100 includes a primary contact pad and the copper core ball 120 is soldered to a shadow contact pad, the removal of the IC chip 130 does not affect subsequent test production. Figure 2

[0068] In summary, the test apparatus of the present application has a ceramic interposer with a via therein and a copper core ball, so that during the joining of the IC chip, the solder will penetrate the via, thereby reducing the distance effect of the thickness of the ceramic interposer to avoid contact resistance effects. In addition, the concentration of the surfactant in the solder forming the solder ball can be tailored to the desired surface tension behavior to allow the liquid solder to flow into the via without leakage. The specific contact assembly on the carrier plate allows the carrier plate to have multiple test modes, which can be used in the test apparatus of the present application and also in a test socket with probes. In addition, the ceramic interposer of the present application can also have a stiffener to enhance its resistance to warping, which is beneficial for the use of the copper core ball and allows for good electrical connection between the ceramic interposer and the carrier plate.

[0069] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, and are not intended to limit the present application; even though the present application has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above-described embodiments, or make equivalent replacements to some or all of the technical features; and such modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.​

Claims

1. A probeless testing device for IC chip testing, characterized in that, include: Carrier plate; A ceramic insert plate is disposed on the carrier plate, wherein the ceramic insert plate has a first surface, a second surface, and a plurality of connection points, the second surface of the ceramic insert plate faces the carrier plate, wherein each connection point has a plurality of through holes penetrating the first surface and the second surface, the inner wall of each through hole has a metallization layer, the metallization layer extends to a portion of the first surface and a portion of the second surface, and the area of ​​the metallization layer extending to the second surface in each connection point is smaller than the area of ​​its extension to the first surface; A plurality of copper core balls are disposed between the plurality of through holes at each of the connection points between the carrier plate and the ceramic insert plate; and A plurality of contact assemblies are disposed on the surface of the carrier plate facing the ceramic insert plate, wherein one of the plurality of contact assemblies is in electrical contact with one of the plurality of copper core balls. Each of the aforementioned contact components includes: Main pad; A shadow pad is spaced apart from the main pad, and the size of the shadow pad is smaller than the size of the main pad; and Connect the shadow pad to the main pad.

2. The probeless testing device for IC chip testing according to claim 1, characterized in that, Each of the aforementioned contact components also includes: A solder resist layer is formed on the surface of the wiring.

3. The probeless testing device for IC chip testing according to claim 1, characterized in that, The shadow pad is in electrical contact with the copper core ball.

4. The probeless testing device for IC chip testing according to claim 1, characterized in that, It also includes solder balls formed on the extension of the metallization layer at each of the connection points.

5. The probeless testing apparatus for IC chip testing according to claim 4, characterized in that, The concentration of surfactant contained in the solder that forms the solder ball is inversely proportional to the size of each of the through holes.

6. The probeless testing apparatus for IC chip testing according to claim 1, characterized in that, The number of through holes in each connection point of the ceramic insert plate is three or more.

7. The probeless testing apparatus for IC chip testing according to claim 1, characterized in that, The ceramic insert plate also includes a reinforcing member disposed around the periphery of the ceramic insert plate, and the thickness of the reinforcing member is greater than the thickness of the portion of the ceramic insert plate having the plurality of connection points.

8. A method for testing IC chips using the apparatus as described in any one of claims 1 to 7, comprising: The IC chip is attached to the metallization layer of the plurality of connection points on the first surface of the ceramic insert plate using a first solder paste; A first soldering operation is performed to bond the ceramic insert plate to the IC chip, and a portion of the first solder paste penetrates into the plurality of through-holes of the ceramic insert plate. The plurality of copper core balls are attached to the metallization layer of the plurality of connection points on the second surface of the ceramic insert plate using a second solder paste; A second soldering process is performed to bond the ceramic insert plate to the copper core ball; as well as The copper core ball is bonded to the carrier plate.

9. The IC chip testing method according to claim 8, characterized in that, The temperature of the second reflow is lower than that of the first reflow.

10. The IC chip testing method according to claim 8, characterized in that, The melting point of the first solder paste is higher than that of the second solder paste.

11. The IC chip testing method according to claim 8, characterized in that, A method for bonding the copper core ball to the carrier plate includes: The plurality of copper core balls bonded to the ceramic insert plate are attached to the carrier plate using a third solder paste; and Perform the third round of welding.

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