Memory device and erase method

Abstract

Embodiments of the present application provide a memory device and a method of erasing. The memory device includes a main memory, a first sub-memory, and a controller. The first sub-memory outputs a first erase completion signal when the first sub-memory is erased. The controller receives an erase signal to erase the main memory. The controller erases the main memory according to the erase signal and the first erase completion signal.

Description

Technical Field

[0001] This invention relates to a memory device and an erasure method thereof, and more particularly to a secure memory device and an erasure method thereof. Background Technology

[0002] In the era of the Internet of Things, in order to prevent the data inside devices from being stolen by malicious individuals, more and more device manufacturers tend to use chips with security functions as development tools, and the practice of using memory with security functions inside chips as a storage method and data is gradually gaining market attention and favor.

[0003] As the complexity of device applications increases, the memory capacity of the chips used as development tools must also increase. In view of this, many chip designers have begun to try to place more than one memory inside the chip. In order to ensure that the data inside each memory is protected by security functions and can be easily controlled in a unified manner, chip designers often use a main memory to be responsible for the security function switching of itself and each sub-memory.

[0004] However, when users clear security features, how can chip designers ensure that memory data in each block is not accidentally exposed, thus avoiding data security issues? Therefore, it is necessary to optimize the memory erasure process for memory security. Summary of the Invention

[0005] This invention discloses a secure memory device and its erasure method. Since the security of the sub-memory of the memory device is stored in the main memory, when the main memory needs to be erased, it must be erased only after all the sub-memories have been erased. This is to prevent the sub-memories from entering an unlocked state after the main memory is erased, which would expose the secure data in the sub-memories.

[0006] In view of this, the present invention provides a memory device, including a main memory, a first sub-memory, and a controller. When the first sub-memory is erased, the first sub-memory outputs a first erase completion signal. The controller receives an erase signal to erase the main memory, wherein the controller erases the main memory according to the erase signal and the first erase completion signal.

[0007] According to one embodiment of the present invention, the memory device further includes a second sub-memory. When the second sub-memory is completely erased, the second sub-memory outputs a second erase completion signal. The controller erases the main memory based on the erase signal, the first erase completion signal, and the second erase completion signal.

[0008] According to an embodiment of the present invention, when the first sub-memory does not generate the first erase completion signal and / or the second sub-memory does not generate the second erase completion signal, the controller does not erase the main memory.

[0009] According to one embodiment of the present invention, the memory device further includes a security register. The security register stores a first security control and a second security control. The first sub-memory operates in a locked state according to the first security control, and the second sub-memory operates in the locked state according to the second security control. When the controller completes an initialization procedure, the controller writes the first security control and the second security control from the main memory into the security register. When the first sub-memory and / or the second sub-memory are erased, the first sub-memory and / or the second sub-memory operate in an unlocked state according to the first security control and / or the second security control, respectively.

[0010] According to one embodiment of the present invention, either the first sub-memory or the second sub-memory further includes a multiplexer and a trigger. The multiplexer selects one of a first sub-erasure control signal and a first erasure completion signal as an intermediate signal based on the first security control, or selects one of a second sub-erasure control signal and a second erasure completion signal as the intermediate signal based on the second security control. The trigger outputs the intermediate signal as the first erasure completion signal based on a clock signal, or outputs the intermediate signal as the second erasure completion signal based on the clock signal.

[0011] According to an embodiment of the present invention, when the controller receives the first sub-erasure control signal to erase the first sub-memory and / or receives the second sub-erasure control signal to erase the second sub-memory, the controller uses the first security control and / or the second security control to respectively operate the first sub-memory and / or the second sub-memory in an unlocked state, and the multiplexers of the first sub-memory and the second sub-memory respectively generate the first erasure completion signal and the second erasure completion signal.

[0012] According to one embodiment of the present invention, the controller includes an AND gate. The AND gate receives the erase signal, the first erase complete signal, and the second erase complete signal to generate an enable signal. When the erase signal, the first erase complete signal, and the second erase complete signal are all at a first logic level, the enable signal output by the AND gate is the first logic level. The controller erases the main memory in response to the enable signal.

[0013] The present invention further proposes an erasure method applicable to a memory device. The memory device includes a main memory and a first sub-memory. The erasure method includes receiving an erasure signal to erase the main memory; determining whether the first sub-memory has been completely erased; erasing the main memory when the first sub-memory has been completely erased; and not erasing the main memory when the first sub-memory has not been completely erased.

[0014] According to an embodiment of the present invention, the memory device further includes a second sub-memory, wherein the erasure method further includes determining whether the second sub-memory has been erased; erasing the main memory when both the first sub-memory and the second sub-memory have been erased; and not erasing the main memory when the first sub-memory and / or the second sub-memory have not been erased.

[0015] According to an embodiment of the present invention, the memory device further includes a security register for storing a first security control and a second security control, wherein the first sub-memory and the second sub-memory operate in a locked state according to the first security control and the second security control, respectively, wherein when the memory device is initialized, the first security control and the second security control are written from the main memory to the security register, and wherein when the first sub-memory and / or the second sub-memory are erased, the first sub-memory and / or the second sub-memory operate in an unlocked state according to the first security control and / or the second security control, respectively. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a block diagram of a memory device according to an embodiment of the present invention;

[0018] Figure 2 This is a circuit diagram of a circuit unit according to an embodiment of the present invention;

[0019] Figure 3 This is a circuit diagram of a circuit unit according to an embodiment of the present invention;

[0020] Figure 4 This is a flowchart of an erasure method according to an embodiment of the present invention.

[0021] [Icon Numbers]

[0022] 100: Memory device

[0023] 110: Main Memory

[0024] 120: Security Register

[0025] 130-1: First Sub-Memory

[0026] 130-2: Second Sub-Memory

[0027] 130-N: Nth sub-memory

[0028] 140: Controller

[0029] SE: Erasure signal

[0030] SC1: First Safety Control

[0031] SC2: Second Safety Control

[0032] SCN: Nth Security Control

[0033] EC1: First erasure complete signal

[0034] EC2: Second erasure complete signal

[0035] ECN: Nth erasure complete signal

[0036] SES1: First Sub-Erase Signal

[0037] SES2: Second Sub-Erase Signal

[0038] SESN: Nth child erasure signal

[0039] 200, 300: Circuit Units

[0040] 210: Multiplexer

[0041] 220: Trigger

[0042] SC: Safety Control

[0043] SES: Sub-Erase Control Signal

[0044] EC: Erasure complete signal

[0045] SM: Intermediate signal

[0046] 310: and the door

[0047] EN: Enable signal

[0048] 400: Removal Method

[0049] S410~S440: Procedure Flow Detailed Implementation

[0050] The following description illustrates embodiments of the present invention. Its purpose is to demonstrate the general principles of the invention and should not be construed as limiting the invention. The scope of the invention is defined by the claims.

[0051] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments disclosed herein.

[0052] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of the invention. The specific examples and arrangements of elements described below are merely for briefly illustrating the spirit of the invention and are not intended to limit its scope. Furthermore, the same element symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear description and is not intended to limit the relationship between the various embodiments and / or configurations discussed below. Moreover, descriptions in the following description of a feature being connected to, coupled to, and / or formed on another feature may actually encompass multiple different embodiments, including those where the features are in direct contact, or those where additional features are formed between the features, such that the features are not in direct contact.

[0053] Figure 1 This is a block diagram of a memory device according to an embodiment of the present invention. Figure 1As shown, the memory device 100 includes a main memory 110, a security register 120, a first sub-memory 130-1, a second sub-memory 130-2, ..., an Nth sub-memory 130-N, and a controller 140. According to an embodiment of the present invention, the main memory 110 is used to store the security controls of the main memory 110, the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N.

[0054] Security register 120 is used to store first security controls SC1, second security controls SC2, ..., and Nth security controls SCN, which respectively control the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N. According to one embodiment of the present invention, when the controller 140 completes the initialization procedure, the controller 140 writes the first security controls SC1, the second security controls SC2, ..., and the Nth security controls SCN from the autonomous memory 110 to the security register 120. Furthermore, the controller 140 uses the first security controls SC1, the second security controls SC2, ..., and the Nth security controls SCN stored in the security register 120 to control the security of the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N, respectively. According to one embodiment of the present invention, as... Figure 1 As shown, the security register 120 is coupled to the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N.

[0055] According to an embodiment of the present invention, when any of the first security control SC1, the second security control SC2, ... and the Nth security control SCN is at the first logic level, the corresponding first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N are in a locked state, so that the controller 140 cannot perform an erase operation on the corresponding first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N, and the data stored in the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N are protected with security.

[0056] According to another embodiment of the present invention, when any of the first security control SC1, the second security control SC2, ... and the Nth security control SCN is at the second logic level, the corresponding first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N are in an unlocked state, so that the controller 140 can perform an erase operation on the corresponding first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N, and the data stored in the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N is unprotected.

[0057] When any of the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N completes the erase operation, the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N respectively generate a first erase completion signal EC1, a second erase completion signal EC2, ..., and an Nth erase completion signal ECN. Furthermore, the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N respectively send the generated first erase completion signal EC1, second erase completion signal EC2, ..., and Nth erase completion signal ECN to the controller 140.

[0058] The controller 140 receives an erase signal SE, a first sub-erasure signal SES1, a second sub-erasure signal SES2, ..., an Nth sub-erasure signal SESN, a first erase completion signal EC1, a second erase completion signal EC2, ..., and an Nth erase completion signal ECN to perform corresponding erase operations. The erase signal SE is used to erase the main memory 110, and the first sub-erasure signals SES1, SES2, ..., and SESN are used to erase the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N, respectively. The controller 140 further provides the first sub-erasure signals SES1, SES2, ..., and SESN to the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N, respectively. According to an embodiment of the present invention, the controller 140 performs an erase operation on the main memory 110 based on the erase signal SE, the first erase completion signal EC1, the second erase completion signal EC2, ... and the Nth erase completion signal ECN.

[0059] In other words, the controller 140 will not erase the main memory 110 until any of the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N has completed the erasure operation.

[0060] Since the first security control SC1, the second security control SC2, ... and the Nth security control SCN of the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N are stored in the main memory 110, if the main memory 110 is erased before the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N are cleared, the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N will be forced into an unlocked state, thus exposing the stored data.

[0061] Figure 2 This is a circuit diagram of a circuit unit according to an embodiment of the present invention. According to an embodiment of the present invention, circuit unit 200 is located in... Figure 1 Each of the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N.

[0062] like Figure 2 As shown, circuit unit 200 includes a multiplexer 210 and a trigger 220. The multiplexer 210 selects the erase control signal SES and the erase completion signal EC as the intermediate signal SM according to the security control SC. According to an embodiment of the present invention, the security control SC corresponds to... Figure 1 One of the first security control SC1, the second security control SC2, ... and the Nth security control SCN, the sub-erasure control signal SES corresponds to... Figure 1 The first sub-erase control signal SES1, the second sub-erase control signal SES2, ... and the Nth sub-erase control signal SESN. The trigger 220 outputs the intermediate signal SM as the erase completion signal EC according to the clock signal CLK, where the erase completion signal EC corresponds to the first erase completion signal EC1, the second erase completion signal EC2, ... and the Nth erase completion signal ECN.

[0063] For example, when the Nth sub-memory 130-N is based on the Nth security control SCN (corresponding to) at the first logic level... Figure 2 When the multiplexer 210 operates in the locked state according to the Nth safety control SCN (corresponding to the Nth safety control SCN), the multiplexer 210 operates in the locked state according to the Nth safety control SCN (corresponding to the Nth safety control SCN). Figure 2The security control SC shown selects the Nth erase completion signal ECN (corresponding to...). Figure 2 The erase completion signal EC shown is used as the intermediate signal SM. In other words, trigger 220 latches the Nth erase completion signal ECN (corresponding to...). Figure 2 The erase completion signal EC shown makes the Nth erase completion signal ECN (corresponding to) Figure 2 The erase completion signal (EC) shown maintains the same logic level.

[0064] For example, when the Nth sub-memory 130-N is based on the Nth security control SCN located at the second logic level (corresponding to... Figure 2 The security control SC shown operates in the unlocked state and is activated according to the Nth sub-erasure control signal SESN (corresponding to the high logic level). Figure 2 When the erase operation is performed by the sub-erasure control signal SES shown, the multiplexer 210 determines the Nth safety control SCN (corresponding to the Nth safety control SCN) according to the Nth safety control SCN. Figure 2 The security control SC shown selects the Nth sub-erasure control signal SESN (corresponding to...). Figure 2 The sub-erase control signal SES shown is used as an intermediate signal SM. Therefore, trigger 220 will convert the Nth sub-erase control signal SESN (corresponding to...) into an intermediate signal SM. Figure 2 The sub-erase control signal SES shown is output as the Nth erase completion signal ECN (corresponding to...). Figure 2 The erase completion signal (EC) is shown.

[0065] Figure 3 This is a circuit diagram of a circuit unit according to an embodiment of the present invention. Figure 3 As shown, circuit unit 300 includes AND gate 310. According to an embodiment of the present invention, circuit unit 300 is located in controller 140. AND gate 310 receives erase signal SE, first erase completion signal EC1, second erase completion signal EC2, ... and Nth erase completion signal ECN and performs logical operations to generate enable signal EN. When erase signal SE, first erase completion signal EC1, second erase completion signal EC2, ... and Nth erase completion signal ECN are all at high logic level, the enable signal EN output by AND gate 310 is at high logic level, wherein controller 140 erases main memory 110 in response to the enable signal EN at high logic level.

[0066] According to one embodiment of the present invention, when the enable signal EN is at a high logic level, it indicates that the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N have all completed the erase operation, and the erase signal SE for erasing the main memory 110 has also been received. Therefore, the AND gate 310 generates an enable signal EN at a high logic level. The controller 140 erases the main memory 110 in response to the enable signal EN at a high logic level, which ensures that the main memory 110 will not be erased before any of the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N has completed the erase operation, thereby preserving the security protection of the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N.

[0067] Figure 4 This is a flowchart illustrating an embodiment of the erasure method of the present invention. The following is specifically for... Figure 4 The flowchart shown will be described in conjunction with Figure 1 A block diagram is provided to facilitate detailed explanation.

[0068] like Figure 4 The erase method 400 shown first receives an erase signal SE to erase the main memory 110 (step S410). It then determines whether the first sub-memory 130-1, the second sub-memory 130-2, ..., and the Nth sub-memory 130-N have all been erased (step S420). According to an embodiment of the present invention, as... Figure 3 As shown, the enable signal EN of AND gate 310 is used to determine whether the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N have all been erased.

[0069] When it is determined that the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N have all been erased, the main memory 110 is erased (step S430). In detail, Figure 3 AND gate 310 determines whether the erase signal SE, the first erase completion signal EC1, the second erase completion signal EC2, ... and the Nth erase completion signal ECN are all at a high logic level. When the erase signal SE, the first erase completion signal EC1, the second erase completion signal EC2, ... and the Nth erase completion signal ECN are all at a high logic level, it means that the main memory 110 can be erased.

[0070] If it is determined that the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N have not been completely erased, the main memory is not erased (step S440), and step S420 is executed again until the first sub-memory 130-1, the second sub-memory 130-2, ... and the Nth sub-memory 130-N have all been completely erased before the main memory 110 is erased.

[0071] This invention discloses a secure memory device and its erasure method. Since the security of the sub-memory of the memory device is stored in the main memory, when the main memory needs to be erased, it must be erased only after all the sub-memories have been erased, in order to prevent the sub-memories from entering an unlocked state after the main memory is erased, which would expose the secure data in the sub-memory.

[0072] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that those skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of this specification. Those skilled in the art can understand, from the disclosure of some embodiments of this disclosure, current or future developed manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned manufacturing processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments.

Claims

1. A memory device, comprising: Comprising: a main memory storing a first security control; a first sub-memory, wherein when the first sub-memory is completely erased, the first sub-memory outputs a first erase completion signal; and a controller receiving an erase signal to erase the main memory, wherein the controller erases the main memory according to the erase signal and the first erase completion signal; wherein the first sub-memory operates in a lock state according to the first security control.

2. The memory device of claim 1, wherein, Further comprising: a second sub-memory, wherein when the second sub-memory is completely erased, the second sub-memory outputs a second erase completion signal, wherein the controller erases the main memory according to the erase signal, the first erase completion signal and the second erase completion signal.

3. The memory device of claim 2, wherein, When the first sub-memory does not generate the first erase completion signal and / or the second sub-memory does not generate the second erase completion signal, the controller does not erase the main memory.

4. The memory device of claim 2, wherein, Further comprising: a security register storing the first security control and a second security control, the second sub-memory operates in the lock state according to the second security control, wherein when the controller completes an initialization procedure, the controller writes the first security control and the second security control from the main memory to the security register, wherein when the first sub-memory and / or the second sub-memory is erased, the first sub-memory and / or the second sub-memory operates in an unlock state according to the first security control and / or the second security control, respectively.

5. The memory device of claim 4, wherein, Either of the first sub-memory and the second sub-memory further comprises: a multiplexer selecting one of a first sub-erase control signal and the first erase completion signal as an intermediate signal according to the first security control, or selecting one of a second sub-erase control signal and the second erase completion signal as the intermediate signal according to the second security control; and a flip-flop outputting the intermediate signal as the first erase completion signal according to a clock signal, or outputting the intermediate signal as the second erase completion signal according to the clock signal.

6. The memory device of claim 5, wherein, When the controller receives the first sub-erase control signal to erase the first sub-memory and / or receives the second sub-erase control signal to erase the second sub-memory, the controller operates the first sub-memory and / or the second sub-memory in an unlock state according to the first security control and / or the second security control, respectively, and the multiplexer of the first sub-memory and the second sub-memory generates the first erase completion signal and the second erase completion signal, respectively.

7. The memory device of claim 3, wherein, The controller comprises: a NAND gate receiving the erase signal, the first erase completion signal and the second erase completion signal to generate an enable signal, wherein the enable signal outputted from the NAND gate is a first logic level when the erase signal, the first erase completion signal and the second erase completion signal are all the first logic level, wherein the controller is responsive to the enable signal to erase the main memory.

8. An erase method suitable for use with a memory device, the method comprising: The memory device includes a main memory storing a first security control and a first sub-memory operating in a locked state according to the first security control, wherein the erase method includes: receiving an erase signal to erase the main memory; determining whether the first sub-memory is erased; erasing the main memory when the first sub-memory is erased; and not erasing the main memory when the first sub-memory is not erased.

9. The erasing method according to claim 8, wherein The memory device further includes a second sub-memory, wherein the erase method further includes: determining whether the second sub-memory is erased; erasing the main memory when the first sub-memory and the second sub-memory are both erased; and not erasing the main memory when the first sub-memory and / or the second sub-memory is not erased.

10. The erasing method according to claim 9, wherein The memory device further includes a security register storing the first security control and a second security control, wherein the first sub-memory and the second sub-memory are operating in the locked state according to the first security control and the second security control respectively, wherein the first security control and the second security control are written from the main memory to the security register when the memory device completes an initialization procedure, wherein the first sub-memory and / or the second sub-memory is operating in an unlocked state according to the first security control and / or the second security control respectively when the first sub-memory and / or the second sub-memory is erased.

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