Method for preparing a semiconductor structure, semiconductor structure and semiconductor memory

Abstract

The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes: providing a substrate; an active region is included in the substrate; forming a first dielectric wall and a second dielectric wall extending along a first direction on the substrate; the first dielectric wall and the second dielectric wall are alternately distributed; etching the first dielectric wall and the second dielectric wall to form trenches extending along a second direction; wherein, the trenches are arranged at intervals; within the trenches, the height of the remaining first dielectric wall is greater than the height of the remaining second dielectric wall; etching the remaining second dielectric wall within the trenches to form first contact holes arranged at intervals within the trenches; the first contact holes expose the active region. The present application can form a novel semiconductor structure with fewer photomask times for metal wiring.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processes, and particularly to a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. Background Art

[0002] With the continuous development of semiconductor technology, integrated circuits are constantly pursuing high speed, high integration density, and low power consumption. Therefore, the structural dimensions of semiconductor devices in integrated circuits are also continuously miniaturized.

[0003] Existing semiconductor structures are increasingly difficult to meet the development needs, and semiconductor structures need to be continuously innovated to design more novel semiconductor structures. Summary of the Invention

[0004] Embodiments of the present application are expected to provide a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory, which can form a novel semiconductor structure with fewer photomask times for metal wiring.

[0005] The technical solution of the present application is implemented as follows:

[0006] Embodiments of the present application provide a method for manufacturing a semiconductor structure, the method comprising:

[0007] Providing a substrate; an active region is included in the substrate;

[0008] Forming a first dielectric wall and a second dielectric wall extending along a first direction on the substrate; the first dielectric wall and the second dielectric wall are alternately distributed;

[0009] Etching the first dielectric wall and the second dielectric wall to form trenches extending along a second direction; wherein, the trenches are spaced apart; within the trenches, the height of the remaining first dielectric wall is greater than the height of the remaining second dielectric wall;

[0010] Etching the remaining second dielectric wall within the trenches to form first contact holes spaced apart within the trenches; the first contact holes expose the active region.

[0011] Embodiments of the present application further provide a semiconductor structure manufactured by the manufacturing method in the above solution.

[0012] Embodiments of the present application further provide a semiconductor memory including the semiconductor structure in the above solution.

[0013] As can be seen, the embodiments of the present application provide a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory, which can form a first dielectric wall and a second dielectric wall extending along a first direction on the provided substrate, wherein the first dielectric wall and the second dielectric wall are alternately distributed; then, the first dielectric wall and the second dielectric wall are etched to form trenches extending along a second direction, wherein the height of the remaining first dielectric wall in the trenches is greater than the height of the remaining second dielectric wall; then, the remaining second dielectric wall in the trenches is etched to form first contact holes arranged at intervals in the trenches, wherein the first contact holes expose the active regions in the substrate. In this way, the trenches provide a buried area for metal wiring, and the first contact holes provide contact points between the metal wiring and the active regions, and only two photomasks are required for the two etching processes; thus, a novel semiconductor structure capable of performing metal wiring is formed with a small number of photomask times, providing a new option for semiconductor processes. Description of the Drawings

[0014] Figure 1 Flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present application Figure 1 ;

[0015] Figure 2A Schematic diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present application Figure 1 ;

[0016] Figure 2B Schematic diagram II of a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0017] Figure 3A Schematic diagram III of a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0018] Figure 3B Schematic diagram IV of a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0019] Figure 4A Schematic diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present application Figure 5 ;

[0020] Figure 4B Schematic diagram VI of a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0021] Figure 5 Flow chart II of a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0022] Figure 6A Schematic diagram VII of a method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0023] Figure 6BSchematic diagram eight of a semiconductor structure preparation method provided by an embodiment of the present application;

[0024] Figure 7A Schematic diagram nine of a semiconductor structure preparation method provided by an embodiment of the present application;

[0025] Figure 7B Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 ;

[0026] Figure 8A Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 One;

[0027] Figure 8B Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 Two;

[0028] Figure 9A Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 Three;

[0029] Figure 9B Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 Four;

[0030] Figure 10 Flowchart three of a semiconductor structure preparation method provided by an embodiment of the present application;

[0031] Figure 11A Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 Five;

[0032] Figure 11B Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 Six;

[0033] Figure 12A Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 Seven;

[0034] Figure 12B Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 Eight;

[0035] Figure 13A Schematic of a semiconductor structure preparation method provided by an embodiment of the present application Figure 10 Nine;

[0036] Figure 13BSchematic diagram twenty of a semiconductor structure manufacturing method provided by an embodiment of the present application;

[0037] Figure 14A Schematic diagram twenty - one of a semiconductor structure manufacturing method provided by an embodiment of the present application;

[0038] Figure 14B Schematic of a semiconductor structure manufacturing method provided by an embodiment of the present application Figure 22 ;

[0039] Figure 15A Schematic of a semiconductor structure manufacturing method provided by an embodiment of the present application Figure 23 ;

[0040] Figure 15B Schematic diagram twenty - four of a semiconductor structure manufacturing method provided by an embodiment of the present application;

[0041] Figure 16A Schematic of a semiconductor structure manufacturing method provided by an embodiment of the present application Figure 25 ;

[0042] Figure 16B Schematic of a semiconductor structure manufacturing method provided by an embodiment of the present application Figure 26 ;

[0043] Figure 17A Schematic of a semiconductor structure manufacturing method provided by an embodiment of the present application Figure 27 ;

[0044] Figure 17B Schematic diagram twenty - eight of a semiconductor structure manufacturing method provided by an embodiment of the present application;

[0045] Figure 18A Schematic diagram twenty - nine of a semiconductor structure manufacturing method provided by an embodiment of the present application;

[0046] Figure 18B Schematic of a semiconductor structure manufacturing method provided by an embodiment of the present application Figure 30 One;

[0047] Figure 19 Flowchart four of a semiconductor structure manufacturing method provided by an embodiment of the present application;

[0048] Figure 20A Schematic of a semiconductor structure manufacturing method provided by an embodiment of the present application Figure 30 Two;

[0049] Figure 20B Schematic of a semiconductor structure manufacturing method provided by an embodiment of the present application Figure 30 Three;

[0050] Figure 21A Schematic of a method for preparing a semiconductor structure provided by an embodiment of the present application Figure 30 Four;

[0051] Figure 21B Schematic of a method for preparing a semiconductor structure provided by an embodiment of the present application Figure 30 Five;

[0052] Figure 22 Flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present application Figure 5 ;

[0053] Figure 23 Schematic of a method for preparing a semiconductor structure provided by an embodiment of the present application Figure 30 Six;

[0054] Figure 24A Schematic of a method for preparing a semiconductor structure provided by an embodiment of the present application Figure 30 Seven;

[0055] Figure 24B Schematic of a method for preparing a semiconductor structure provided by an embodiment of the present application Figure 30 Eight;

[0056] Figure 25 Flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present application; Six

[0057] Figure 26 Schematic of a method for preparing a semiconductor structure provided by an embodiment of the present application Figure 30 Nine;

[0058] Figure 27 Schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present application; Forty

[0059] Figure 28A Schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present application; Forty - one

[0060] Figure 28B Schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present application; Forty - two

[0061] Figure 29A Schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present application; Forty - three

[0062] Figure 29B Schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present application; Forty - four

[0063] Figure 30 Flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present application; Seven

[0064] Figure 31A Schematic diagram forty-five of a method for preparing a semiconductor structure provided by an embodiment of the present application;

[0065] Figure 31B Schematic diagram forty-six of a method for preparing a semiconductor structure provided by an embodiment of the present application;

[0066] Figure 32A Schematic diagram forty-seven of a method for preparing a semiconductor structure provided by an embodiment of the present application;

[0067] Figure 32B Schematic diagram forty-eight of a method for preparing a semiconductor structure provided by an embodiment of the present application;

[0068] Figure 33 Schematic diagram of the structure of a semiconductor memory provided by an embodiment of the present application. Detailed implementation manners

[0069] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be construed as limiting the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0070] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0071] If similar descriptions such as "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" only distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0073] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor component in electronic devices such as computers. It consists of multiple memory cells, and each memory cell typically includes a transistor and a capacitor. Among them, the gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that data information stored in the capacitor can be read through the bit line, or data information can be written into the capacitor.

[0074] The development of dynamic memory pursues performance indicators such as high speed, high integration density, and low power consumption. With the miniaturization of the semiconductor device structure size, especially in the manufacturing process of DRAM with a critical dimension less than 15 nm, the technical barriers encountered by the existing structure are becoming more and more obvious. Therefore, on the basis of the existing structure, developing more novel structures is an effective means to break through the existing technical barriers.

[0075] Figure 1 is an optional process schematic diagram of the preparation method of the semiconductor structure provided by the embodiments of the present application, and will be described in conjunction with Figure 1 the steps shown.

[0076] S101. Provide a substrate; the substrate includes an active region.

[0077] In the embodiments of the present application, Figure 2B is a side view cross-sectional view. As Figure 2B shown, the substrate 00 can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a germanium-arsenic substrate, a Silicon On Insulator (SOI) substrate, or a Germanium On Insulator (GOI) substrate, etc. The substrate 00 can be doped or undoped. Exemplarily, the substrate 00 can be an N-type substrate or a P-type substrate. The substrate 00 includes an active region 01,...

[0078] It should be noted that the substrate is a clean single-crystal thin wafer used for semiconductor processing, which has a specific crystal plane and appropriate electrical, optical, and mechanical properties. The semiconductor structure is processed on the substrate.

[0079] S102. Form a first dielectric wall and a second dielectric wall extending along a first direction on the substrate; the first dielectric wall and the second dielectric wall are alternately distributed.

[0080] In the embodiments of the present application, the semiconductor device can form a first dielectric wall and a second dielectric wall extending along a first direction on the substrate. Figure 2A and Figure 2B are respectively a top view and a side view cross-sectional view. As Figure 2A andFigure 2B As shown, a first dielectric wall 11 and a second dielectric wall 12 extending along a first direction X are formed on a substrate 00, and the first dielectric wall 11 and the second dielectric wall 12 are alternately distributed.

[0081] In an embodiment of the present application, the material of the first dielectric wall may be silicon nitride (SiN), and the material of the second dielectric wall may be silicon dioxide (SiO2).

[0082] S103. Etch the first dielectric wall and the second dielectric wall to form trenches extending along a second direction; wherein, the trenches are arranged at intervals; within the trenches, the height of the remaining first dielectric wall is greater than the height of the remaining second dielectric wall.

[0083] In an embodiment of the present application, a semiconductor device may etch the first dielectric wall and the second dielectric wall to form trenches extending along a second direction. Figure 3A and Figure 3B are a top view and a front cross-sectional view respectively. As shown in Figure 3A and Figure 3B shown, the first dielectric wall 11 and the second dielectric wall 12 are etched to form trenches 13, wherein the trenches 13 extend along a second direction Y and are arranged at intervals. Within the trenches 13, the height of the remaining first dielectric wall 11 is greater than the height of the remaining second dielectric wall 12. Therefore, in Figure 3B , the remaining first dielectric wall 11 within the trenches 13 blocks the remaining second dielectric wall 12. In this way, the position of the remaining second dielectric wall within the trenches 13 forms a square hole as shown in Figure 3A shown.

[0084] In an embodiment of the present application, if the etching rate ratio of the material of the first dielectric wall to the material of the second dielectric wall is 1:4, then the height of the remaining first dielectric wall 11 within the trenches 13 accounts for three-quarters of the depth of the trenches 13.

[0085] In an embodiment of the present application, a semiconductor device may first form a mandrel with a relatively wide interval through a lithography process. As shown in Figure 12A and Figure 12B shown, the mandrel 301 extends along a second direction Y. Then, sidewalls may be formed on both sides of the mandrel. As shown in Figure 15A and Figure 15B shown, the sidewalls 311 cover both sides of the mandrel 301, and the sidewalls 311 also extend along a second direction Y. Finally, using the sidewalls as a mask, trenches 13 are etched. Since the sidewalls 311 are formed in the interval region of the mandrel 301 and their spacing is smaller than the spacing of the mandrel 301, the size of the etched trenches 13 is smaller than the size of the mandrel 301, that is, trenches with a smaller size are formed using a photomask with a larger size.

[0086] S104. Etch the remaining second dielectric walls in the trench to form first contact holes arranged at intervals in the trench; the first contact holes expose the active regions.

[0087] In the embodiment of the present application, the semiconductor device can etch the remaining second dielectric walls in the trench to form first contact holes arranged at intervals in the trench; wherein, the first contact holes penetrate through the remaining second dielectric walls, thereby exposing the active regions. Figure 4A and Figure 4B are respectively a top view and a front cross-sectional view. As shown in Figure 4A and Figure 4B , the remaining second dielectric walls 12 in the trench 13 are etched to form first contact holes 14. The first contact holes 14 are arranged at intervals and expose the active regions 01.

[0088] In the embodiment of the present application, the semiconductor device can first deposit a third barrier layer in the trench, and then form a second mask on the third barrier layer through a lithography process. Figure 20A and Figure 20B are respectively a top view and a front cross-sectional view. As shown in Figure 20A and Figure 20B , the third barrier layer 50 is deposited on the trench 13 to cover the trench 13; a second mask 60 is formed on the third barrier layer 50, and the second mask 60 includes recessed holes (i.e., second etching patterns 601) arranged at intervals; wherein, the recessed holes need to be aligned with the square holes of the remaining second dielectric walls 12 in the trench 13. In this way, first contact holes 14 can be formed at the positions of the remaining second dielectric walls 12, as shown in Figure 4A . Then, the semiconductor device can perform at least one etching along the second etching pattern 601 to remove the third barrier layer 50 and etch the remaining second dielectric walls 12 in the trench 13 to form the first contact holes 14 as shown in Figure 4A .

[0089] It can be understood that in the embodiment of the present application, first dielectric walls and second dielectric walls extending along a first direction and distributed alternately are first formed on the substrate, and then the first dielectric walls and the second dielectric walls are etched to form trenches extending along a second direction. In this way, by using different materials of the first dielectric walls and the second dielectric walls and selecting an appropriate etching rate ratio, the height of the remaining first dielectric walls in the trench is greater than the height of the remaining second dielectric walls, and square holes are formed at the positions of the remaining second dielectric walls, providing a position basis for the setting of the first contact holes.

[0090] Then, aligned with the square holes, the remaining second dielectric walls in the trench are etched to form first contact holes arranged at intervals. In this way, the trench provides a buried area for metal wiring, and the first contact holes provide contact points between the metal wiring and the active region, and only two photomasks are required for the two etching processes. Thus, a novel semiconductor structure capable of performing metal wiring is formed with a smaller number of photomasks, providing a new option for semiconductor processes.

[0091] In some embodiments of the present application, Figure 1 after S104 shown, it further includes Figure 5 S105 - S107 shown, which will be described in combination with each step.

[0092] S105. Form a first conductive layer in the trench; the first conductive layer fills the first contact holes and at least part of the trench.

[0093] In the embodiments of the present application, after the semiconductor device forms the first contact holes in the trench, a first conductive layer can be formed in the trench. The first conductive layer fills the first contact holes and at least a part of the trench. Figure 6A and Figure 6B are a top view and a front cross-sectional view respectively. As Figure 6A and Figure 6B shown, a first conductive layer 15 is formed in the trench 13. The first conductive layer 15 fills the first contact holes and a part of the trench 13, that is, the thickness of the first conductive layer 15 is less than the depth of the trench 13. At the same time, the semiconductor device can also form second isolation layers 17 made of the same material as the first dielectric wall 11 on both sides of the first conductive layer 15, and the second isolation layers 17 isolate the first conductive layer 15 from other parts.

[0094] In the embodiments of the present application, since if a metal material directly contacts the active region, it will diffuse into the active region and damage the electrical characteristics of the active region. Therefore, the semiconductor device can first deposit a metal isolation layer, such as TiN, in the first contact holes to block the diffusion of the metal material into the active region; then, deposit a metal layer, as Figure 23 shown, the metal layer 70 covers the metal isolation layer and fills the first contact holes 14 (not shown due to occlusion) and the trench 13. Among them, the material of the metal layer 70 can be tungsten (W) or copper (Cu); then, grind the metal layer 70 until the top of the trench 13, that is, adopt the damascene process to grind the metal layer 70 to form the first conductive layer 15 as shown in Figure 24A and 24B shown.

[0095] In the embodiments of the present application, the first conductive layer 15 can be used for the bit line structure.

[0096] S106. Etch the remaining second dielectric wall outside the trench to form a second contact hole; the second contact hole exposes the active region.

[0097] In the embodiment of the present application, after the first conductive layer is formed, the semiconductor device can etch the remaining second dielectric wall outside the trench to form a second contact hole, and the second contact hole exposes the active region.

[0098] In the embodiment of the present application, the semiconductor device can first form a first isolation layer on the first conductive layer. Figure 7A And Figure 7B Are a top view and a front cross-sectional view respectively. As Figure 7A And Figure 7B Shown, a first isolation layer 16 is formed on the first conductive layer 15. The first isolation layer 16 covers the first conductive layer 15 and fills the remaining part of the trench 13. The materials of the first isolation layer 16 and the first dielectric wall 11 are the same.

[0099] Then, the semiconductor device can use the first isolation layer and the remaining first dielectric wall outside the trench as a mask to etch the remaining second dielectric wall outside the trench to form a second contact hole. Here, since the materials of the first isolation layer 16 and the first dielectric wall 11 are the same, the semiconductor device can etch with an etching selectivity ratio of the second dielectric wall 12 being higher than that of the first isolation layer 16 and the first dielectric wall 11. For example, if the materials of the first isolation layer 16 and the first dielectric wall 11 are silicon nitride and the material of the second dielectric wall 12 is silicon oxide, then an etching selectivity ratio of silicon oxide being higher than that of silicon nitride is used for etching. In this way, only the remaining second dielectric wall 12 outside the trench 13 is etched, and the first isolation layer 16 and the first dielectric wall 11 are retained. Figure 8A And Figure 8B Are a top view and a front cross-sectional view respectively. As Figure 8A And Figure 8B Shown, after the remaining second dielectric wall 12 outside the trench 13 is etched, a second contact hole 18 is formed, and the second contact hole 18 exposes the active region 01.

[0100] S107. Form a second conductive layer in the second contact hole.

[0101] In the embodiment of the present application, after the second contact hole is formed, the semiconductor device can form a second conductive layer in the second contact hole. Figure 9A And Figure 9B Are a top view and a front cross-sectional view respectively. As Figure 9A And Figure 9B Shown, the semiconductor device forms a second conductive layer 19 in the second contact hole 18. The second conductive layer 19 fills part of the second contact hole 18 and is in contact with the active region 01.

[0102] In an embodiment of the present application, a semiconductor device may first form a second isolation layer in a second contact hole. Figure 31B is a front view cross-sectional view, as Figure 31B shown, the second isolation layer 17 covers the side surface of the first conductive layer 15. Then, the semiconductor device may deposit a conductive medium, and the material of the conductive medium layer may be polysilicon. Figure 31A and Figure 31B are a top view and a front view cross-sectional view respectively, as Figure 31A and Figure 31B shown, the conductive medium 90 fills the second contact hole 18 and covers the first conductive layer 15, and the second isolation layer 17 separates the conductive medium 90 from the first conductive layer 15. Then, the semiconductor device may perform a high-selectivity etching of the conductive medium 90, that is, the etching rate of the conductive medium 90 is higher than that of other materials; etching like this until the height of the conductive medium 90 is lower than the top of the second contact hole 18, exposing the remaining first dielectric wall 11 and the first isolation layer 16 outside the trench, as Figure 32A shown. In this way, the remaining conductive medium 90 forms the second conductive layer 19; and the second isolation layer 17 separates the first conductive layer 15 from the second conductive layer 19.

[0103] It can be understood that a first conductive layer is formed in the trench and contacts the active region through a first contact hole; at the same time, using the remaining second dielectric wall outside the trench as a mask, a second contact hole is etched and formed at its corresponding position, and a second conductive layer is filled. In this way, without using a photomask, the second contact hole is etched and formed by using the pattern of the semiconductor structure itself, achieving the purpose of self-alignment.

[0104] At the same time, the first conductive layer is formed by filling the trench, and the second conductive layer is formed by filling the second contact hole, and both are buried structures, thereby reducing the height of the semiconductor structure and being beneficial to improving the integration density in the vertical direction.

[0105] In some embodiments of the present application, S103 shown in Figure 10 can be implemented through S201 - S204 shown in Figure 1 , and will be described in conjunction with each step.

[0106] S201: Deposit a first barrier layer and a second barrier layer on the first dielectric wall and the second dielectric wall in sequence.

[0107] In an embodiment of the present application, the semiconductor device may deposit a first barrier layer and a second barrier layer on the first dielectric wall and the second dielectric wall in sequence. It should be noted that the barrier layer is used to form a downwardly transferred pattern as needed, and to protect the areas that do not need to be etched during etching. Figure 11A and Figure 11B are a top view and a front view cross-sectional view respectively, asFigure 11A and Figure 11B As shown, a first barrier layer 20 and a second barrier layer 30 are sequentially deposited on the first dielectric wall 11 and the second dielectric wall 12 (due to the occlusion relationship, the alternating structure of the first dielectric wall 11 and the second dielectric wall 12 is not shown in Figure 11B .) The materials of the first barrier layer 20 and the second barrier layer 30 may include: SiON (silicon oxynitride) and SOH (Spin-on Hardmasks).

[0108] S202. Etch the second barrier layer to form mandrels extending in the second direction; the mandrels are arranged at intervals.

[0109] In the embodiment of the present application, the semiconductor device may etch the second barrier layer to form mandrels extending in the second direction, wherein the mandrels are arranged at intervals.

[0110] In the embodiment of the present application, as shown in Figure 11A and Figure 11B , the semiconductor device may first form a first mask 40 on the second barrier layer 30 through a photolithography process, and the shape of the first mask 40 is characterized as a first etching pattern extending along the second direction Y. Then, the semiconductor device may etch the second barrier layer 30 along the first etching pattern to form the Figure 12A and Figure 12B shown mandrels 301. The mandrels 301 extend along the second direction Y and are arranged at intervals.

[0111] S203. Form sidewalls covering the sides of the mandrels.

[0112] In the embodiment of the present application, the semiconductor device may form sidewalls covering the sides of the mandrels.

[0113] In the embodiment of the present application, as shown in Figure 13A and Figure 13B , the semiconductor device may first deposit a hard mask layer 31 by ALD (Atomic Layer Deposition) process to cover the first barrier layer 20 and the mandrels 301.

[0114] Then, as shown in Figure 14A and Figure 14B , the semiconductor device may fill the voids between the hard mask layers 31 with a third dielectric layer 32, and the third dielectric layer 32 serves as a barrier layer in subsequent etching.

[0115] Then, the semiconductor device may etch back the hard mask layer 31 to remove the top of the hard mask layer 31 until the mandrels 301 are exposed, and retain the sides of the hard mask layer 31 as sidewalls 311, as shown in Figure 15A and Figure 15B . The sidewalls 311 also extend along the second direction Y.

[0116] S204. Etch using the sidewall as a mask to remove the first barrier layer, and etch the first dielectric wall and the second dielectric wall to form trenches.

[0117] In the embodiment of the present application, the semiconductor device can etch using the sidewall as a mask to remove the first barrier layer, and etch the first dielectric wall and the second dielectric wall to form trenches extending in the second direction.

[0118] In the embodiment of the present application, referring to Figure 15A and Figure 15B , there is a mandrel 301 remaining in the middle of the sidewall 311. The semiconductor device can first etch using a high selectivity etching rate to remove the mandrel 301 remaining in the middle of the sidewall 311. Here, the high selectivity means that the etching rate of the material of the mandrel 301 is much greater than the etching rates of other materials, and the obtained structure is as shown in Figure 16A and Figure 16B . Then, in combination with Figure 16B and Figure 17B , the semiconductor device can use the sidewall 311 as a mask to etch the first barrier layer 20 to form a first intermediate structure 201 as shown in Figure 17B , and expose the first dielectric wall 11 and the second dielectric wall 12. As shown in Figure 17A , the first intermediate structure 201 extends along the second direction Y in the same way as the sidewall 311, and the first dielectric wall 11 and the second dielectric wall 12 are exposed at the gap of the first intermediate structure 201.

[0119] Then, in combination with Figure 17B and Figure 18B , the semiconductor device can use the first intermediate structure 201 as a mask to etch the first dielectric wall 11 and the second dielectric wall 12 according to the etching rate ratio; here, the etching rate ratio can be that the etching rate ratio of the material of the first dielectric wall to the material of the second dielectric wall is 1:4. In this way, a structure as shown in Figure 18B can be obtained. At the gap of the first intermediate structure 201, the first dielectric wall 11 and the second dielectric wall 12 are etched to form trenches 13; inside the trenches 13, the height of the remaining first dielectric wall 11 is greater than the height of the remaining second dielectric wall 12, that is, in Figure 18B , the remaining first dielectric wall 11 in the trenches 13 blocks the remaining second dielectric wall 12.

[0120] Then, the semiconductor device can remove the remaining first intermediate structure 201, thereby obtaining a structure as shown in Figure 3A and Figure 3B . Here, if the etching rate ratio of the material of the first dielectric wall to the material of the second dielectric wall is 1:4, the height of the remaining first dielectric wall 11 in the trenches 13 accounts for three - quarters of the depth of the trenches 13.

[0121] It can be understood that in the embodiments of the present application, after the semiconductor device deposits the first barrier layer 20 and the second barrier layer 30, a first mask 40 is first formed through a lithography process, and a mandrel 301 is etched along the first mask 40; then, sidewalls 311 are formed to cover the side surfaces of the mandrel 301; finally, trenches 13 are etched using the sidewalls 311 as a mask. Since the sidewalls 311 are formed in the spaced regions of the mandrel 301, the spacing therebetween is smaller than the spacing between the mandrels 301. Therefore, the width of the trenches 13 formed using the sidewalls 311 as a mask is smaller than the spacing between the mandrels 301. In this way, even if the lithography process limits the achievable critical dimension, trenches 13 with a smaller critical dimension can be formed by means of the mandrels 301, expanding the process dimension limit that the semiconductor device can achieve.

[0122] In some embodiments of the present application, it can be achieved through S2021 to S2022 Figure 10 S202 shown will be described in conjunction with each step.

[0123] S2021. Form a first mask on the second barrier layer; the first mask includes a first etching pattern extending along the second direction.

[0124] In the embodiments of the present application, the semiconductor device may first form a first mask on the second barrier layer. Among them, the first mask can be obtained through a lithography process. Figure 11A and Figure 11B Illustrates the first mask, which are a top view and a front cross-sectional view respectively. As Figure 11A and Figure 11B shown, a first mask 40 is formed on the second barrier layer 30, and the first etching pattern of the first mask 40 extends along the second direction Y.

[0125] S2022. Etch the second barrier layer along the first etching pattern to form a mandrel extending along the second direction.

[0126] In the embodiments of the present application, after the semiconductor device forms the first mask 40, it can etch the second barrier layer 30 along the first etching pattern to form Figure 12A and Figure 12B the mandrel 301 shown in; the mandrel 301 also extends along the second direction Y.

[0127] In some embodiments of the present application, it can be achieved through S2031 to S2032 Figure 10 S203 shown will be described in conjunction with each step.

[0128] S2031. Deposit a hard mask layer; the hard mask layer covers the first barrier layer and the mandrel.

[0129] In the embodiments of the present application, asFigure 13A And Figure 13B As shown in, the semiconductor device may first deposit a hard mask layer 31 by an ALD process to cover the first barrier layer 20 and the mandrel 301.

[0130] S2032. Etch back the hard mask layer to remove the top of the hard mask layer until the mandrel is exposed, and retain the side portions of the hard mask layer as sidewalls.

[0131] In the embodiment of the present application, after depositing the hard mask layer 31, the semiconductor device may etch back the hard mask layer 31 to remove the top of the hard mask layer 31 until the mandrel 301 is exposed, and retain the side portions of the hard mask layer 31 as sidewalls 311, as Figure 15A And Figure 15B shown.

[0132] In some embodiments of the present application, S204 shown in Figure 10 can be implemented through S2041~S2043, and will be described in conjunction with each step.

[0133] S2041. Remove the mandrel in the middle of the sidewall.

[0134] In the embodiment of the present application, referring to Figure 15A And Figure 15B , there is a remaining mandrel 301 in the middle of the sidewall 311. The semiconductor device may first etch using a high selectivity etching rate to remove the remaining mandrel 301 in the middle of the sidewall 311, and the obtained structure is as Figure 16A And Figure 16B shown.

[0135] S2042. Use the sidewall as a mask to etch the first barrier layer to form a first intermediate structure.

[0136] In the embodiment of the present application, after the semiconductor device removes the remaining mandrel 301 in the middle of the sidewall 311, it can use the sidewall 311 as a mask to etch the first barrier layer 20 to form a first intermediate structure 201 as Figure 17A And 17B shown, and expose the first dielectric wall 11 and the second dielectric wall 12. As Figure 17A shown, the first intermediate structure 201 extends along the second direction Y, and the first dielectric wall 11 and the second dielectric wall 12 are exposed at the gap of the first intermediate structure 201.

[0137] S2043. Use the first intermediate structure as a mask to etch the first dielectric wall and the second dielectric wall according to the etching rate ratio to form a trench.

[0138] In the embodiment of the present application, the semiconductor device forms Figure 17BAfter the first intermediate structure 201 shown, the first dielectric wall 11 and the second dielectric wall 12 can be etched using the first intermediate structure 201 as a mask according to the etching rate ratio to form Figure 3A and Figure 3B the groove 13 shown; within the groove 13, the height of the remaining first dielectric wall 11 is greater than the height of the remaining second dielectric wall 12.

[0139] In some embodiments of the present application, the etching rate ratio described in S2043 includes: the etching rate ratio of the material of the first dielectric wall to the material of the second dielectric wall is 1:4. Correspondingly, etching is performed according to the etching rate ratio of 1:4, and the height of the remaining first dielectric wall 11 within the groove 13 accounts for three-quarters of the depth of the groove 13.

[0140] In some embodiments of the present application, S104 shown can be implemented through Figure 19 S301 - S303 shown Figure 1 and will be described in conjunction with each step.

[0141] S301: Deposit a third barrier layer on the groove.

[0142] In the embodiments of the present application, after the groove is formed, the semiconductor device can deposit a third barrier layer on the groove to cover the groove. Figure 20A and Figure 20B are a top view and a front cross-sectional view respectively. As shown in Figure 20A and Figure 20B , the third barrier layer 50 is deposited on the groove 13 to cover the groove 13.

[0143] S302: Form a second mask on the third barrier layer; the second mask includes second etching patterns arranged at intervals.

[0144] In the embodiments of the present application, continuing to refer to Figure 20A and Figure 20B , the semiconductor device can form a second mask 60 on the third barrier layer 50 through a lithography process. Among them, the second mask 60 includes second etching patterns 601 arranged at intervals.

[0145] In the embodiments of the present application, the second etching pattern 601 is a concave hole on the second mask 60, and this concave hole needs to be aligned with the square hole of the remaining second dielectric wall 12 within the groove 13. In this way, a first contact hole 14 can be formed at the position of the remaining second dielectric wall 12, as shown in Figure 4A .

[0146] S303: Etch along the second etching pattern to remove the third barrier layer and etch the remaining second dielectric wall within the groove to form first contact holes arranged at intervals.

[0147] In the embodiments of the present application, the semiconductor device may perform at least one etching along the second etching pattern to remove the third barrier layer and etch the remaining second dielectric walls in the trench to form spaced-apart first contact holes.

[0148] In the embodiments of the present application, the semiconductor device may first etch the third barrier layer 50 along the second etching pattern 601 to form a second intermediate structure as shown in Figure 21A and Figure 21B ; the second etching pattern 601 is transferred to the second intermediate structure 501. Then, the semiconductor device can use the second intermediate structure 501 as a mask to etch the remaining second dielectric walls 12 in the trench 13 to form first contact holes 14 as shown in Figure 4A shown.

[0149] It should be noted that the third barrier layer 50 may include multiple material layers. The semiconductor device can perform multiple etchings according to different materials and different etching rate ratios to control the recess depth of the second etching pattern 601 on the second intermediate structure 501, and further control the depth of the obtained first contact holes 14. In this way, at the position of the first contact holes 14, the active region 01 can be exposed; while at other positions, the active region 01 is not exposed.

[0150] It can be understood that corresponding to the positions of the remaining second dielectric walls in the trench, spaced-apart first contact holes are etched along the second etching pattern to expose the active region. In this way, only through one photomask, contact points between the metal wiring and the active region are provided.

[0151] In some embodiments of the present application, S303 shown in Figure 19 can be implemented through S3031 to S3032, and will be described in combination with each step.

[0152] S3031: Etch the third barrier layer along the second etching pattern to form a second intermediate structure.

[0153] In the embodiments of the present application, the semiconductor device may first etch the third barrier layer 50 along the second etching pattern 601 to form a second intermediate structure as shown in Figure 21A and Figure 21B shown.

[0154] S3032: Use the second intermediate structure as a mask to etch the remaining second dielectric walls in the trench to form spaced-apart first contact holes.

[0155] In the embodiments of the present application, the semiconductor device can use the second intermediate structure 501 as a mask to etch the remaining second dielectric walls 12 in the trench 13 to form first contact holes 14 as shown in Figure 4A shown.

[0156] In some embodiments of the present application, it can be implemented through Figure 22 S401 - S403 shown in Figure 5 S105 shown in, and it will be described in conjunction with each step.

[0157] S401: Deposit a metal isolation layer in the first contact hole.

[0158] In the embodiments of the present application, referring to Figure 4A , the first contact hole 14 exposes the active region 01, which can serve as the contact point between the metal layer and the active region 01. Before filling the metal layer into the first contact hole, a metal isolation layer needs to be deposited in the first contact hole first. The metal isolation layer partially fills the first contact hole 14 and covers the exposed active region 01. The material of the metal isolation layer can be titanium nitride (TiN), which can prevent the diffusion of metal materials into the active region.

[0159] S402: Deposit a metal layer; the metal layer covers the metal isolation layer and fills the first contact hole and the trench.

[0160] In the embodiments of the present application, after depositing the metal isolation layer, the semiconductor device can deposit a metal layer. Figure 23 For the front - view cross - sectional view, as shown in Figure 23 , the metal layer 70 covers the metal isolation layer and fills the first contact hole 14 (not shown due to occlusion) and the trench 13. Among them, the material of the metal layer 70 can be tungsten (W) or copper (Cu).

[0161] S403: Grind the metal layer until the top of the trench, thereby forming the first conductive layer.

[0162] In the embodiments of the present application, after depositing the metal layer 70, the semiconductor device can grind the metal layer 70 until the top of the trench 13, that is, adopt the damascene process to grind the metal layer 70 to form the first conductive layer 15 as shown in Figure 24A and 24B .

[0163] In the embodiments of the present application, the first conductive layer 15 can be used for the bit - line structure.

[0164] It can be understood that forming the first conductive layer in the trench and contacting the active region through the first contact hole, in this way, a buried bit - line structure is formed, reducing the height of the semiconductor structure, which is beneficial to improving the integration density in the vertical direction.

[0165] In some embodiments of the present application, it can be implemented through Figure 25 S501 - S502 shown in Figure 5 S106 shown in, and it will be described in conjunction with each step.

[0166] S501. Form a first isolation layer on the first conductive layer; the material of the first isolation layer is the same as that of the first dielectric wall.

[0167] In the embodiment of the present application, the semiconductor device may first form a first isolation layer on the first conductive layer, where the material of the first isolation layer is the same as that of the first dielectric wall.

[0168] In the embodiment of the present application, referring to Figure 24B and Figure 26 , the semiconductor device may first etch the first conductive layer 15 at a high selectivity etching rate to reduce the height of the first conductive layer. Here, the high selectivity means that the etching rate of the material of the first conductive layer 15 is much greater than that of other materials.

[0169] Then, as Figure 27 shown, the semiconductor device may deposit a fourth barrier layer 80 on the first conductive layer 15. The fourth barrier layer 80 covers the remaining second dielectric wall 12 outside the trench.

[0170] Then, as Figure 28A and Figure 28B shown, the semiconductor device may grind the fourth barrier layer 80 until the remaining second dielectric wall 12 outside the trench is exposed, and the remaining fourth barrier layer 80 forms the first isolation layer 16.

[0171] S502. Using the first isolation layer and the remaining first dielectric wall outside the trench as a mask, etch the remaining second dielectric wall outside the trench to form a second contact hole.

[0172] In the embodiment of the present application, in combination with Figure 28A , Figure 28B , Figure 29A and Figure 29B , since the material of the first isolation layer 16 is the same as that of the first dielectric wall 11, the semiconductor device can use the first isolation layer 16 and the remaining first dielectric wall 11 outside the trench as a mask to etch the remaining second dielectric wall 12 outside the trench, and form a second contact hole 18 at the position of the second dielectric wall 12. The second contact hole 18 exposes the active region 01.

[0173] It can be understood that using the remaining second dielectric wall outside the trench as a mask, etching to form a second contact hole at its corresponding position, and filling a second conductive layer. In this way, without a mask, the second contact hole is etched and formed using the pattern of the semiconductor structure itself, achieving the purpose of self-alignment; at the same time, the second conductive layer is an embedded structure, reducing the height of the semiconductor structure, which is beneficial to improving the integration degree in the vertical direction.

[0174] In some embodiments of the present application, it can be implemented through S5011 to S5013 Figure 25S501 shown will be described in conjunction with each step.

[0175] S5011. Etch the first conductive layer to reduce its height.

[0176] In the embodiments of the present application, referring to Figure 24B and Figure 26 , the semiconductor device can first etch the first conductive layer 15 at a high selectivity etching rate to reduce the height of the first conductive layer.

[0177] S5012. Deposit a fourth barrier layer on the first conductive layer; the fourth barrier layer covers the remaining second dielectric wall outside the trench.

[0178] In the embodiments of the present application, as Figure 27 shown, the semiconductor device can deposit a fourth barrier layer 80 on the first conductive layer 15. The fourth barrier layer 80 covers the remaining second dielectric wall 12 outside the trench.

[0179] S5013. Grind the fourth barrier layer until the remaining second dielectric wall outside the trench is exposed, and the remaining fourth barrier layer forms the first isolation layer.

[0180] In the embodiments of the present application, as Figure 28A and Figure 28B shown, the semiconductor device can grind the fourth barrier layer 80 until the remaining second dielectric wall 12 outside the trench is exposed, and the remaining fourth barrier layer 80 forms the first isolation layer 16.

[0181] In some embodiments of the present application, S107 shown in Figure 30 can be implemented through S601 - S603 shown in Figure 5 and will be described in conjunction with each step.

[0182] S601. Form a second isolation layer in the second contact hole; the second isolation layer covers the side surface of the first conductive layer.

[0183] In the embodiments of the present application, the semiconductor device can form a second isolation layer in the second contact hole. Figure 31B For the front - view sectional view, as Figure 31B shown, the second isolation layer 17 covers the side surface of the first conductive layer 15. Among them, the material of the second isolation layer 17 is the same as that of the first dielectric wall 11.

[0184] S602. Deposit a conductive medium; the conductive medium fills the second contact hole.

[0185] In the embodiments of the present application, after forming the second isolation layer, the semiconductor device can deposit a conductive medium. Figure 31A and Figure 31B are respectively the top - view and the front - view sectional view. AsFigure 31A and Figure 31B As shown in Figure 31B , the conductive medium 90 fills the second contact hole 18 and covers the first conductive layer 15; the second isolation layer 17 isolates the conductive medium 90 from the first conductive layer 15. Among them, the material of the conductive medium layer 90 can be polysilicon.

[0186] S603, etch the conductive medium with a high selectivity until the height of the conductive medium is lower than the top of the second contact hole, and the remaining conductive medium forms the second conductive layer; the second isolation layer isolates the first conductive layer and the second conductive layer.

[0187] In the embodiments of the present application, Figure 32A and Figure 32B are respectively the top view and the front cross-sectional view. Combining Figure 31A , Figure 31B , Figure 32A , Figure 32B , after depositing the conductive medium 90, the semiconductor device can etch the conductive medium 90 with a high selectivity, that is, the etching rate of the conductive medium 90 is higher than that of other materials; etching like this until the height of the conductive medium 90 is lower than the top of the second contact hole 18, exposing the remaining first dielectric wall 11 and the first isolation layer 16 outside the trench, as shown in Figure 32A . In this way, the remaining conductive medium 90 forms the second conductive layer 19; and the second isolation layer 17 isolates the first conductive layer 15 from the second conductive layer 19. Figure 32A As shown in Figure 32A . In this way, the remaining conductive medium 90 forms the second conductive layer 19; and the second isolation layer 17 isolates the first conductive layer 15 from the second conductive layer 19.

[0188] It can be understood that the same material as the first dielectric wall 11 is selected to form the second isolation layer 17 on the side of the first conductive layer 15. In this way, the appropriate etching selectivity can be selected according to the material characteristics to etch the conductive medium 70, so that the first dielectric wall 11 and the second isolation layer 17 can be retained; at the same time, the second isolation layer 17 isolates the first conductive layer 15 from the second conductive layer 19, avoiding short circuits.

[0189] The embodiments of the present application also provide a semiconductor structure 08, and the semiconductor structure 08 is prepared by the preparation method provided by the foregoing embodiments.

[0190] The embodiments of the present application also provide a semiconductor memory 09. As shown in Figure 33 , the semiconductor memory 09 at least includes the semiconductor structure 08. Figure 33 As shown in Figure 33 , the semiconductor memory 09 at least includes the semiconductor structure 08.

[0191] In some embodiments of the present application, Figure 33 the semiconductor memory 09 shown at least includes a dynamic random access memory DRAM.

[0192] ​​​​​​​​It should be noted that in this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including such element.

[0193] The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments. The methods disclosed in several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0194] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that, The method includes: providing a substrate; an active region is included in the substrate; forming a first dielectric wall and a second dielectric wall extending in a first direction on the substrate; the first dielectric wall and the second dielectric wall are alternately distributed; etching the first dielectric wall and the second dielectric wall to form trenches extending in a second direction; wherein, the trenches are arranged at intervals; in the trenches, the height of the remaining first dielectric wall is greater than the height of the remaining second dielectric wall; etching the remaining second dielectric wall in the trenches to form first contact holes arranged at intervals in the trenches; the first contact holes expose the active region; the material of the first dielectric wall is silicon nitride, the material of the second dielectric wall is silicon oxide, and the height of the remaining first dielectric wall in the trenches accounts for three quarters of the trench depth; wherein, etching the remaining second dielectric wall in the trenches to form first contact holes arranged at intervals in the trenches includes: depositing a third barrier layer on the trenches; forming a second mask on the third barrier layer; the second mask includes second etching patterns arranged at intervals; etching along the second etching patterns to remove the third barrier layer, and etching the remaining second dielectric wall in the trenches to form the first contact holes arranged at intervals; the second etching patterns are concave holes on the second mask, and the concave holes are aligned with the square holes of the remaining second dielectric wall in the trenches.

2. The preparation method according to claim 1, wherein After etching the remaining second dielectric wall in the trenches to form first contact holes arranged at intervals in the trenches, the method further includes: forming a first conductive layer in the trenches; the first conductive layer fills the first contact holes and fills at least part of the trenches; etching the remaining second dielectric wall outside the trenches to form second contact holes; the second contact holes expose the active region; forming a second conductive layer in the second contact holes.

3. The preparation method according to claim 1, wherein The etching the first dielectric wall and the second dielectric wall to form trenches extending in a second direction includes: sequentially depositing a first barrier layer and a second barrier layer on the first dielectric wall and the second dielectric wall; etching the second barrier layer to form mandrels extending in the second direction; the mandrels are arranged at intervals; forming sidewalls covering the sides of the mandrels; etching with the sidewalls as a mask to remove the first barrier layer, and etching the first dielectric wall and the second dielectric wall to form the trenches.

4. The preparation method according to claim 3, characterized in that, The etching the second barrier layer to form mandrels extending in the second direction includes: forming a first mask on the second barrier layer; the first mask includes a first etching pattern extending in the second direction; etching the second barrier layer along the first etching pattern to form the mandrels extending in the second direction.

5. The preparation method according to claim 3, characterized in that, The covering the sides of the mandrels to form sidewalls includes: depositing a hard mask layer; the hard mask layer covers the first barrier layer and the mandrels; performing a back-etch on the hard mask layer to remove the top of the hard mask layer until the mandrels are exposed, and retaining the sides of the hard mask layer as the sidewalls.

6. The preparation method according to claim 3, wherein Etching is performed using the sidewall as a mask to remove the first barrier layer, and the first dielectric wall and the second dielectric wall are etched to form the trench, including: Removing the mandrel in the middle of the sidewall; Using the sidewall as a mask, etching the first barrier layer to form a first intermediate structure; Using the first intermediate structure as a mask, etching the first dielectric wall and the second dielectric wall according to an etching rate ratio to form the trench.

7. The manufacturing method according to claim 6, wherein The etching rate ratio includes: the etching rate ratio of the material of the first dielectric wall to the material of the second dielectric wall is 1:

4.

8. The preparation method according to claim 1, wherein Etching is performed along the second etching pattern to remove the third barrier layer, and the remaining second dielectric wall in the trench is etched to form the first contact holes arranged at intervals, including: Etching the third barrier layer along the second etching pattern to form a second intermediate structure; Using the second intermediate structure as a mask, etching the remaining second dielectric wall in the trench to form the first contact holes arranged at intervals.

9. The preparation method according to claim 2, characterized in that, The first conductive layer includes: a metal isolation layer and a metal layer; forming the first conductive layer in the trench includes: Depositing the metal isolation layer in the first contact hole; Depositing the metal layer; the metal layer covers the metal isolation layer and fills the first contact hole and the trench; Polishing the metal layer until the top of the trench is reached, thereby forming the first conductive layer.

10. The preparation method according to claim 2, wherein Etching the remaining second dielectric wall outside the trench to form the second contact hole, including: Forming a first isolation layer on the first conductive layer; the material of the first isolation layer is the same as the material of the first dielectric wall; Using the first isolation layer and the remaining first dielectric wall outside the trench as masks, etching the remaining second dielectric wall outside the trench to form the second contact hole.

11. The preparation method according to claim 10, wherein Forming the first isolation layer on the first conductive layer includes: Etching the first conductive layer to reduce the height of the first conductive layer; Depositing a fourth barrier layer on the first conductive layer; the fourth barrier layer covers the remaining second dielectric wall outside the trench; Polishing the fourth barrier layer until the remaining second dielectric wall outside the trench is exposed, and the remaining fourth barrier layer forms the first isolation layer.

12. The preparation method according to claim 2, wherein, Forming a second conductive layer in the second contact hole includes: Forming a second isolation layer in the second contact hole; the second isolation layer covers the side surface of the first conductive layer; Depositing a conductive medium; the conductive medium fills the second contact hole; Performing high-selectivity etching on the conductive medium until the height of the conductive medium is lower than the top of the second contact hole, and the remaining conductive medium forms the second conductive layer; the second isolation layer isolates the first conductive layer and the second conductive layer.

13. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the manufacturing method according to any one of claims 1 to 12.

14. A semiconductor memory, characterized in that, Including the semiconductor structure according to claim 13.

15. The semiconductor memory according to claim 14, characterized in that, The semiconductor memory at least includes a dynamic random access memory DRAM.

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