Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a first well region in the substrate, a first body region in the first well region, a second body region in the substrate and spaced from the first body region, and at least partially in the first well region, a second well region in the first well region and between the first body region and the second body region and spaced from the first body region, and a plurality of ohmic contact regions in the substrate, at least part of the ohmic contact regions being in the first body region, the second body region, the first well region and the second well region in a first direction. The second well region and the ohmic contact region in the second well region serve as a drain region of a junction field effect transistor and a collector region of an NPN. The NPN region and the junction field effect transistor region are mutually overlapped, and the NPN and the junction field effect transistor share part of the structure to reduce the area of the overall semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the development of semiconductor technology, the requirement for the integration of semiconductor products is higher and higher, and thus the size of semiconductor devices is required to be smaller and smaller.

[0003] Many semiconductor structures include both NPN (NPN type triode) elements and JFET (Junction Field-Effect Transistor) elements, but in these semiconductor structures, the NPN and JFET are usually manufactured separately, and the NPN region and the JFET region are independent of each other, resulting in a large semiconductor structure area. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof aiming at the above problems.

[0005] To solve the above problems, on one hand, the present application provides a semiconductor structure, comprising:

[0006] a substrate;

[0007] a first well region in the substrate;

[0008] a first body region in the first well region;

[0009] a second body region in the substrate, spaced apart from the first body region, and at least partially in the first well region;

[0010] a second well region in the first well region, and between the first body region and the second body region, spaced apart from the first body region;

[0011] a plurality of ohmic contact regions in the substrate, at least part of the ohmic contact regions being in the first body region, the second body region, the first well region and the second well region in a first direction;

[0012] wherein the second well region and the ohmic contact regions in the second well region serve as a drain region of a junction field-effect transistor and a collector region of an NPN.

[0013] The semiconductor structure of the present application comprises a substrate, a first well region, a first body region, a second body region, a second well region and a plurality of ohmic contact regions; the first well region is located in the substrate and is used to form a parasitic diode together with the substrate; the first body region is located in the first well region and is used as a body region of an NPN; the second body region is located between the first body region and the first well region and is used as a body region of a JFET; the second well region located between the first body region and the second body region and the ohmic contact region located in the second well region are shared by the JFET and the NPN and are used as an anode of the JFET and a collector of the NPN and are also used as a drain of the semiconductor structure, so that the NPN region and the JFET region are overlapped with each other and the NPN and the JFET share part of the structure to reduce the area of the overall structure.

[0014] In one of the embodiments, the semiconductor structure further comprises a plurality of third well regions located in the substrate; wherein, in a second direction, the third well regions are located on opposite sides of the first well region, and the first direction is perpendicular to the second direction.

[0015] In one of the embodiments, in the second direction, the second body region is located in the first well region.

[0016] In one of the embodiments, in the second direction, the plurality of ohmic contact regions are located in the second body region.

[0017] In one of the embodiments, in the second direction, the second body region is partially located in the first well region.

[0018] In one of the embodiments, in the second direction, part of the ohmic contact regions extend into the third well region.

[0019] In one of the embodiments, the ohmic contact regions comprise a plurality of ohmic contact regions of a first conductive type and a plurality of ohmic contact regions of a second conductive type, and the ohmic contact regions of the first conductive type and the ohmic contact regions of the second conductive type are alternately and spacedly arranged.

[0020] In one of the embodiments, in the second direction, ohmic contact regions of a target type extend into the third well region; wherein the target type is one of the first conductive type and the second conductive type.

[0021] In one of the embodiments, the semiconductor structure further comprises a plurality of shallow trench isolation structures spacedly arranged in the substrate, and at least part of the shallow trench isolation structures are located in the first well region and the first body region; wherein the plurality of ohmic contact regions are located between two adjacent shallow trench isolation structures.

[0022] The present application further provides a preparation method of a semiconductor structure, comprising:

[0023] providing a substrate;

[0024] forming a first well region in the substrate;

[0025] forming a first body region in the first well region;

[0026] forming a second body region in the substrate, the second body region being spaced apart from the first body region and at least partially located in the first well region;

[0027] forming a second well region in the first well region, the second well region being located between the first body region and the second body region and being spaced apart from the first body region;

[0028] forming a plurality of ohmic contact regions in the substrate, at least part of the ohmic contact regions being located in the first body region, the second body region, the first well region and the second well region in a first direction;

[0029] wherein the second well region and the ohmic contact region located in the second well region serve as a drain region of a junction field effect transistor (JFET) and a collector region of an NPN.

[0030] In the method for manufacturing the semiconductor structure, the first well region is formed in the substrate, the first well region and the substrate together form a parasitic diode; the first body region is formed in the first well region, the first body region serves as a body region of the NPN; the second body region is formed in the substrate, the second body region is spaced apart from the first body region and at least partially located in the first well region, and serves as a body region of the JFET; the second well region is formed in the first well region, the second well region located between the first body region and the second body region and the ohmic contact region located in the second well region are shared by the JFET and the NPN, serving as a drain of the JFET and a collector lead-out end of the NPN, and also serving as a drain of the semiconductor structure, so that the NPN region and the JFET region are mutually overlapped, and the NPN and the JFET share part of the structure to reduce the area of the overall structure. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0032] Figure 1 a schematic view of a cross section structure of the semiconductor structure provided in an embodiment in a first direction;

[0033] Figure 2A layout view of a semiconductor structure provided in an embodiment;

[0034] Figure 3 A cross-sectional view of a semiconductor structure provided in an embodiment in a second direction;

[0035] Figure 4 A layout view of a semiconductor structure provided in another embodiment;

[0036] Figure 5 A cross-sectional view of a semiconductor structure provided in another embodiment in a second direction;

[0037] Figure 6 A cross-sectional view of a semiconductor structure provided in another embodiment in a first direction;

[0038] Figure 7 A cross-sectional view of a semiconductor structure provided in another embodiment in a first direction;

[0039] Figure 8 A flow chart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0040] Figure 9 A cross-sectional view of a structure obtained in step S105 of a method for manufacturing a semiconductor structure provided in an embodiment.

[0041] BRIEF DESCRIPTION OF DRAWINGS

[0042] 1 - substrate; 2 - first well region; 3 - first body region; 4 - second body region; 5 - second well region; 6 - fourth well region; 7 - shallow trench isolation structure; 81 - ohmic contact region of first conductivity type; 82 - ohmic contact region of second conductivity type; 9 - third well region; 10 - passivation layer; 11 - interconnection structure; 12 - electrode layer. DETAILED DESCRIPTION

[0043] In order to facilitate the understanding of the present application, a more complete understanding of the present application can be had by reference to the following description in conjunction with the associated drawings. The preferred embodiments of the present application are illustrated in the attached drawings. However, the present application can be realized in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It will be apparent, however, to one of ordinary skill in the art that the present application can be realized in other forms.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0045] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0047] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] like Figure 1 As shown, this application provides a semiconductor structure including: a substrate 1, a first well region 2, a first body region 3, a second body region 4, a second well region 5, and a plurality of ohmic contact regions; the first well region 2 is located within the substrate 1; the first body region 3 is located within the first well region 2; the second body region 4 is located within the substrate 1, spaced apart from the first body region 3, and at least partially located within the first well region 2; the second well region 5 is located within the first well region 2, and is located between the first body region 3 and the second body region 4, spaced apart from the first body region 3; the plurality of ohmic contact regions are located within the substrate 1, and in a first direction, at least a portion of the ohmic contact regions are located within the first body region 3, the second body region 4, the first well region 2, and the second well region 5; wherein, the second well region 4 and the ohmic contact regions located within the second well region 4 serve as the drain region of a JFET (Junction Field-Effect Transistor) and the collector region of an NPN.

[0049] wherein reference can be made to Figure 2 and Figure 4 the semiconductor structure layout shown in FIG. 1, X is the first direction and Y is the second direction. Figure 1 FIG. 2 is a schematic cross-sectional view of a semiconductor structure in the first direction according to one embodiment. The substrate 1 can comprise a silicon substrate 1. Further, the substrate 1 can be a doped silicon substrate 1 of a first conductivity type. The first well region 2 can comprise a well region of a second conductivity type. Further, the first well region 2 can be a high-voltage well region of the second conductivity type. The first body region 3 and the second body region 4 can each comprise a well region of the first conductivity type. Further, in the first direction, the first body region 3 has a larger area than the second body region 4. The second well region 5 can comprise a well region of the second conductivity type. Further, the second well region 5 can be a low-voltage well region of the second conductivity type. The second body region 4 is at least partially located within the first well region 2, which means that the second body region 4 is entirely located within the first well region 2 or the second body region 4 is partially located within the first well region 2.

[0050] Still referring to Figure 1 , the at least partially ohmic contact region is located within the first body region 3, the second body region 4, the first well region 2 and the second well region 5. It can be understood that there can be a portion of the ohmic contact region located within the first body region 3, the second body region 4, the first well region 2 and the second well region 5 and another portion located within the substrate 1 outside the first body region 3, the second body region 4, the first well region 2 and the second well region 5; or the ohmic contact region can be entirely located within the first body region 3, the second body region 4, the first well region 2 and the second well region 5. The ohmic contact region comprises a plurality of ohmic contact regions 81 of the first conductivity type and a plurality of ohmic contact regions 82 of the second conductivity type, the ohmic contact regions 81 of the first conductivity type and the ohmic contact regions 82 of the second conductivity type being alternately and spacedly arranged. In the first direction, the ohmic contact region located within the first body region 3 comprises two ohmic contact regions 81 of the first conductivity type and one ohmic contact region 82 of the second conductivity type, the two ohmic contact regions 81 of the first conductivity type being located on opposite sides of the ohmic contact region 82 of the second conductivity type and having a spacing with the ohmic contact region 82 of the second conductivity type.

[0051] For example, the first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type. In the present embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

[0052] The semiconductor structure in the above embodiment comprises a substrate 1, a first well region 2, a first body region 3, a second body region 4, a second well region 5, and a plurality of ohmic contact regions; the first well region 2 is located in the substrate 1 and is used to form a parasitic diode together with the substrate 1; the first body region 3 is located in the first well region 2 and is used as a body region of an NPN; the second body region 4 is located apart from the first body region 3 and at least partially in the first well region 2 and is used as a body region of a JFET; the second well region 5 located between the first body region 3 and the second body region 4 and the ohmic contact region located in the second well region 5 are shared by the JFET and the NPN and are used as an anode of the JFET and a collector of the NPN and also as an anode of the semiconductor structure, so that the NPN region and the JFET region overlap each other and the NPN and the JFET share part of the structure to reduce the area of the overall structure.

[0053] In some examples, the doping concentration of the second-conductivity-type ions in the first well region 2 is less than the doping concentration of the second-conductivity-type ions in the second-conductivity-type ohmic contact region 82; the doping concentration of the second-conductivity-type ions in the second well region 5 is less than the doping concentration of the second-conductivity-type ions in the second-conductivity-type ohmic contact region 82; the doping concentration of the first-conductivity-type ions in the first body region 3 is less than the doping concentration of the first-conductivity-type ions in the first-conductivity-type ohmic contact region 81; and the doping concentration of the first-conductivity-type ions in the second body region 4 is less than the doping concentration of the first-conductivity-type ions in the first-conductivity-type ohmic contact region 81.

[0054] In one embodiment, referring to Figure 2 to Figure 3 , Figure 3 is a sectional view of the semiconductor structure in the second direction in one embodiment, in the second direction, the second body region 4 is located in the first well region 2, and the first direction is perpendicular to the second direction.

[0055] In the above embodiment, the second body region 4 is used as the body region of the JFET, and the second body region 4 is entirely located in the first well region 2, which is suitable for the case where the JFET requires a high on-voltage.

[0056] In one embodiment, referring to Figure 3 , the semiconductor structure further comprises a plurality of third well regions 9, and the third well regions 9 are located in the substrate 1; in the second direction, the third well regions 9 are located on opposite sides of the first well region 2.

[0057] In the above embodiment, the third well regions 9 can comprise first-conductivity-type well regions; further, the third well regions 9 can be first-conductivity-type low-voltage well regions.

[0058] In one embodiment, referring to Figure 3 , in the second direction, the plurality of ohmic contact regions are all located in the second body region 4.

[0059] In the second direction, the ohmic contact region located in the second body region 4 includes two ohmic contact regions 81 of the first conductive type and one ohmic contact region 82 of the second conductive type, the two ohmic contact regions 81 of the first conductive type are located on opposite sides of the ohmic contact region 82 of the second conductive type and have a spacing with the ohmic contact region 82 of the second conductive type.

[0060] For example, still referring to Figure 3 In each third well region 9, the ohmic contact region 82 of the second conductive type is also correspondingly arranged.

[0061] In other embodiments, referring to Figure 4 to Figure 5 , Figure 4 X shown in the figure is the first direction, Y is the second direction, Figure 5 is a cross-sectional view of the semiconductor structure in the second direction in an embodiment, in the second direction, the second body region 4 is partially located in the first well region 2.

[0062] In the second body region 4, the second body region 4 is not entirely located in the first well region 2, which is suitable for the case that the JFET requires a low opening voltage, the second body region 4 serves as the body region of the JFET, and the second body region 4 can extend to the end of the substrate 1, the pinch-off voltage of the JFET can be made lower, and the voltage applied to the second body region 4 is also present at the end of the substrate 1, which is equivalent to the second body region 4 and the substrate 1 simultaneously pinching off the first well region 2, so that the opening voltage of the semiconductor structure can be lower.

[0063] In an embodiment, still referring to Figure 5 In the second direction, part of the ohmic contact region extends into the third well region 9.

[0064] In an embodiment, still referring to Figure 5 In the second direction, the ohmic contact region of the target type extends into the third well region 9; wherein the target type is one of the first conductive type and the second conductive type. In this embodiment, the target type is the first conductive type.

[0065] In an embodiment, as Figure 6 shown, Figure 6 is a cross-sectional view of the semiconductor structure in the first direction in an embodiment, the semiconductor structure can further include: a fourth well region 6, wherein in the first direction, the second well region 5 and the fourth well region 6 are located on opposite sides of the first body region 3.

[0066] Further, the ohmic contact region located in the fourth well region 6 can be the ohmic contact region 82 of the second conductive type.

[0067] In an embodiment, still referring to Figure 6The semiconductor structure can further include: a plurality of shallow trench isolation structures 7; the plurality of shallow trench isolation structures 7 are arranged in the substrate 1 in a spaced manner, and at least part of the plurality of shallow trench isolation structures 7 are located in the first well region 2 and the first body region 3; wherein the plurality of ohmic contact regions are located between two adjacent shallow trench isolation structures 7.

[0068] In one embodiment, referring to Figure 7 , Figure 7 Fig. 1 is a schematic cross-sectional view of a semiconductor structure in a first direction according to an embodiment. The semiconductor structure can further include: a passivation layer 10, an interconnection structure 11, and an electrode layer 12; wherein the passivation layer 10 is located on an upper surface of the substrate 1; the interconnection structure 11 is located in the passivation layer 10 and penetrates the passivation layer 10, and is in contact with the ohmic contact region; the electrode layer 12 is located on an upper surface of the passivation layer 10 and is in contact with the interconnection structure 11. The electrode layer 12 is in conductive connection with the ohmic contact region through the interconnection structure 11.

[0069] For example, the passivation layer 10 includes a silicon nitride layer; and the electrode layer 12 includes a metal layer.

[0070] The present application also provides a method for manufacturing a semiconductor structure, as shown in Figure 8 The method for manufacturing a semiconductor structure can include the following steps S101 to S106:

[0071] S101: providing a substrate 1.

[0072] As shown in Figure 9 The substrate 1 can include a silicon substrate 1; further, the substrate 1 can be a doped silicon substrate 1 of a first conductivity type.

[0073] S102: forming a first well region 2 in the substrate 1.

[0074] As shown in Figure 9 The substrate 1 can be doped by a doping process to form the first well region 2 in the substrate 1; the first well region 2 can include a well region of a second conductivity type; further, the first well region 2 can be a high-voltage well region of the second conductivity type.

[0075] For example, the first conductivity type can be N-type, and the second conductivity type can be P-type; or, the first conductivity type can be P-type, and the second conductivity type can be N-type. In the present embodiment, the first conductivity type is P-type, and the second conductivity type is N-type.

[0076] In some examples, after the first well region 2 is formed in the substrate 1, the substrate 1 can be subjected to a heat treatment to expand the area of the first well region 2.

[0077] S103: forming a first body region 3 in the first well region 2.

[0078] The resultant structure is still referred to as Figure 9 The substrate 1 can be doped by a doping process to form the first body region 3 in the first well region 2. The first body region 3 can comprise a well region of the first conductivity type.

[0079] In some examples, after the first body region 3 is formed in the first well region 2, the substrate 1 can be subjected to a thermal treatment to expand the area of the first body region 3. The time for the thermal treatment of the substrate 1 after the first body region 3 is formed in the first well region 2 is less than the time for the thermal treatment of the substrate 1 after the first well region 2 is formed in the substrate 1.

[0080] S104: Form a second body region 4 in the substrate 1, the second body region 4 is spaced apart from the first body region 3 and at least partially located in the first well region 2.

[0081] The resultant structure is still referred to as Figure 9 The substrate 1 can be doped by a doping process to form the second body region 4 in the substrate 1. The second body region 4 can comprise a well region of the first conductivity type. Further, in the first direction, the area of the first body region 3 is greater than the area of the second body region 4.

[0082] The second body region 4 being at least partially located in the first well region 2 means that the second body region 4 is entirely located in the first well region 2 or the second body region 4 is partially located in the first well region 2.

[0083] In some examples, after the second body region 4 is formed in the substrate 1, the substrate 1 can be subjected to a thermal treatment to expand the area of the second body region 4. The time for the thermal treatment of the substrate 1 after the second body region 4 is formed in the substrate 1 is less than the time for the thermal treatment of the substrate 1 after the first well region 2 is formed in the substrate 1.

[0084] It should be noted that the second body region 4 can be formed at the same time as the first body region 3 to save the process.

[0085] S105: Form a second well region 5 in the substrate 1, the second well region 5 is located between the first body region 3 and the second body region 4 and spaced apart from the first body region 3.

[0086] The resultant structure is still referred to as Figure 9 The second well region 5 can comprise a well region of the second conductivity type. Further, the second well region 5 can be a low-voltage well region of the second conductivity type.

[0087] S106: Forming a plurality of ohmic contact regions in the substrate 1, in the first direction, at least part of the ohmic contact regions are located in the first body region 3, the second body region 4, the first well region 2 and the second well region 5; wherein the second well region 4 and the ohmic contact regions located in the second well region 4 serve as the drain region of the junction field effect transistor and the collector region of the NPN.

[0088] As shown in FIG. 1, at least part of the ohmic contact regions are located in the first body region 3, the second body region 4, the first well region 2 and the second well region 5, which can be understood as that part of the ohmic contact regions are located in the first body region 3, the second body region 4, the first well region 2 and the second well region 5, and the other part are located in the substrate 1 outside the first body region 3, the second body region 4, the first well region 2 and the second well region 5; or the ohmic contact regions can be all located in the first body region 3, the second body region 4, the first well region 2 and the second well region 5. Figure 1 As shown in FIG. 1, at least part of the ohmic contact regions are located in the first body region 3, the second body region 4, the first well region 2 and the second well region 5, which can be understood as that part of the ohmic contact regions are located in the first body region 3, the second body region 4, the first well region 2 and the second well region 5, and the other part are located in the substrate 1 outside the first body region 3, the second body region 4, the first well region 2 and the second well region 5; or the ohmic contact regions can be all located in the first body region 3, the second body region 4, the first well region 2 and the second well region 5.

[0089] As shown in FIG. 1, the ohmic contact regions include a plurality of first-conductivity-type ohmic contact regions 81 and a plurality of second-conductivity-type ohmic contact regions 82, the first-conductivity-type ohmic contact regions 81 and the second-conductivity-type ohmic contact regions 82 are alternately and spacedly arranged.

[0090] As shown in FIG. 1, in the first direction, the ohmic contact regions located in the first body region 3 include two first-conductivity-type ohmic contact regions 81 and one second-conductivity-type ohmic contact region 82, the two first-conductivity-type ohmic contact regions 81 are located on the opposite sides of the second-conductivity-type ohmic contact region 82 and have a spacing with the second-conductivity-type ohmic contact region 82.

[0091] The semiconductor structure obtained after the steps S101-S106 can refer to Figure 1 . Of course, in order to facilitate the understanding of the present application, Figure 1 an example of the semiconductor structure prepared by the preparation method of the semiconductor structure of the present application is given, and the semiconductor structure prepared by the preparation method of the semiconductor structure of the present application can also have other suitable examples, which are not limited herein.

[0092] The semiconductor structure in the above embodiment is prepared by forming the first well region 2 in the substrate 1, the first well region 2 and the substrate 1 together forming a parasitic diode; forming the first body region 3 in the first well region 2, the first body region 3 serving as a body region of the NPN; forming the second body region 4 in the substrate 1, the second body region 4 being spaced apart from the first body region 3 and at least partially located in the first well region 2, serving as a body region of the JFET; forming the second well region 5 in the first well region 2, the second well region 5 located between the first body region 3 and the second body region 4 and the ohmic contact region located in the second well region 5 being shared by the JFET and the NPN, serving as a drain of the JFET and a collector terminal of the NPN, and also serving as a drain of the semiconductor structure, so that the NPN region and the JFET region overlap each other, and the NPN and the JFET share part of the structure to reduce the area of the overall structure.

[0093] In some examples, the doping concentration of the second-conductivity-type ions in the first well region 2 is less than the doping concentration of the second-conductivity-type ions in the second-conductivity-type ohmic contact region 82; the doping concentration of the second-conductivity-type ions in the second well region 5 is less than the doping concentration of the second-conductivity-type ions in the second-conductivity-type ohmic contact region 82; the doping concentration of the first-conductivity-type ions in the first body region 3 is less than the doping concentration of the first-conductivity-type ions in the first-conductivity-type ohmic contact region 81; and the doping concentration of the first-conductivity-type ions in the second body region 4 is less than the doping concentration of the first-conductivity-type ions in the first-conductivity-type ohmic contact region 81.

[0094] In one embodiment, referring to Figure 2 to Figure 3 In the second direction, the second body region 4 is located in the first well region 2, and the first direction is perpendicular to the second direction.

[0095] In the second direction, the second body region 4 is located in the first well region 2, and the first direction is perpendicular to the second direction.

[0096] In the embodiment, the step of forming the second well region 5 in the substrate 1 further includes: forming a plurality of third well regions 9 in the substrate 1; and in the second direction, the third well regions 9 are located on opposite sides of the first well region 2.

[0097] In the second direction, the second body region 4 is located in the first well region 2, and the first direction is perpendicular to the second direction. Figure 3 The third well regions 9 can include first-conductivity-type well regions; further, the third well regions 9 can be first-conductivity-type low-voltage well regions.

[0098] In one embodiment, still referring to Figure 3 In the second direction, the plurality of ohmic contact regions are all located in the second body region 4.

[0099] In the second direction, the ohmic contact regions located in the second body region 4 include two ohmic contact regions 81 of the first conductivity type and one ohmic contact region 82 of the second conductivity type, the two ohmic contact regions 81 of the first conductivity type are located on opposite sides of the ohmic contact region 82 of the second conductivity type and have a spacing from the ohmic contact region 82 of the second conductivity type.

[0100] For example, still referring to Figure 3 In each third well region 9, an ohmic contact region 82 of the second conductivity type is also correspondingly arranged.

[0101] In other embodiments, referring to Figure 4 to Figure 5 In the second direction, the second body region 4 is partially located in the first well region 2.

[0102] In the second direction, the second body region 4 is partially located in the first well region 2.

[0103] In the second direction, the second body region 4 is partially located in the first well region 2.

[0104] In the second direction, the second body region 4 is partially located in the first well region 2. Figure 5 The third well region 9 can include a well region of the first conductivity type; further, the third well region 9 can be a low-voltage well region of the first conductivity type.

[0105] In one embodiment, still referring to Figure 5 In the second direction, part of the ohmic contact regions extend into the third well region 9.

[0106] In one embodiment, referring to Figure 5 In the second direction, the ohmic contact region of the target type extends into the third well region 9; wherein the target type is one of the first conductivity type and the second conductivity type. In this embodiment, the target type is the first conductivity type.

[0107] In one embodiment, in combination with Figure 9 and referring to Figure 6 In the first direction, the second well region 5 and the fourth well region 6 are located on opposite sides of the first body region 3.

[0108] In one embodiment, in combination withFigure 9 Referring to Figure 6 After forming the second well region 5 in the substrate 1, before forming the plurality of ohmic contact regions in the substrate 1, the method for preparing the semiconductor structure further comprises: a step of forming a plurality of shallow trench isolation structures 7 in the substrate 1; wherein at least part of the shallow trench isolation structures 7 are located in the first well region 2 and the first body region 3; the plurality of ohmic contact regions are located between two adjacent shallow trench isolation structures 7.

[0109] In one embodiment, the method for preparing the semiconductor structure further comprises: forming a passivation layer 10 on the upper surface of the substrate 1; etching the passivation layer 10 to form a plurality of spaced-apart contact holes in the passivation layer 10, the contact holes penetrating through the passivation layer 10 and exposing part of the upper surface of the ohmic contact regions; filling an interconnection material in the contact holes to form an interconnection structure 11; forming an electrode layer 12 on the upper surface of the passivation layer 10. The resulting structure can refer to Figure 7 Wherein the electrode layer 12 is electrically connected with the ohmic contact regions through the interconnection structure 11.

[0110] Wherein the passivation layer 10 can be formed on the upper surface of the substrate 1 by a chemical vapor deposition process or an atomic layer deposition process; the passivation layer 10 comprises a silicon nitride layer. The interconnection material can be filled in the contact holes by a damascene process to form the interconnection structure 11; the interconnection material comprises tungsten. The electrode layer 12 can be formed on the upper surface of the passivation layer 10 by a physical vapor deposition process or an atomic layer deposition process; the electrode layer 12 comprises a metal layer.

[0111] Wherein after forming the passivation layer 10 on the upper surface of the substrate 1, the upper surface of the passivation layer 10 needs to be subjected to chemical mechanical polishing to make the upper surface of the passivation layer 10 flat, so as to facilitate the deposition of the metal layer on the upper surface of the passivation layer 10.

[0112] It should be understood that although each step in the flowchart of each embodiment is shown in sequence according to the direction of the arrow, these steps are not necessarily executed in sequence according to the direction of the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart of each embodiment can comprise multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0113] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as there is no conflict, any combination of the technical features should be considered within the scope of the present disclosure.

[0114] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a first well region in the substrate; a first body region in the first well region; a second body region in the substrate, spaced apart from the first body region, and at least partially in the first well region; a second well region in the first well region, and between the first body region and the second body region, spaced apart from the first body region; a plurality of ohmic contact regions in the substrate, at least some of the ohmic contact regions being in the first body region, the second body region, the first well region and the second well region in a first direction; the ohmic contact regions comprise a plurality of first-conductivity-type ohmic contact regions and a plurality of second-conductivity-type ohmic contact regions, the first-conductivity-type ohmic contact regions and the second-conductivity-type ohmic contact regions being alternately spaced apart; wherein the second well region and the ohmic contact regions in the second well region serve as a drain region of a junction field effect transistor and a collector region of an NPN-type transistor.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a plurality of third well regions in the substrate; wherein the third well regions are on opposite sides of the first well region in a second direction, the first direction being perpendicular to the second direction.

3. The semiconductor structure of claim 2, wherein, In the second direction, the second body region is in the first well region.

4. The semiconductor structure of claim 3, wherein, In the second direction, all of the ohmic contact regions are in the second body region.

5. The semiconductor structure of claim 2, wherein, In the second direction, the second body region is partially in the first well region.

6. The semiconductor structure of claim 5, wherein, In the second direction, some of the ohmic contact regions extend into the third well region.

7. The semiconductor structure of claim 6, wherein, In the second direction, ohmic contact regions of a target type extend into the third well region; wherein the target type is one of the first conductivity type and the second conductivity type.

8. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a plurality of shallow trench isolation structures spaced apart in the substrate, and at least some of the shallow trench isolation structures being in the first well region and the first body region; wherein the ohmic contact regions are between two adjacent shallow trench isolation structures.

9. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure comprises: providing a substrate; forming a first well region in the substrate; forming a first body region in the first well region; forming a second body region in the substrate, the second body region being spaced apart from the first body region, and at least partially in the first well region; forming a second well region in the first well region, the second well region being between the first body region and the second body region, and spaced apart from the first body region; forming a plurality of ohmic contact regions in the substrate, at least some of the ohmic contact regions being in the first body region, the second body region, the first well region and the second well region in a first direction; the ohmic contact regions comprise a plurality of first-conductivity-type ohmic contact regions and a plurality of second-conductivity-type ohmic contact regions, the first-conductivity-type ohmic contact regions and the second-conductivity-type ohmic contact regions being alternately spaced apart; wherein the second well region and the ohmic contact regions in the second well region serve as a drain region of a junction field effect transistor and a collector region of an NPN-type transistor.

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