Vertical two-dimensional complementary field-effect devices and their manufacturing methods

Abstract

This invention provides a vertical two-dimensional complementary field-effect device and its manufacturing method. The complementary field-effect device includes a substrate and field-effect cells. Each field-effect cell includes at least two symmetrically arranged field-effect sub-cells. Each field-effect sub-cell includes a P-type field-effect transistor and an N-type field-effect transistor spaced apart. Both the P-type and N-type field-effect transistors include a source, a gate, and a drain. A first insulating material is filled between the P-type and N-type field-effect transistors to achieve mutual isolation. The manufacturing method involves setting a first forming mask and a first etching mask. Before filling the gap between the P-type and N-type field-effect transistors, the first etching mask preserves the two ends of the vertical two-dimensional complementary field-effect device prototype to form a tensioned skeleton structure, preventing lateral collapse and ensuring the quality and yield of the vertical two-dimensional complementary field-effect device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device and manufacturing technology, and in particular to a vertical two-dimensional complementary field-effect device and its manufacturing method. Background Technology

[0002] Complementary field-effect devices (i.e., CMOS field-effect devices) include two types of transistors: NMOS and PMOS. CMOS integrated circuits use field-effect transistors, and they are all complementary structures. When working, the two field-effect transistors connected in series are always in a state where one transistor is on and the other is off. Theoretically, the static power consumption of the circuit is zero. In reality, due to leakage current, CMOS circuits still have a small amount of static power consumption.

[0003] Traditional complementary field-effect devices are horizontally mounted on a substrate, meaning that the source, gate, and drain of the field-effect device are all horizontally laid on the silicon substrate. They have mature manufacturing processes for production. During the manufacturing process, due to the large area of ​​support provided by the silicon substrate, the device height is small, resulting in good structural stability and preventing instability and deformation that could affect quality and yield.

[0004] However, the laying process results in occupying a large area of ​​the silicon substrate (base), which reduces the number and density of distributions per unit area, thereby affecting the integration of semiconductors and hindering miniaturization. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention provides a vertical two-dimensional complementary field-effect device, comprising a substrate and a field-effect unit. The field-effect unit includes at least two symmetrically arranged field-effect sub-units. Each field-effect sub-unit includes a P-type field-effect transistor and an N-type field-effect transistor spaced apart. Both the P-type and N-type field-effect transistors include a source, a gate, and a drain. A first insulating material is filled between the P-type and N-type field-effect transistors to achieve mutual isolation.

[0006] Optionally, the substrate includes a protrusion, and the P-type field-effect transistor and the N-type field-effect transistor are connected to the protrusion in a direction perpendicular to the substrate.

[0007] Optionally, the source, gate, and drain of the P-type field-effect transistor are arranged vertically in a first vertical plane perpendicular to the substrate, and the source, gate, and drain of the N-type field-effect transistor are arranged vertically in a second vertical plane perpendicular to the substrate. The upper part of the first vertical plane and the second vertical plane is the source or drain, the lower part of the first vertical plane and the second vertical plane is the drain or source, and the middle part of the first vertical plane and the second vertical plane is the gate.

[0008] Optionally, a connection structure is provided between the P-type field-effect transistor and the protrusion; a connection structure is provided between the N-type field-effect transistor and the protrusion.

[0009] Optionally, the connection structure includes cobalt silicide material.

[0010] Optionally, a titanium nitride structure layer is disposed between the N-type field-effect transistors in two adjacent field-effect sub-units.

[0011] Optionally, the N-type field-effect transistor is connected to the titanium nitride structural layer through the connection structure.

[0012] Optionally, a fracture groove is provided between the N-type field-effect transistors in two adjacent field-effect sub-units, and the titanium nitride structural layer extends to the sidewall of the fracture groove.

[0013] Optionally, the gate of the P-type field-effect transistor and the gate of the N-type field-effect transistor are electrically connected.

[0014] Optionally, the spacing between adjacent field-effect sub-units is a first spacing, and the spacing between the P-type field-effect transistor and the N-type field-effect transistor is a second spacing, wherein the first spacing is greater than the second spacing.

[0015] This invention also provides a method for manufacturing a vertical two-dimensional complementary field-effect device, comprising the following steps:

[0016] S10: A first forming mask is set on the substrate, and a first etching mask intersecting with the first forming mask is set at intervals on the substrate surface according to a set distance; the substrate is etched for the first time to form a first groove of a first depth between the P-type field-effect transistor prototype and the N-type field-effect transistor prototype in the same field-effect sub-unit, and a second groove of a second depth is formed on the outside of the P-type field-effect transistor prototype and the N-type field-effect transistor prototype to form a field-effect unit prototype;

[0017] S20 Removes the first forming mask and the first etching mask, performs doping treatment, fills the first groove and the second groove with the second insulating material and performs a flattening treatment; restores the first forming mask and the first etching mask, performs a second etching, and retains the second insulating material layer in the first groove and the second groove except for the root of the P-type field-effect transistor prototype and the N-type field-effect transistor prototype.

[0018] S30 fills the grooves between adjacent sub-units and between the P-type field-effect transistor prototype and the N-type field-effect transistor prototype with a first insulating material and performs a leveling process.

[0019] S40 removes the first forming mask and the first etching mask again, sets the second etching mask in the area outside the first etching mask, performs a third etching to form a third groove of the third depth, and then performs a post-processing process to form the source, gate and drain of the P-type field-effect transistor and the N-type field-effect transistor.

[0020] Optionally, in step S20, the doping process can be performed as follows:

[0021] S21 sets a first mask for two N-type field-effect transistor prototypes in the same field-effect sub-unit and the second groove between them. The P-type field-effect transistor prototype is vertically divided into three height segments along the first depth and doped with different densities. The doping density of the upper height segment and the lower height segment is higher than that of the middle height segment. The middle height segment forms the gate prototype, and the upper height segment and the lower height segment form the source prototype or the drain prototype, respectively.

[0022] S23 removes the first mask, sets a second mask on the two P-type field-effect transistor prototypes of the same field-effect sub-unit and the second groove on their outer sides, and divides the N-type field-effect transistor prototypes vertically into three height segments along the first depth for doping treatment with different densities. The doping density of the upper height segment and the lower height segment is higher than that of the middle height segment. The middle height segment forms the gate prototype, and the upper height segment and the lower height segment form the source prototype or the drain prototype, respectively.

[0023] Optionally, in step S10, the width of the first forming mask is the same as the thickness of the P-type and N-type field-effect transistors.

[0024] Optionally, in step S10, the first depth is less than the second depth, and the height difference between the two forms a protrusion of the base.

[0025] Optionally, in step S20, after retaining the second insulating material layer at the first and second grooves (excluding the roots of the P-type and N-type field-effect transistor prototypes), a conductor material infiltration process is performed at the roots of the P-type and N-type field-effect transistor prototypes to form a connection structure between the P-type field-effect transistor and the protrusion, and a connection structure is formed between the N-type field-effect transistor and the protrusion.

[0026] Optionally, in step S20, the conductor material is cobalt metal, and the connection structure includes cobalt silicide.

[0027] Optionally, in step S30, a titanium nitride structure layer is provided between the roots of two N-type field-effect transistor prototypes in the same field-effect unit for connection.

[0028] Optionally, the N-type field-effect transistor is connected to the titanium nitride structural layer through the connection structure.

[0029] Optionally, in step S40, a fracture groove is formed by cutting at the midpoint between the two N-type field-effect transistors, and the fracture groove disconnects the titanium nitride structural layer connection between the roots of the two N-type field-effect transistor prototypes.

[0030] Optionally, in step S10, the first forming mask is configured as follows:

[0031] S1 forms multiple spaced strip-shaped polymer layers by dry photolithography on the surface of a silicon substrate with a polymer layer formed by interspersed strip-shaped protective layers.

[0032] S2 fills the first insulating material into the groove of the dry photolithography and flattens it, then performs the first sidewall etching to form the first insulating material layer on both sides of the strip polymer layer;

[0033] S3 fills the grooves etched in the sidewalls with carbon and polishes them smooth.

[0034] S4 removes the strip-shaped polymer layer, fills the second insulating material, and performs a second sidewall etching to form the second insulating layer on the side of the first insulating material layer away from the filled carbon.

[0035] S5 removes the first insulating material layer and carbon, and the remaining second insulating material layer is the first forming mask.

[0036] Optionally, in step S40, the post-processing includes:

[0037] S41 fills the third groove with the first insulating material and performs a flattening process. A third mask is set at the second groove between the two N-type field-effect transistor prototypes. A fourth etching is performed to remove the first insulating material and form a fourth groove with a fourth depth, which includes an upper height section, a middle height section and a lower height section.

[0038] S43 After filling the fourth groove with the first insulating material and leveling it, a fifth etching is performed to remove the first insulating material and form a fifth groove with a fifth depth, which includes an upper height section and a middle height section.

[0039] S45 After filling the fifth groove with the second insulating material and leveling it, a sixth etching is performed to remove the second insulating material to form a sixth groove with a sixth depth, the sixth depth including the upper height section; a first insulating material film layer is provided on the sidewall of the sixth groove;

[0040] S47 forms a door groove by etching the middle height section of the sixth groove, oxidizes the sidewall of the door groove to form a second insulating material layer, and fills the door groove with metal to form a metal layer.

[0041] S49 uses the first insulating material to fill the sixth groove.

[0042] Optionally, in step S41, before filling the third groove with the first insulating material, the third groove is oxidized to form a second insulating material film.

[0043] The present invention relates to a vertical two-dimensional complementary field-effect device and its manufacturing method. During manufacturing, a first forming mask is formed on the substrate surface according to the sub-unit spacing between field-effect sub-units and the wafer pitch between the P-type and N-type field-effect transistors within the same field-effect sub-unit. The width of the first forming mask is the same as the thickness of the P-type and N-type field-effect transistors. First etching masks, intersecting the first forming mask, are then interposed at intervals on the substrate surface according to a predetermined distance. The substrate is then etched for the first time. Due to the differences in sub-unit spacing and wafer pitch, the P-type field-effect transistor prototype and the N-type field-effect transistor within the same field-effect sub-unit are etched. A first groove of a first depth is formed between the prototype transistors. A second groove of a second depth is formed on the outer side of the prototype P-type and prototype N-type field-effect transistors, forming a prototype field-effect cell. The first depth is less than the second depth, and the height difference between the two forms a protrusion on the substrate. The prototype P-type and prototype N-type field-effect transistors stand vertically on the protrusion. Due to the preservation of the position of the first etch mask, a tension skeleton structure is formed at both ends of the vertical two-dimensional complementary field-effect device prototype, so that even if the height and thickness of the prototype P-type and prototype N-type field-effect transistors are relatively large, they can maintain an upright planar shape and will not be filled. If the transistor tipps or collapses, remove the first forming mask and the first etching mask, perform doping treatment, optimize the material of the P-type and N-type field-effect transistor prototypes, fill the first and second grooves with the second insulating material and perform a leveling treatment, restore the first forming mask and the first etching mask, and perform a second etching. Except for the roots of the P-type and N-type field-effect transistor prototypes, retain the second insulating material layer at the first and second grooves. A titanium nitride structural layer is provided between the roots of two N-type field-effect transistor prototypes in the same field-effect unit for connection. Fill the grooves for sub-unit spacing and wafer spacing with the second insulating material. The process involves filling the substrate with a first insulating material and then leveling it. The first forming mask and the first etching mask are then removed. A second etching mask is placed on the area excluding the first etching mask, and a third etching is performed to form a third groove of a third depth. This removes the tensioned framework structure at both ends of the previously retained vertical field-effect device prototype. Since the sides are filled with the first insulating material, the removal of the tensioned framework structure does not affect the vertical two-dimensional complementary field-effect device prototype. A post-processing step is then performed, followed by cutting to form a fracture groove in the middle of the two N-type field-effect transistors, forming the source, gate, and drain of the P-type and N-type field-effect transistors. This method allows the fabrication of a vertical two-dimensional complementary field-effect device with a thickness on the nanometer scale. This device is arranged vertically perpendicular to the substrate, with the ends and sides of the P-type and N-type field-effect transistors filled with the first insulating material. Because the complementary field-effect device is vertically arranged, it occupies a very small substrate area, allowing for a greater number of devices to be arranged per unit area, increasing the device's integration and performance.

[0044] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0045] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0046] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0047] Figure 1 This is a schematic diagram of a cross-section of a vertical two-dimensional complementary field-effect device according to an embodiment of the present invention;

[0048] Figure 2 This is a flowchart illustrating a manufacturing method for a vertical two-dimensional complementary field-effect device according to an embodiment of the present invention.

[0049] Figure 3 This is a flowchart illustrating the doping process used in an embodiment of the manufacturing method for the vertical two-dimensional complementary field-effect device of the present invention.

[0050] Figure 4 This is a flowchart illustrating the setup of the first molding mask used in an embodiment of the manufacturing method for the vertical two-dimensional complementary field-effect device of the present invention.

[0051] Figure 5 This is a flowchart of the post-processing technology used in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0052] Figure 6 A planar schematic diagram showing the first etching process performed using a first forming mask and a first etching mask in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention;

[0053] Figure 7 This is a schematic diagram of the first etched plane in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention;

[0054] Figure 8 This is a schematic diagram of the a-a' cross-section after the first etching in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention;

[0055] Figure 9 A schematic diagram of the a-a' cross-section after filling with a second insulating material and performing a second etching, according to an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention;

[0056] Figure 10 This is a schematic diagram of cross section a-a' after a titanium nitride structure layer is connected between the roots of two N-type field-effect transistor prototypes in the same field-effect unit, as an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0057] Figure 11 This is a schematic diagram of the a-a' section after filling the grooves of the sub-cell spacing and wafer spacing with the first insulating material and performing a flattening process, as an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0058] Figure 12 A planar schematic diagram showing the third etching performed using a second etching mask in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention;

[0059] Figure 13 This is a planar schematic diagram of a P-type field-effect transistor prototype, which is vertically divided into three height segments along a first depth and doped with different densities, as an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0060] Figure 14 This is a planar schematic diagram of an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, in which an N-type field-effect transistor prototype is vertically divided into three height segments along a first depth and doped with different densities.

[0061] Figure 15 This is a schematic cross-sectional view of a strip-shaped polymer layer and a first insulating material layer formed on the surface of a silicon substrate in the first molding mask setting of an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0062] Figure 16 This is a cross-sectional view of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, in the first molding mask setting, a strip-shaped polymer layer and a first insulating material layer are formed on the surface of a silicon substrate, and carbon is filled into the groove etched in the sidewall and polished flat.

[0063] Figure 17 This is a cross-sectional view of the first molding mask setup in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, after filling the groove etched in the sidewall with carbon, polishing and smoothing it, and removing the strip-shaped polymer layer.

[0064] Figure 18 This is a cross-sectional view of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, in the first molding mask setting, after removing the strip polymer layer, filling the second insulating material, and performing the second sidewall etching, after the second insulating material layer is formed on the side away from the filled carbon in the first insulating material layer.

[0065] Figure 19This is a cross-sectional schematic diagram of the first molding mask setting in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, in which the first insulating material and carbon are removed and the second insulating material layer is retained as the first molding mask;

[0066] Figure 20 An embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention is as follows: Figure 9 After filling with the second insulating material and performing the second etching, cobalt is used to penetrate the roots of the P-type field-effect transistor prototype and the N-type field-effect transistor prototype to form a cross-sectional diagram of the connection structure at the connection point between the protrusion of the substrate and the root of the P-type field-effect transistor or the root of the N-type field-effect transistor.

[0067] Figure 21 An embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention is as follows: Figure 12 A schematic diagram of the b-b' cross-section after setting a second etching mask for the third etching, filling the third groove with the first insulating material and performing a flattening process;

[0068] Figure 22 An embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention is as follows: Figure 12 A schematic diagram of the c-c' cross-section after setting a second etching mask for the third etching, filling the third groove with the first insulating material and performing a flattening process;

[0069] Figure 23 This is a planar schematic diagram of the post-processing steps in the manufacturing method embodiment of the vertical two-dimensional complementary field-effect device of the present invention, in which a third mask is set in the second groove between two N-type field-effect transistor prototypes based on the second etching mask, and a fourth etching is performed.

[0070] Figure 24 In the post-processing of the manufacturing method embodiment of the vertical two-dimensional complementary field-effect device of the present invention, in the post-processing process... Figure 23 A schematic diagram of the b-b' cross-section after the fourth groove is filled with the first insulating material and etched for the fifth time;

[0071] Figure 25 In the post-processing of the manufacturing method embodiment of the vertical two-dimensional complementary field-effect device of the present invention, in the post-processing process... Figure 23 A schematic diagram of the d-d' cross-section after the fourth groove is filled with the first insulating material and etched for the fifth time;

[0072] Figure 26 This is a schematic diagram of the b-b' cross-section after the fifth groove of the fifth etching in the post-processing stage of the manufacturing method embodiment of the vertical two-dimensional complementary field-effect device of the present invention is filled with the second insulating material and flattened.

[0073] Figure 27A schematic diagram of the d-d' cross-section after the fifth groove of the fifth etching in the post-processing stage of the manufacturing method embodiment of the vertical two-dimensional complementary field-effect device of the invention is filled with the second insulating material and flattened.

[0074] Figure 28 This is a schematic diagram of the b-b' cross-section after the sixth etching and setting of the first insulating material film layer in the post-processing process of an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0075] Figure 29 This is a schematic diagram of the d-d' section after the sixth etching and setting of the first insulating material film layer in the post-processing process of an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0076] Figure 30 This is a schematic diagram of the b-b' cross-section after the gate groove etching is performed in the post-processing stage of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, and a second insulating material layer and a metal layer are set in the formed gate groove.

[0077] Figure 31 This is a schematic diagram of the d-d' cross-section after the gate groove etching is performed in the post-processing stage of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, and a second insulating material layer and a metal layer are set in the formed gate groove.

[0078] Figure 32 This is a schematic diagram of the a-a' section after the sixth etching to form the sixth groove and fill it with the first insulating material in the post-processing process of an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0079] Figure 33 This is a schematic diagram of the b-b' cross-section after the sixth etching to form the sixth groove and fill the first insulating material in the post-processing process of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, in an embodiment of the manufacturing method of the present invention.

[0080] Figure 34 This is a schematic diagram of the d-d' cross-section after the sixth etching to form the sixth groove and fill it with the first insulating material in the post-processing stage of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, in an embodiment of the manufacturing method of the present invention. Detailed Implementation

[0081] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0082] like Figure 1 As shown, this embodiment of the invention provides a vertical two-dimensional complementary field-effect device, including a substrate 3 and a field-effect unit. The field-effect unit includes at least two symmetrically arranged field-effect sub-units, i.e., as shown in the figure. Figure 1 The first field-effect subunit 1 and the second field-effect subunit 2 shown are provided. Each field-effect subunit includes a P-type field-effect transistor 11 and an N-type field-effect transistor 12 arranged at intervals. Both the P-type field-effect transistor 11 and the N-type field-effect transistor 12 include a source, a gate, and a drain. A first insulating material 6 is filled between the P-type field-effect transistor 11 and the N-type field-effect transistor 12 to achieve mutual isolation.

[0083] The working principle and beneficial effects of the above technical solution are as follows: The thickness of this solution is a vertical two-dimensional complementary field-effect device with a thickness of nanometers, which is arranged vertically and perpendicular to the substrate. Both ends and sides of the P-type field-effect transistor and the N-type field-effect transistor are filled with a first insulating material, which can generally be silicon nitride, etc. Since the complementary field-effect device is arranged vertically, it occupies a very small substrate area. Therefore, more devices can be arranged on a unit area, increasing the integration and performance of the devices.

[0084] In one embodiment, such as Figure 1 As shown, the source, gate, and drain of the P-type field-effect transistor 11 are arranged vertically in the same vertical plane perpendicular to the substrate, and the source, gate, and drain of the N-type field-effect transistor 12 are arranged vertically in another vertical plane perpendicular to the substrate. The upper and lower parts of the vertical plane are the source and drain, respectively, and the middle part of the vertical plane between the source and drain is the gate.

[0085] The working principle and beneficial effects of the above technical solution are as follows: Both the P-type and N-type field-effect transistors in this solution include a source, a gate, and a drain. The P-type and N-type field-effect transistors are vertically perpendicular to the substrate and are arranged in parallel intervals, that is, each of the P-type and N-type field-effect transistors forms a vertical plane of the substrate. The upper and lower ends of the P-type or N-type field-effect transistors are the source and drain, respectively, and the gate is located between the source and drain. Both ends and sides of the P-type and N-type field-effect transistors are filled with a first insulating material; this ensures that the P-type and N-type field-effect transistors are vertically perpendicular, occupying a small substrate area, thereby improving the integration density.

[0086] In one embodiment, the roots of both N-type field-effect transistors 12 are connected to a titanium nitride structure layer 5 extending horizontally to the sidewall of the fracture trench; the N-type field-effect transistors 12 in the two field-effect sub-units of the same field-effect unit are adjacent and a fracture trench 4 is provided in the middle, and the fracture trench 4 disconnects the titanium nitride structure layer 5 between the two N-type field-effect transistors 12.

[0087] The working principle and beneficial effects of the above technical solution are as follows: In this solution, the titanium nitride structure layer in the two field-effect sub-units of the same field-effect unit N-type field-effect transistor is broken by a fracture groove as required. In some cases, it can also be broken without interruption, that is, no fracture groove is provided or the depth of the fracture groove does not reach the position of the titanium nitride structure layer (as in the aforementioned embodiment); multiple sets of field-effect units can be set on the same substrate, and all field-effect units are arranged in parallel and vertically spaced intervals. The spacing between each adjacent field-effect unit can be the same as the spacing between traditional horizontally laid field-effect devices. Since the thickness of the field-effect unit is only at the nanometer level, the number of field-effect devices per unit area can be greatly increased, and the integration of the device can be improved.

[0088] In one embodiment, such as Figure 1 As shown, a connection structure 7 is provided on the protrusion of the substrate 3 at the connection point with the root of the P-type field-effect transistor 11 or the root of the N-type field-effect transistor 12. The connection structure is generally made of cobalt silicide material. The roots of the two N-type field-effect transistors 12 in the same field-effect unit are connected by the connection structure 7 and the titanium nitride structure layer 5. The gates of the P-type field-effect transistor 11 and the N-type field-effect transistor 12 on the same protrusion are connected by a metal layer.

[0089] The working principle and beneficial effects of the above technical solution are as follows: This solution has a connection structure at the connection between the protrusion of the substrate and the root of the P-type field-effect transistor or the root of the N-type field-effect transistor. The connection structure is generally made of cobalt silicide material. The gates of the P-type field-effect transistor and the N-type field-effect transistor on the same protrusion are connected by a metal layer to form a field-effect sub-unit, thereby achieving complementarity and ensuring the device function.

[0090] In one embodiment, such as Figure 1 As shown, the spacing between the sub-units of the field-effect sub-units is greater than the chip spacing between the P-type field-effect transistor 11 and the N-type field-effect transistor 12 in the same field-effect sub-unit.

[0091] The working principle and beneficial effects of the above technical solution are as follows: In this solution, the spacing between effect groups is called the sub-cell spacing, and the spacing between the P-type field-effect transistor and the N-type field-effect transistor located on the same protrusion in the same field-effect sub-cell is called the wafer spacing. Both the sub-cell spacing and the wafer spacing are at the nanometer level. The sub-cell spacing is limited to being greater than the wafer spacing. Two grooves of different depths can be formed in the first etching during manufacturing. The second groove of the second depth is formed at the sub-cell spacing, and the first groove of the first depth is formed at the wafer spacing. The etching is relatively deeper at the larger spacing, so the second depth is greater than the first depth. It is precisely because of the difference in depth between the two that the protrusion carrying the P-type field-effect transistor and the N-type field-effect transistor is formed.

[0092] like Figure 2As shown, this embodiment of the invention also provides a method for manufacturing a vertical two-dimensional complementary field-effect device, comprising the following steps:

[0093] S10 Figure 6-8 As shown, a first forming mask 110 is provided on the surface of substrate 3 with a width equal to the thickness of P-type and N-type field-effect transistors. A first etching mask 210, intersecting with the first forming mask, is provided on the surface of substrate 3 at intervals according to a set distance. The substrate 3 is etched for the first time, forming a first groove 113 of a first depth between P-type field-effect transistor prototype 111 and N-type field-effect transistor prototype 112 of the same field-effect level. A second groove 114 of a second depth is formed on the outside of P-type field-effect transistor prototype 111 and N-type field-effect transistor prototype 112, forming a field-effect cell prototype. The first depth is less than the second depth and the height difference between the two forms a protrusion 115 on substrate 3.

[0094] S20 Figure 9 As shown, after removing the first molding mask 110 and the first etching mask 210 and performing doping treatment, the second insulating material is filled into the first groove 113 and the second groove 114 and the surface is leveled. The first molding mask 110 and the first etching mask 210 are restored and a second etching is performed. Except for the roots of the P-type field-effect transistor prototype 111 and the N-type field-effect transistor prototype 112, the second insulating material layer 221 is retained in the first groove 113 and the second groove 114.

[0095] S30 Figure 10 As shown, a titanium nitride structure layer 222 is provided between the roots of two N-type field-effect transistor prototypes 112 in the same field-effect unit for connection, as... Figure 11 As shown, the grooves for the sub-unit spacing and the chip spacing (i.e., the first groove 113 and the second groove 114) are filled with the first insulating material 6 and then leveled.

[0096] S40 removes the first forming mask and the first etching mask again, as follows: Figure 12 As shown, a second etching mask 310 is provided at the location other than the first etching mask 210, and a third etching is performed to form a third groove 311 with a third depth. Then, a post-processing process is performed to form the source, gate, and drain of the P-type and N-type field-effect transistors, as shown. Figure 1 As shown, a fracture groove is then formed by cutting at the midpoint between the two N-type field-effect transistors.

[0097] The working principle of the above technical solution is as follows: the setting of the first forming mask in this solution is based on the sub-unit spacing between field-effect sub-units and the wafer spacing between the P-type and N-type field-effect transistors in the same field-effect sub-unit; in step S20, as... Figure 20As shown, after retaining the second insulating material layer at the first and second grooves, the roots of the P-type field-effect transistor prototype 111 and the N-type field-effect transistor prototype 112 are further permeated with the conductive material cobalt, thereby forming a connection structure 7 on the protrusion of the substrate that connects to the root of the P-type field-effect transistor 111 or the root of the N-type field-effect transistor 12. During manufacturing, a first forming mask is set on the substrate surface according to the sub-unit spacing between field-effect sub-units and the wafer spacing between the P-type and N-type field-effect transistors in the same field-effect sub-unit. The width of the first forming mask is the same as the thickness of the P-type and N-type field-effect transistors. The first forming mask is also spaced at intervals on the substrate surface according to a set distance. The first etch mask, with its intersecting masks, performs the first etching on the substrate. Due to the differences in sub-cell spacing and wafer pitch, a first groove of a first depth is formed between the P-type and N-type field-effect transistor prototypes within the same field-effect sub-cell. A second groove of a second depth is formed on the outer sides of the P-type and N-type field-effect transistor prototypes, forming the field-effect cell prototype. The first depth is less than the second depth, and the height difference between the two forms a protrusion on the substrate. The P-type and N-type field-effect transistor prototypes stand vertically on the protrusion. Due to the preservation of the first etch mask position, a tensioned skeleton structure is formed at both ends of the vertical two-dimensional complementary field-effect device prototype, making the P-type and N-type field-effect transistor prototypes... Even with significant height and thickness, the transistor prototype maintains its upright planar shape and will not tilt or fall over before filling. After removing the first forming mask and the first etching mask, performing doping treatment, and optimizing the materials of the P-type and N-type field-effect transistor prototypes, the second insulating material is filled into the first and second grooves and leveled. The first forming mask and the first etching mask are then restored, and a second etching is performed. Except for the roots of the P-type and N-type field-effect transistor prototypes, the second insulating material layer is retained in the first and second grooves. A titanium nitride structural layer is connected between the roots of two N-type field-effect transistor prototypes in the same field-effect unit. The grooves for sub-unit spacing and wafer spacing are then filled. The first insulating material is then flattened; the first forming mask and the first etching mask are removed again, and a second etching mask is set in the area other than the first etching mask. A third etching is performed to form a third groove of a third depth, that is, the tension skeleton structure at both ends of the previously retained vertical field-effect device prototype is removed. Since the two sides are filled with the first insulating material, the removal of the tension skeleton structure will not affect the vertical two-dimensional complementary field-effect device prototype. Then, a post-processing process is performed to form the source, gate and drain of the P-type field-effect transistor and the N-type field-effect transistor. Then, a cutting is performed in the middle of the two N-type field-effect transistors to form a fracture groove, and the titanium nitride structure layer is cut into titanium nitride structure layers that are respectively connected to the two N-type field-effect transistors.

[0098] The beneficial effects of the above technical solution are as follows: it can manufacture vertical two-dimensional complementary field-effect devices with a thickness of nanometers. The vertical two-dimensional complementary field-effect devices are arranged vertically and perpendicular to the substrate. The two ends and both sides of the P-type field-effect transistors and N-type field-effect transistors are filled with a first insulating material. Since the complementary field-effect devices are arranged vertically, they occupy a very small substrate area. Therefore, more devices can be arranged on a unit area, increasing the integration and performance of the devices.

[0099] In one embodiment, such as Figure 3 As shown, the doping process in step S20 is as follows:

[0100] S21 as Figure 9 and 13 As shown, a first mask 22 is set for two N-type field-effect transistor prototypes 112 and the second groove 114 between them in the same field-effect sub-unit. The P-type field-effect transistor prototype 111 is vertically divided into three height segments along the first depth and doped with different densities. The doping density of the upper height segment and the lower height segment is higher than that of the middle height segment. The middle height segment forms the gate prototype, and the upper height segment and the lower height segment form the source prototype or the drain prototype, respectively.

[0101] S23 as Figure 9 and 14 As shown, the first mask 22 is removed, and a second mask 23 is set on the two P-type field-effect transistor prototypes 111 and the second groove 114 on the outside of the same field-effect sub-unit. The N-type field-effect transistor prototype 112 is vertically divided into three height segments along the first depth and doped with different densities. The doping density of the upper height segment and the lower height segment is higher than that of the middle height segment. The middle height segment forms the gate prototype, and the upper height segment and the lower height segment form the source prototype or the drain prototype, respectively.

[0102] The working principle and beneficial effects of the above technical solution are as follows: This solution arranges the doping process before the first and second filling grooves. At this time, the prototypes of the P-type field-effect device and the N-type field-effect device are fully exposed. The doping process can be carried out simultaneously on both sides of the prototype of the vertical field-effect device, which increases the doping area and improves the doping efficiency. During doping, the first depth is divided into three height segments along the vertical direction for different density doping processes. The doping density of the upper and lower height segments is higher than that of the middle height segment, which ensures the quality and performance requirements of each part of the device. The gate prototype is formed in the middle height segment, and the source prototype or drain prototype is formed in the upper and lower height segments, respectively.

[0103] In one embodiment, such as Figure 4 As shown, in step S10, the first forming mask is configured as follows:

[0104] S1 as Figure 15 As shown, a polymer layer is formed on the surface of a silicon substrate 3, and strip-shaped protective layers are formed at intervals by dry photolithography to form multiple spaced strip-shaped polymer layers 101.

[0105] S2 as Figure 15 As shown, after filling the groove of the dry photolithography with the first insulating material and smoothing it, the first sidewall etching is performed to form the first insulating material layer 102 on both sides of the strip polymer layer.

[0106] S3 as Figure 15-16 As shown, carbon 104 is filled into the groove 103 of the first sidewall etching and then polished flat.

[0107] S4 Figure 17 As shown, the strip-shaped polymer layer 101 is removed, as... Figure 18 As shown, a second insulating material is filled, and a second sidewall etching is performed to form a second insulating material layer 105 on the side of the first insulating material layer away from the filled carbon.

[0108] S5 Figure 19 As shown, after removing the first insulating material layer 102 and carbon 104, the remaining second insulating material layer 105 is the first forming mask 110.

[0109] The working principle and beneficial effects of the above technical solution are as follows: A polymer layer is formed on the substrate surface using dry photolithography to create a strip-shaped polymer layer. A first insulating material is filled into the grooves created by dry photolithography. A first sidewall etching is performed, leaving the first insulating material on both sides of the strip-shaped polymer layer to form a first insulating material layer. Carbon is filled into the grooves created by the first sidewall etching. The strip-shaped polymer layer is then removed, and a second insulating material is used to fill the original position of the strip-shaped polymer layer. A second sidewall etching is performed, leaving the second insulating material on the side of the first insulating material layer away from the carbon-filled side to form a second insulating material layer. The second insulating material can generally be silicon oxide. After removing the first insulating material layer and the filled carbon, the remaining second insulating material layer is the first forming mask. This process ensures the accuracy of the distance between the first forming mask and the substrate. The first insulating material can be silicon carbide, forming a silicon carbide layer. The second insulating material can be silicon dioxide.

[0110] In one embodiment, such as Figure 5 As shown, in step S40, the post-processing technology includes:

[0111] S41 Figure 21-22 As shown, the third groove is oxidized to form a second insulating material film layer 312, and then the third groove 311 is filled with the first insulating material 6 and leveled. Figure 23As shown, a third mask 24 is set in the second groove 114 between two N-type field-effect transistor prototypes 112, and a fourth etching is performed to remove the first insulating material to form a fourth groove 313 with a fourth depth, which includes an upper height section, a middle height section and a lower height section.

[0112] S43 After filling the fourth groove 313 with the first insulating material 6 and smoothing it out, as follows Figure 24-25 As shown, a fifth etching is performed to remove the first insulating material to form a fifth groove 314 with a fifth depth, the fifth depth including an upper height section and a middle height section;

[0113] S45 Figure 26-27 As shown, after the fifth groove 314 is filled with the second insulating material 220 and leveled, as Figures 28-29 As shown, a sixth etching is performed to remove the second insulating material to form a sixth groove 315 with a sixth depth, the sixth depth including the upper height section; a first insulating material film layer 316 is provided on the sidewall of the sixth groove 315;

[0114] S47 Figures 30-31 As shown, a door groove is formed by etching the middle height section of the sixth groove 315, and the sidewall of the door groove is oxidized to form a second insulating material layer 317. The door groove is filled with metal to form a metal layer 318.

[0115] S49 Figures 32-34 As shown, the sixth groove 315 is filled with the first insulating material 6.

[0116] The working principle and beneficial effects of the above technical solution are as follows: The post-processing of this solution shapes the gate structure of the middle height section of the device through multiple etching processes, so that the gate includes a base layer and a second insulating material layer and a metal layer symmetrically arranged on both sides of the base layer. Conductivity is achieved through the metal layer. The second insulating material layer is in close contact with the base layer, and the metal layer is in close contact with the second insulating material layer. The base layer, the second insulating material layer and the metal layer are all perpendicular to the substrate, which is used to finally form the source, gate and drain of the P-type field-effect transistor and the N-type field-effect transistor. This structure ensures that the gate has sufficient area, thereby ensuring the performance of the device.

[0117] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A vertical two-dimensional complementary field effect device, characterized by, The device includes a substrate and a field-effect unit. The field-effect unit includes at least two symmetrically arranged field-effect sub-units. Each field-effect sub-unit includes a P-type field-effect transistor and an N-type field-effect transistor arranged at intervals. Both the P-type field-effect transistor and the N-type field-effect transistor include a source, a gate, and a drain. A first insulating material is filled between the P-type field-effect transistor and the N-type field-effect transistor to achieve mutual isolation. The substrate includes a protrusion, and the P-type field-effect transistor and the N-type field-effect transistor are connected to the protrusion in a direction perpendicular to the substrate; The spacing between adjacent field-effect sub-units is the first spacing, and the spacing between the P-type field-effect transistor and the N-type field-effect transistor is the second spacing. The first spacing is greater than the second spacing.

2. The vertical two-dimensional complementary field effect device of claim 1, wherein, The source, gate, and drain of the P-type field-effect transistor are arranged vertically in a first vertical plane perpendicular to the substrate, and the source, gate, and drain of the N-type field-effect transistor are arranged vertically in a second vertical plane perpendicular to the substrate. The upper part of the first vertical plane and the second vertical plane is the source or drain, the lower part of the first vertical plane and the second vertical plane is the drain or source, and the middle part of the first vertical plane and the second vertical plane is the gate.

3. The vertical two-dimensional complementary field-effect device according to claim 1, characterized in that, A connection structure is provided between the P-type field-effect transistor and the protrusion; a connection structure is provided between the N-type field-effect transistor and the protrusion.

4. The vertical two-dimensional complementary field-effect device according to claim 3, characterized in that, The connection structure includes cobalt silicide material.

5. The vertical two-dimensional complementary field-effect device according to claim 3, characterized in that, A titanium nitride structure layer is disposed between the N-type field-effect transistors in two adjacent field-effect sub-units.

6. The vertical two-dimensional complementary field-effect device according to claim 5, characterized in that, The N-type field-effect transistor is connected to the titanium nitride structural layer through the connection structure.

7. The vertical two-dimensional complementary field-effect device according to claim 5, characterized in that, A fracture groove is provided between the N-type field-effect transistors in two adjacent field-effect sub-units, and the titanium nitride structural layer extends to the sidewall of the fracture groove.

8. The vertical two-dimensional complementary field-effect device according to claim 2, characterized in that, The gate of the P-type field-effect transistor and the gate of the N-type field-effect transistor are electrically connected.

9. A method for manufacturing a vertical two-dimensional complementary field-effect device, characterized in that, Includes the following steps: S10 sets a first forming mask on the substrate, and sets a first etching mask intersecting with the first forming mask at intervals on the substrate surface according to a set distance; The substrate is etched for the first time to form a first groove of a first depth between the P-type field-effect transistor prototype and the N-type field-effect transistor prototype in the same field-effect sub-unit, and a second groove of a second depth is formed on the outside of the P-type field-effect transistor prototype and the N-type field-effect transistor prototype to form a field-effect unit prototype. The first depth is less than the second depth, and the height difference between the two forms a protrusion on the base; S20 Removes the first forming mask and the first etching mask, performs doping treatment, fills the first groove and the second groove with the second insulating material and performs a leveling treatment; The first forming mask and the first etching mask are restored, and a second etching is performed. Except for the root of the P-type field-effect transistor prototype and the N-type field-effect transistor prototype, the second insulating material layer is retained at the first groove and the second groove. S30 fills the grooves between adjacent sub-units and between the P-type field-effect transistor prototype and the N-type field-effect transistor prototype with a first insulating material and performs a leveling process. S40 removes the first forming mask and the first etching mask again, sets the second etching mask in the area outside the first etching mask, performs a third etching to form a third groove of the third depth, and then performs a post-processing process to form the source, gate and drain of the P-type field-effect transistor and the N-type field-effect transistor.

10. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 9, characterized in that, In step S20, the doping process is as follows: In step S21, a first mask is set for the two N-type field-effect transistor prototypes in the same field-effect unit and the second groove between them. The P-type field-effect transistor prototype is vertically divided into three height segments along the first depth and doped with different densities. The doping density of the upper height segment and the lower height segment is higher than that of the middle height segment. The middle height segment forms the gate prototype, and the upper height segment and the lower height segment form the source prototype or the drain prototype, respectively. S23 removes the first mask, sets a second mask on the two P-type field-effect transistor prototypes of the same field-effect unit and the second groove on their outer sides, and divides the N-type field-effect transistor prototypes vertically into three height segments along the first depth for doping treatment with different densities. The doping density of the upper height segment and the lower height segment is higher than that of the middle height segment. The middle height segment forms the gate prototype, and the upper height segment and the lower height segment form the source prototype or the drain prototype, respectively.

11. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 9, characterized in that, In step S10, the width of the first forming mask is the same as the thickness of the P-type field-effect transistor and the N-type field-effect transistor.

12. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 9, characterized in that, In step S20, after retaining the second insulating material layer in the first and second grooves (excluding the roots of the P-type and N-type field-effect transistor prototypes), a conductor material infiltration process is performed at the roots of the P-type and N-type field-effect transistor prototypes to form a connection structure between the P-type field-effect transistor and the protrusion, and a connection structure is formed between the N-type field-effect transistor and the protrusion.

13. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 12, characterized in that, In step S20, the conductor material is cobalt metal, and the connection structure includes cobalt silicide.

14. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 13, characterized in that, In step S30, a titanium nitride structure layer is connected between the roots of two N-type field-effect transistor prototypes in the same field-effect unit.

15. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 14, characterized in that, The N-type field-effect transistor is connected to the titanium nitride structural layer through the connection structure.

16. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 14, characterized in that, In step S40, a fracture groove is formed by cutting at the middle position of the two N-type field-effect transistors, and the fracture groove disconnects the titanium nitride structural layer between the roots of the two N-type field-effect transistor prototypes.

17. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 9, characterized in that, In step S10, the first forming mask is set as follows: S1, a polymer layer is set on the surface of a silicon substrate, and a strip-shaped protective layer is set at intervals for dry photolithography to form multiple spaced strip-shaped polymer layers; S2 fills the first insulating material into the groove of the dry photolithography and flattens it, then performs the first sidewall etching to form the first insulating material layer on both sides of the strip polymer layer; S3 fills the grooves etched in the sidewalls with carbon and polishes them smooth. S4 removes the strip-shaped polymer layer, fills the second insulating material, and performs a second sidewall etching to form the second insulating layer on the side of the first insulating material layer away from the filled carbon. S5 removes the first insulating material layer and carbon, and the remaining second insulating material layer is the first forming mask.

18. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 10, characterized in that, In step S40, the post-processing includes: S41 filling the third groove with the first insulating material and performing a flattening process; setting a third mask at the second groove between the two N-type field-effect transistor prototypes; and performing a fourth etching to remove the first insulating material to form a fourth groove with a fourth depth, the fourth depth including an upper height section, a middle height section and a lower height section. S43 After filling the fourth groove with the first insulating material and leveling it, a fifth etching is performed to remove the first insulating material and form a fifth groove with a fifth depth, which includes an upper height section and a middle height section. S45 After filling the fifth groove with the second insulating material and leveling it, a sixth etching is performed to remove the second insulating material to form a sixth groove with a sixth depth, the sixth depth including the upper height section; a first insulating material film layer is provided on the sidewall of the sixth groove; S47 forms a door groove by etching the middle height section of the sixth groove, oxidizes the sidewall of the door groove to form a second insulating material layer, and fills the door groove with metal to form a metal layer. S49 uses the first insulating material to fill the sixth groove.

19. The method for manufacturing a vertical two-dimensional complementary field-effect device according to claim 18, characterized in that, In step S41, before filling the third groove with the first insulating material, the third groove is oxidized to form a second insulating material film.

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