A trench SOI-LDMOS transistor with control region

Abstract

The application discloses a trench SOI-LDMOS transistor with a control region, a silicon film layer is located on a buried oxygen layer, and the trench SOI-LDMOS transistor comprises a silicon body, a source region, a trench, a drift region, a drain region, an isolation region and a control region; the silicon body and the drain region are arranged on the top of both sides of the inside of the isolation region; the source region is located at a groove of the silicon body; the drift region is all regions in the silicon film layer except the source region, the silicon body, the trench and the drain region in the inside of the isolation region; the control region is composed of two L-shaped regions, the left L-shaped region is doped with a P type, and the right L-shaped region is doped with an N type; a channel is provided by the silicon body between the side of the source region close to the drain region and the drift region; a source electrode is located above the source region, the silicon body, the isolation region and the left control region; a gate oxide layer is located above the channel and completely covers the channel; a gate electrode completely covers the gate oxide layer; and a drain electrode covers the drain region, the isolation region and the right control region. The application is high in device breakdown voltage, low in on-resistance, and superior in device performance quality factor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor high-voltage power integrated circuit devices, specifically relating to a trench silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor with a control region. Background Technology

[0002] With the development of semiconductor process technology and power integrated circuits, the requirements for high-voltage, high-power semiconductor devices are becoming increasingly stringent. Therefore, improving the performance of high-voltage devices has become particularly important, with increasing breakdown voltage and reducing on-resistance being key research focuses. LDMOS, compared to traditional MOS devices, offers advantages such as high gain, high efficiency, good linearity, excellent switching characteristics, and good thermal conductivity. Firstly, the core of trench technology is to remove the curved junction portion through trenching, thereby removing electric field concentration and transferring the high electric field to a dielectric region with a lower dielectric constant but capable of withstanding higher breakdown voltages. This improves the withstand voltage and significantly reduces the device size. Therefore, further improvements to the existing trench structure can reduce on-resistance while maintaining high breakdown voltage, thus improving device performance. This plays a positive role in expanding the application range of high-voltage, high-power devices and promoting the development of semiconductor power integrated circuits. Summary of the Invention

[0003] The purpose of this invention is to provide an LDMOS transistor with high breakdown voltage, low on-resistance, and high drive capability for the development of power integrated circuits.

[0004] The technical solution adopted in this invention is as follows:

[0005] This invention includes a substrate layer, a buried oxide layer, a silicon film layer, and a top layer of the device. The substrate layer is located at the bottom and is p-type doped with silicon. Above the substrate layer is a buried oxide layer made of silicon dioxide, and above that is a silicon film layer. The silicon film layer includes a source region, a silicon body, a drift region, a drain region, a trench, an isolation region, an L-shaped p-type control region, and an L-shaped n-type control region. The silicon body and drain region are located on either side of the trench, with a gap between the inner side of the silicon body and the trench, and the inner side of the drain region is attached to the trench. The silicon body is concave, and the source region is located within the concave area of ​​the silicon body. The isolation region surrounds the outer sides of the silicon body and drain region, and also surrounds the bottom of the silicon body, drain region, and trench. The inner walls of the isolation region are respectively attached to the outer sides of the silicon body and drain region. The bottom surface is not attached to the bottom of the silicon body, drain region, and trench; the portion inside the isolation region other than the source region, silicon body, drain region, and trench is a drift region; the L-shaped P-type control region includes a vertical P-type control region and a horizontal P-type control region; the vertical P-type control region is located on the outer side of the isolation region near the source region and is attached to the outer wall of the isolation region; the L-shaped N-type control region includes a vertical N-type control region and a horizontal N-type control region; the vertical N-type control region is located on the outer side of the isolation region near the drain region and is attached to the outer wall of the isolation region; both the horizontal P-type control region and the horizontal N-type control region are located between the buried oxide layer and the bottom of the isolation region, and the inner sides of the horizontal P-type control region and the horizontal N-type control region are attached. The top surfaces of the source region, silicon body, drift region, trench, and drain region are aligned. The trench and isolation region are made of silicon dioxide, while the source region, silicon body, drift region, drain region, L-shaped P-type control region, and L-shaped N-type control region are all made of silicon. The device channel is provided by the silicon body between the side of the source region closest to the drain region and the drift region. The source region, drain region, drift region, and L-shaped N-type control region are N-type doped, while the silicon body and L-shaped P-type control region are P-type doped. The top layer of the device includes a gate oxide layer, a source electrode, a gate electrode, and a drain electrode. The gate oxide layer is located above the channel and covers a portion of the top of the trench. The gate oxide layer is made of silicon dioxide. The gate electrode is located above the gate oxide layer. The source electrode is located above the L-shaped P-type control region and covers the top of the silicon body, the top of the isolation region, and a portion of the top of the source region. The drain electrode is located above the L-shaped N-type control region and covers the top of the isolation region and the top of the drain region.

[0006] Preferably, the substrate layer has a length of 17 μm, a thickness of 4.5 μm, and a doping concentration of 1 × 10⁻⁶. 14 cm -3 The buried oxide layer has a thickness of 0.5 μm; the silicon film layer has a thickness of 25 μm; the source region has a length of 0.9 μm, the drain region has a length of 3.5 μm, and the doping concentration of both the source and drain regions is 1 × 10⁻⁶. 20 cm -3 The silicon mass has a length of 2.3 μm and a doping concentration of 1 × 10⁻⁶. 17 cm-3 The channel length is 0.9 μm; the gate oxide layer thickness is 0.04 μm; the trench depth is 16 μm and the width is 7 μm; the drift region thickness is 3.5 μm and the doping concentration is 8 × 10⁻⁶. 14 cm -3 .

[0007] Preferably, the distance between the two sides of the trench and the corresponding inner wall of the isolation zone is 3.5 μm, and the distance between the trench and the inner side of the vertical P-type control zone and the vertical N-type control zone is 4 μm. The length of the horizontal P-type control zone and the length of the horizontal N-type control zone are both 8.5 μm, and the width of the vertical P-type control zone and the width of the vertical N-type control zone are both 1 μm. The bottom of the trench is 7.5 μm from the bottom upper surface of the isolation zone and 8 μm from the upper surface of the horizontal P-type control zone and the horizontal N-type control zone. The thickness of the horizontal P-type control zone and the thickness of the horizontal N-type control zone are both 1 μm. The doping concentration of the L-shaped P-type control zone and the L-shaped N-type control zone is 3 × 10⁻⁶. 15 cm -3 .

[0008] The beneficial effects of this invention are:

[0009] 1. The introduction of the control region in this invention effectively promotes the depletion of the drift region, thereby increasing the drift region concentration. This makes the silicon film layer of the high-voltage LDMOS device more capable of accommodating carriers and increases the current. However, due to the reduction in trench width, the device can maintain a high breakdown voltage and greatly reduce the on-resistance (Ron) of the device, resulting in a higher quality factor.

[0010] 2. Because this invention further optimizes the performance of LDMOS, it provides a new option for high-voltage integrated circuit design. Attached Figure Description

[0011] Figure 1 This is a structural diagram of the present invention;

[0012] Figure 2 The graph shows the variation of the electric field intensity along the lateral position of the upper surface of the device in Embodiment 1 of the present invention and the conventional trench LDMOS structure.

[0013] Figure 3 The graph shows the electric field intensity of Embodiment 1 of the present invention and a conventional trench LDMOS structure, which varies from the highest point on the left side of the trench along the trench boundary.

[0014] Figure 4 The graph shows the electric field intensity along the longitudinal position of the drain region in Embodiment 1 of the present invention and a conventional trench LDMOS structure.

[0015] Figure 5This is a schematic diagram illustrating the effect of changing the trench depth and drift region doping concentration on the device breakdown voltage in Embodiment 2 of the present invention.

[0016] Figure 6 This is a schematic diagram illustrating the effect of changing the doping concentration in the control region and the doping concentration in the drift region on the device breakdown voltage in Embodiment 3 of the present invention.

[0017] Figure 7 This is a schematic diagram illustrating the effect of changing the trench depth and drift region doping concentration on the device on-resistance in Embodiment 4 of the present invention.

[0018] Figure 8 This is a schematic diagram illustrating the effect of changing the doping concentration in the control region and the doping concentration in the drift region on the on-resistance of the device in Embodiment 5 of the present invention.

[0019] Figure 9 This diagram illustrates the relationship between the breakdown voltage and on-resistance of two devices: Embodiment 6 of the present invention and a traditional trench LDMOS device. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings.

[0021] like Figure 1As shown, a trench SOI-LDMOS transistor with a control region includes a substrate layer 9, a buried oxide layer 8, a silicon film layer, and a top layer of the device. The substrate layer 9 is located at the bottom and is P-type doped with silicon. Above the substrate layer 9 is the buried oxide layer 8, which is made of silicon dioxide. Above the buried oxide layer 8 is the silicon film layer. The silicon film layer includes a source region 1, a silicon body 2, a drift region 3, a drain region 4, a trench 7, an isolation region 14, an L-shaped P-type control region 5, and an L-shaped N-type control region 6. The silicon body 2 and the drain region 4 are located on both sides of the trench 7, and there is a gap between the inner side of the silicon body 2 and the trench 7. The inner side of the drain region 4 is attached to the trench 7. The silicon body 2 is concave, and the source region 1 is located within the concave region of the silicon body 2. The isolation region 14 surrounds the outer side of the silicon body 2 and the drain region 4, and surrounds the bottom of the silicon body 2, the drain region 4, and the trench 7. The inner walls of the isolation region 14 are respectively attached to the outer side of the silicon body 2 and the drain region 4. The bottom upper surface of isolation region 14 is not attached to the bottom of silicon body 2, drain region 4 and trench 7; the part inside isolation region 14 other than source region 1, silicon body 2, drain region 4 and trench 7 is drift region 3; L-shaped P-type control region 5 includes vertical P-type control region and horizontal P-type control region; vertical P-type control region is located on the outside of isolation region 14 near source region 1 and is attached to the outer wall of isolation region 14; L-shaped N-type control region 6 includes vertical N-type control region and horizontal N-type control region; vertical N-type control region is located on the outside of isolation region 14 near drain region 4 and is attached to the outer wall of isolation region 14; horizontal P-type control region and horizontal N-type control region are both located between buried oxide layer 8 and bottom of isolation region 14, and the inner sides of horizontal P-type control region and horizontal N-type control region are attached. The top surfaces of source region 1, silicon body 2, drift region 3, trench 7, and drain region 4 are aligned. Trench 7 and isolation region 14 are made of silicon dioxide. Source region 1, silicon body 2, drift region 3, drain region 4, L-shaped P-type control region 5, and L-shaped N-type control region 6 are all made of silicon. The device channel is provided by silicon body 2 between the side of source region 1 closest to the drain region and drift region 3. Source region 1, drain region 4, drift region 3, and L-shaped N-type control region 6 are N-type doped. Silicon body 2 and L-shaped P-type control region 5 are doped. The device is of type P; the top layer includes a gate oxide layer 12, a source electrode 10, a gate electrode 11, and a drain electrode 13; the gate oxide layer 12 is located above the channel and covers a portion of the top of the trench 7; the gate oxide layer 12 is made of silicon dioxide; the gate electrode 11 is located above the gate oxide layer 12; the source electrode 10 is located above the L-shaped P-type control region 5 and covers the top of the silicon body, the top of the isolation region, and a portion of the top of the source region 1; the drain electrode 13 is located above the L-shaped N-type control region 6 and covers the top of the isolation region and the top of the drain region 4. The performance of the trench SOI-LDMOS with control regions of this invention was obtained through simulation using Sentaurus TCAD software, and both the substrate 9 and the source electrode 10 were grounded in the simulation.

[0022] Let the length direction be the horizontal position X, the thickness direction be the vertical position Y, and the top point of the outer interface of the L-shaped P-type control area 5 be the origin O. The following is a detailed description of each embodiment.

[0023] Example 1: As Figure 1 As shown, a trench SOI-LDMOS transistor with a control region has a substrate layer 9 with a length of 17 μm, a thickness of 4.5 μm, and a doping concentration of 1 × 10⁻⁶. 14 cm -3 The buried oxide layer 8 has a thickness of 0.5 μm; the silicon film layer has a thickness of 25 μm; the source region has a length of 0.9 μm, the drain region has a length of 3.5 μm, and the doping concentration of both the source and drain regions is 1 × 10⁻⁶. 20 cm -3 The length of silicon bulk 2 is 2.3 μm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 The channel length is 0.9 μm; the gate oxide layer 12 has a thickness of 0.04 μm; the trench 7 has a depth of 16 μm and a width of 7 μm; the drift region has a thickness of 3.5 μm and a doping concentration of 8 × 10⁻⁶. 14 cm -3 In the horizontal direction, the distance between the left and right sides of trench 3 and the left and right inner sides of isolation region 14 is 3.5 μm, and the distance between trench 3 and the inner sides of the left vertical P-type control region 5 and the right vertical N-type control region 6 is 4 μm. The length of horizontal P-type control region 5 and horizontal N-type control region 6 is 8.5 μm, and the width of vertical P-type control region and vertical N-type control region is 1 μm. In the vertical direction, the bottom of trench 7 is 7.5 μm from the bottom upper surface of isolation region 14, and 8 μm from the upper surfaces of horizontal P-type control region 5 and horizontal N-type control region 6. The thickness of horizontal P-type control region 5 and horizontal N-type control region 6 is 1 μm. The doping concentration of L-shaped P-type control region 5 and L-shaped N-type control region 6 is 3 × 10⁻⁶. 15 cm -3 .

[0024] The curves showing the variation of the upper surface electric field intensity along the lateral position for trench SOI-LDMOS with control region and conventional trench SOI-LDMOS are shown below. Figure 2 As shown, it can be clearly seen that the transverse electric field of the trench SOI-LDMOS with control region (from the left to the right side of trench 7) at the trench surface is higher than that of the conventional trench SOI-LDMOS at the trench surface. However, due to the reduction in trench width, the transverse breakdown voltage of the trench SOI-LDMOS with control region is almost the same as that of the conventional trench SOI-LDMOS.

[0025] The electric field intensity curves of trench SOI-LDMOS with control region and conventional trench SOI-LDMOS, starting from the highest point on the left side of the trench and varying along the trench boundary, are shown in the figure below. Figure 3 As shown, it can be seen that due to the addition of the control region, although the electric field strength on the left side of the trench decreases slightly, the electric field strength below and on the right side of the trench increases significantly. Overall, the bulk breakdown voltage of the trench SOI-LDMOS with the control region is very close to, or even slightly higher than, that of the traditional trench SOI-LDMOS.

[0026] The curve of the device's electric field intensity (starting from the upper right corner of the drain region) as a function of longitudinal position is shown below. Figure 4 As shown, it can be clearly seen that the trench SOI-LDMOS with control region introduces a new electric field peak in the isolation region, and the electric field strength between 5μm and 23.5μm is significantly higher than that of the traditional trench SOI-LDMOS. Although the electric field strength at the buried oxide layer is lower than that of the traditional trench SOI-LDMOS, the longitudinal breakdown voltage of the two is very similar overall.

[0027] Example 2: Changing only the trench depth and the doping concentration N in the drift region d The remaining parameters are the same as those in Example 1;

[0028] like Figure 5 As shown, when the trench depth remains constant, the device breakdown voltage first increases and then decreases with increasing drift region doping concentration; with increasing trench depth h, the highest device breakdown voltage corresponding to each h first increases and then decreases. The optimal trench depth h is 16 μm, and the optimal drift region doping concentration is 8 × 10⁻⁶. 14 cm -3 .

[0029] Example 3: Changing only the doping concentration N in the L-shaped P-type control region 5 cp L-shaped N-type control region 6 doping concentration N cn The drift region doping concentration and other parameters are the same as those in Example 1;

[0030] like Figure 6 As shown, when the doping concentrations of the L-shaped P-type control region 5 and the L-shaped N-type control region 6 remain constant, the device breakdown voltage first increases and then decreases with increasing drift region doping concentration. Furthermore, with increasing doping concentrations of the L-shaped P-type control region 5 and the L-shaped N-type control region 6, the maximum device breakdown voltage corresponding to each control region's doping concentration first increases and then decreases, and the drift region doping concentration corresponding to the maximum breakdown voltage of each control region first increases and then decreases. The optimal doping concentration for the L-shaped P-type control region 5 and the L-shaped N-type control region 6 is 3 × 10⁻⁶. 15 cm -3 .

[0031] Example 4: Only the trench depth and drift region doping concentration were changed, while the other parameters remained the same as those in Example 1;

[0032] like Figure 7 As shown, when the trench depth remains constant, the on-resistance decreases with increasing doping concentration in the drift region; and the on-resistance increases with increasing trench depth.

[0033] Example 5: Only changing the doping concentration of L-shaped P-type control region 5, L-shaped N-type control region 6, and drift region doping concentration N d The remaining parameters are the same as those in Example 1;

[0034] like Figure 8 As shown, the point is the drift region doping concentration corresponding to the highest device breakdown voltage under each control region concentration. Therefore, as the control region doping concentration increases, the drift region doping concentration corresponding to the highest breakdown voltage first increases and then decreases, resulting in a decrease and then an increase in the on-resistance.

[0035] Example 6: All parameters are the same as those in Example 1. The breakdown voltage and on-resistance of two device structures, a trench SOI-LDMOS with a control region and a conventional trench SOI-LDMOS, are compared.

[0036] like Figure 9 As shown, compared with traditional trench SOI-LDMOS, trench SOI-LDMOS with control region can maintain a high breakdown voltage of up to 460V, while greatly reducing the on-resistance of the device to as low as 40Ω·mm2. Therefore, trench SOI-LDMOS with control region can achieve a higher quality factor.

Claims

1. A trench SOI-LDMOS transistor with a control region, comprising a substrate layer, a buried oxide layer, a silicon film layer, and a top layer of the device; wherein the substrate layer is disposed at the bottom, is p-type doped, and the doping material is silicon; a buried oxide layer is disposed above the substrate layer, the buried oxide layer being made of silicon dioxide, and a silicon film layer is disposed above the buried oxide layer; characterized in that: The silicon film layer includes a source region, a silicon body, a drift region, a drain region, a trench, an isolation region, an L-shaped P-type control region, and an L-shaped N-type control region. The silicon body and the drain region are located on both sides of the trench, with a gap between the inner side of the silicon body and the trench, and the inner side of the drain region is attached to the trench. The silicon body is concave, and the source region is located within the concave region of the silicon body. The isolation region surrounds the outer side of the silicon body and the drain region, and also surrounds the bottom of the silicon body, the drain region, and the trench. The inner walls on both sides of the isolation region are respectively attached to the outer side of the silicon body and the drain region, and the upper surface of the bottom of the isolation region is attached to the silicon body, the drain region, and the trench. The bottom of each region is not attached; the interior of the isolation region, excluding the source region, silicon body, drain region, and trench, is a drift region; the L-shaped P-type control region includes a vertical P-type control region and a horizontal P-type control region; the vertical P-type control region is located on the outer side of the isolation region near the source region and is attached to the outer wall of the isolation region; the L-shaped N-type control region includes a vertical N-type control region and a horizontal N-type control region; the vertical N-type control region is located on the outer side of the isolation region near the drain region and is attached to the outer wall of the isolation region; the horizontal P-type control region and the horizontal N-type control region... The regions are all located between the buried oxide layer and the bottom of the isolation region, and the horizontal P-type control region and the horizontal N-type control region are attached to each other on the inner side; the top surfaces of the source region, silicon body, drift region, trench, and drain region are aligned; the trench and isolation region are made of silicon dioxide, and the source region, silicon body, drift region, drain region, L-shaped P-type control region, and L-shaped N-type control region are all made of silicon; the device channel is provided by the silicon body between the side of the source region closest to the drain region and the drift region; the source region, drain region, drift region, and L-shaped N-type control region are N-type doped. The device is P-type doped in both the silicon body and the L-shaped P-type control region. The top layer of the device includes a gate oxide layer, a source electrode, a gate electrode, and a drain electrode. The gate oxide layer is located above the channel and covers a portion of the top of the trench. The gate oxide layer is made of silicon dioxide. The gate electrode is located above the gate oxide layer. The source electrode is located above the L-shaped P-type control region and covers the top of the silicon body, the top of the isolation region, and a portion of the top of the source region. The drain electrode is located above the L-shaped N-type control region and covers the top of the isolation region and the top of the drain region.

2. The trench SOI-LDMOS transistor with a control region according to claim 1, characterized in that: The substrate layer has a length of 17 μm, a thickness of 4.5 μm, and a doping concentration of 1 × 10⁻⁶. 14 cm -3 The buried oxide layer has a thickness of 0.5 μm; the silicon film layer has a thickness of 25 μm; the source region has a length of 0.9 μm, the drain region has a length of 3.5 μm, and the doping concentration of both the source and drain regions is 1 × 10⁻⁶. 20 cm -3 The silicon mass has a length of 2.3 μm and a doping concentration of 1 × 10⁻⁶. 17 cm -3 The channel length is 0.9 μm; the gate oxide layer thickness is 0.04 μm; the trench depth is 16 μm and the width is 7 μm; the drift region thickness is 3.5 μm and the doping concentration is 8 × 10⁻⁶. 14 cm -3 .

3. The trench SOI-LDMOS transistor with a control region according to claim 2, characterized in that: The trench is 3.5 μm away from the inner wall of the corresponding side of the isolation region on both sides, and 4 μm away from the inner side of the vertical P-type control region and the vertical N-type control region. The length of the horizontal P-type control region and the horizontal N-type control region are both 8.5 μm, and the width of the vertical P-type control region and the vertical N-type control region are both 1 μm. The bottom of the trench is 7.5 μm from the bottom upper surface of the isolation region and 8 μm from the upper surface of the horizontal P-type control region and the horizontal N-type control region. The thickness of the horizontal P-type control region and the horizontal N-type control region are both 1 μm. The doping concentration of the L-shaped P-type control region and the L-shaped N-type control region is 3 × 10⁻⁶. 15 cm -3 .

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