Flash memory cell array

Abstract

The present invention relates to a memory cell array of a flash memory, comprising a substrate and at least one memory cell, wherein the memory cell comprises: a common source diffusion region located in the substrate; a common line located directly above the source diffusion region; a pair of stacked gates located on either side of the common line, each stacked gate comprising a control gate and a floating gate vertically stacked; two select gates located on opposite sides of the stacked gates from the common line; in each stacked gate, the control gate is laterally larger than the floating gate, is located above the top of the floating gate and is aligned with one side of the floating gate; or both lateral ends of the control gate extend beyond the floating gate, resulting in misalignment on both sides; and the control gate extends along the misaligned side of the floating gate, between the floating gate and the common line and / or the select gate, toward the substrate below. The memory cell array of the present invention has a small size, a simple structure, is easy to program and erase, and has excellent and stable performance.

Description

Technical Field

[0001] The present invention relates to a non-volatile flash memory storage unit and a memory thereof, and in particular to a split gate flash memory storage unit and a memory thereof. Background Art

[0002] Nonvolatile memory includes electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash EEPROM. Flash memory is widely used for high-capacity data storage in many devices, such as memory cards, mobile phones, personal digital assistants (PDAs), and automotive electronic systems. These applications require high-density memory with a small cell size and low manufacturing cost.

[0003] The prior art generally includes two basic types of non-volatile flash memory cell structures: stacked gate and split gate structures. A stacked gate memory cell typically has a bit line contact, a source region, a floating gate, and a control gate, wherein the control gate is directly above the floating gate. In a split gate memory cell, the control gate is also located above the floating gate, but is laterally offset from it. The manufacturing process of a stacked gate memory cell is generally simpler than that of a split gate memory cell. However, stacked gate memory cells have the problem of over-erase. To solve the over-erase problem, additional circuitry needs to be designed to maintain the threshold voltage of the memory cell within a specific range after an erase cycle, which increases the complexity of the circuit design.

[0004] While split-gate memory cells don't suffer from over-erase issues, they typically have an additional gate, called a select gate, that's slightly larger than stacked-gate memory cells. Furthermore, these cells are typically manufactured using double-poly or triple-poly processes, which are slightly more complex and require more steps. Despite this, the lack of complex circuit design caused by over-erase has led to their widespread use, particularly in embedded non-volatile memory.

[0005] With the rapid development of industries using flash memory, especially the rapid development of industries using embedded flash memory such as electric vehicles, these industries are in urgent need of flash memory storage units and memories with smaller size and better performance. Summary of the Invention

[0006] The object of the present invention is to provide a novel split gate flash memory cell and its array and flash memory which are small in size, simple in structure, easy to program and erase, and have excellent and stable performance.

[0007] The present invention relates to a memory cell array of a flash memory, comprising: a substrate, and at least one memory cell;

[0008] The storage unit comprises:

[0009] a common source diffusion region located in the substrate;

[0010] a common line located on the substrate and directly above the source diffusion region;

[0011] a pair of stacked gates, located on the substrate and arranged in a left-right mirror-symmetrical manner on both sides of the common line, wherein each stacked gate includes a control gate and a floating gate vertically stacked;

[0012] Two selection gates are respectively located on a side of the stacked gate opposite to the common line, aligned with the stacked gate, and arranged in left-right mirror symmetry along the common line;

[0013] In each of the stacked gates, the control gate has a lateral dimension larger than that of the floating gate, is located above the top of the floating gate and is aligned with one side of the floating gate; or both lateral ends of the control gate extend beyond the floating gate, so that both sides are not aligned;

[0014] The control gate extends along the misaligned side of the floating gate, between the floating gate and the common line and / or the select gate, toward the underlying substrate;

[0015] A floating gate oxide layer is provided between the floating gate and the substrate, extending laterally from an end located on the misaligned side of the floating gate toward the common line and / or the select gate and protruding beyond the floating gate to isolate the substrate from the downwardly extending portion of the control gate;

[0016] A first dielectric layer is provided between the control gate and the floating gate, and extends laterally between the downward extension portion of the control gate and the lateral protrusion portion of the floating gate oxide layer, isolating the substrate from the downward extension portion of the control gate.

[0017] In a preferred embodiment, the thickness of the first dielectric layer is greater than the thickness of the floating gate oxide layer.

[0018] In another preferred embodiment, a second dielectric layer is sandwiched between the laterally extending first dielectric layer and the laterally protruding portion of the floating gate oxide layer.

[0019] In another preferred embodiment, the source diffusion region does not overlap with the floating gate.

[0020] In another preferred embodiment, the programming channel of the memory cell is a channel region in the substrate starting from the source diffusion region to the floating gate region, and the erasing channel is a channel region in the substrate from the floating gate to the underlying floating gate.

[0021] In another preferred embodiment, the control gate is aligned with one side of the floating gate, the aligned side is adjacent to the select gate, and the lateral protrusion of the floating gate oxide layer, the laterally extending first dielectric layer, and the second dielectric layer are all between the floating gate and the common line.

[0022] In another preferred embodiment, the control gate is aligned with one side of the floating gate, with the aligned side adjacent to the common line. The laterally protruding portion of the floating gate oxide layer, the laterally extending first dielectric layer, and the second dielectric layer are all located between the floating gate and the select gate. More preferably, the second dielectric layer laterally extends and protrudes into the bottom of the floating gate, with the protruding portion being less than 1 / 2 the length of the floating gate. Even more preferably, an ion diffusion region is located in the substrate directly below the laterally extending first dielectric layer, and is of the same ion type as the source diffusion region.

[0023] In another preferred embodiment, the control gate is misaligned with both sides of the floating gate, and the control gate extends along the misaligned sides of the floating gate, between the floating gate and the common line and the select gate, toward the underlying substrate. The floating gate oxide layer of the floating gate extends laterally from both ends of the floating gate toward the common line and the select gate. The laterally protruding portions of the floating gate oxide layer, the laterally extending first dielectric layer, and the second dielectric layer are all located between the floating gate and the common line and the select gate. More preferably, the second dielectric layer located between the floating gate and the select gate extends laterally, protruding into the bottom of the floating gate, with the protruding portion having a length less than 1 / 2 the length of the floating gate. Furthermore, an ion diffusion region is located in the substrate directly below the laterally extending first dielectric layer located between the floating gate and the select gate, and has the same ion type as the source diffusion region. In another preferred embodiment, the substrate further includes two bitline ion diffusion regions, located on opposite sides of the two select gates from the stacked gate, and have the same ion type as the source diffusion region.

[0024] The programming channel of the flash memory cell of the present invention extends from the channel region near the source electrode in the substrate to the floating gate, while the erasing channel extends from the floating gate to the channel region in the underlying substrate. These are simple channels conventional in the industry, requiring no additional components to form new channels, such as an erase gate or floating gate side bumps. Therefore, the memory cell of the present invention has a simple structure, and programming and erasing operations are simple and easy.

[0025] Furthermore, the control gate extends downward along the misaligned side of the floating gate, surrounding the side of the floating gate, significantly improving the capacitive coupling ratio and thereby reducing the voltage required for erase operations. The laterally protruding portion of the floating gate oxide layer and the laterally extending first dielectric layer superimposed thereon can jointly withstand the high voltage during the erase process, preventing breakdown between the substrate and the downwardly extending portion of the control gate. Consequently, the memory cell and its array of the present invention are easy to operate and offer excellent and stable performance. Furthermore, the memory cell of the present invention has few components and a simple manufacturing process.

[0026] The array of memory cells of the present invention is biased so that all memory cells therein can be erased simultaneously, while programming is bit selective. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1a 1 is a top plan view of the memory cell of the present invention and the 2×2 array it comprises.

[0028] Figure 1b yes Figure 2-3 A 2x2 array of memory cells is shown as a top view looking down from the plane of the top surface of the floating gates.

[0029] Figure 2-7 There are 6 specific embodiments of the storage unit of the present invention. Figure 1a Section view along section line AA.

[0030] Figures 8a-8g yes Figure 2 Schematic diagram of the manufacturing process steps of the memory cell shown.

[0031] Figures 9a-9g yes Figure 4 Schematic diagram of the manufacturing process steps of the memory cell shown.

[0032] Figures 10a-10e yes Figure 6 Schematic diagram of the manufacturing process steps of the memory cell shown.

[0033] Figures 11a-11d yes Figure 7 Schematic diagram of the manufacturing process steps of the memory cell shown.

[0034] Figure 12 It is a circuit diagram of a small memory array of the memory cell of the present invention.

[0035] Figure 13 yes Figure 2 The 2x2 array of memory cells shown has bias signals connected during different operations.

[0036] The same numbers in the drawings indicate the same or similar elements.

[0037] Detailed Description of the Invention

[0038] The memory cell and its array or memory of the present invention will be described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the specific embodiments shown in the drawings.

[0039] The flash memory or its array of the present invention includes a series of split-gate flash memory cells, as shown in FIG1 .

[0040] Figure 1a and Figure 1b A 2×2 array consisting of four memory cells of the present invention is shown respectively. Figure 1a It is a top plan view of a 2×2 array of memory cells of the present invention. Figure 1b yes Figure 2-3 The specific memory cell structure shown is a 2×2 array of memory cells with stacked gates aligned on one side adjacent to the select gate (SG), viewed from above from the top surface plane of the floating gate (FG).

[0041] like Figure 1a and 1b As shown, in the memory cell array of the present invention, odd and even rows are separated by an isolation region (IA), which is formed in the substrate. The corresponding select gates, control gates, and common lines of all memory cells in each column are connected to form a whole, and they are parallel to each other and cross the isolation region (IA) between adjacent rows. However, the floating gates of the memory cells in each column are not connected, and the two adjacent floating gates of the odd and even rows in each column are also separated by the isolation region (IA), as shown in FIG. Figure 1b shown.

[0042] like Figure 2-7 Six specific storage units and their structures of the present invention are respectively illustrated. They are respectively along Figure 1a A cross-sectional view taken along section line AA in FIG. Each of these devices has a P-type substrate (not shown) with an N-well in the substrate. The memory cell and its array are located in the N-well. The source diffusion region in the memory cell is doped with P ions and is located in the N-well.

[0043] When a P-type substrate has a P-well instead of an N-well to accommodate a memory cell, the source diffusion region in the memory cell is doped with N ions. In this case, a deep N-well is required between the P-well and the substrate to isolate the P-well from the substrate.

[0044] like Figure 2-7 As shown, the common line (COM) is located directly above the P-type source diffusion region of the memory cell of the present invention. The common line is connected to the source diffusion region and is located above the N-well. The common line is preferably made of polysilicon.

[0045] As can be seen from the figure, each memory cell of the present invention has a pair of stacked gates: a vertically stacked floating gate (FG) and a control gate (CG). The control gate is located above the floating gate and is laterally larger than the floating gate, aligned with one side of the floating gate. Alternatively, both ends of the control gate extend beyond the floating gate, resulting in misalignment between the two sides. The two stacked gates are arranged in mirror-image symmetry on either side of a common line. Both the floating gate and the control gate are preferably made of polysilicon.

[0046] Each memory cell also has two select gates (SG), one on each side of the stacked gate opposite the common line, arranged in mirror-image symmetry with respect to the common line. The select gates are aligned with the adjacent stacked gates. The select gates are connected to the word lines (WL). A gate oxide layer lies between the select gates and the substrate. The select gates can be made of polysilicon or a high-k metal.

[0047] An isolation dielectric layer 4 is placed between the stacked gate and the common line and select gate. The thickness of the isolation dielectric layer 4 is preferably greater than that of the floating gate oxide layer. The spacer dielectric layer 4 is made of a conventional spacer dielectric material in the industry, preferably a nitride, oxide, or a combination thereof.

[0048] In the case of stacked gates where the control gate is aligned with one side of the floating gate, their aligned sides may be adjacent to the select gate or the common line.

[0049] When the aligned side of the stacked gate is adjacent to the select gate, the control gate located on top of the floating gate extends toward the underlying substrate between the floating gate and the common line along the unaligned side surface of the floating gate. Figure 2-3 shown.

[0050] When the aligned side of the stacked gate is adjacent to the common line, the control gate located on top of the floating gate extends toward the underlying substrate between the floating gate and the select gate along the unaligned side surface of the floating gate. Figure 4-6 shown.

[0051] When both sides of the stacked gate are misaligned, that is, both ends of the control gate extend beyond the floating gate, resulting in misalignment between the control gate and the floating gate, the control gate located on top of the floating gate extends toward the substrate below, along the two misaligned side surfaces of the floating gate, between the floating gate and the common line and the select gate. Figure 7 shown.

[0052] In a stacked gate, a first dielectric layer is placed between the control gate (CG) and the floating gate (FG). The first dielectric layer is located on all surfaces of the floating gate adjacent to the control gate, including the top surface and misaligned side surfaces, to separate the control gate from the floating gate.

[0053] Between the floating gate and the substrate, there is a floating gate oxide layer, which extends laterally from the end located on the misaligned side of the floating gate toward the common line and / or the select gate and protrudes beyond the floating gate to isolate the substrate from the downward extending portion of the control gate.

[0054] When the aligned side of the stacked gate is adjacent to the select gate, the floating gate oxide layer extends laterally toward the common line, forming a lateral protrusion 1 to isolate the substrate from the downward extension of the control gate. Figure 2-3 When the aligned side of the stacked gate is adjacent to the common line, the floating gate oxide layer extends laterally toward the select gate to form a lateral protrusion 1 to isolate the substrate from the downward extension of the control gate. Figure 4-6 shown.

[0055] When both sides of the stacked gate are misaligned, that is, both lateral ends of the control gate extend beyond the floating gate, making both sides of the two gates misaligned; the floating gate oxide layer extends laterally toward the common line and the select gate at the same time, forming a lateral protrusion 1 to isolate the substrate from the downward extension of the control gate. Figure 7 shown.

[0056] The first dielectric layer between the control gate and the floating gate extends laterally between the downward extension of the control gate and the lateral protrusion 1 of the floating gate oxide layer to form a lateral extension 2 of the first dielectric layer to isolate the substrate from the downward extension of the control gate.

[0057] The lateral protrusion 1 of the floating gate oxide layer and the lateral extension 2 of the first dielectric layer are superimposed to isolate the substrate from the downward extension of the control gate. The lateral extension 2 of the first dielectric layer is the same thickness as or thicker than the lateral protrusion 1 of the floating gate oxide layer. Preferably, the former is thicker. As long as their superimposed thickness can withstand the high voltage between the substrate and the control gate applied during the erase operation. In a preferred embodiment, the total thickness of the two superimposed layers is preferably More preferred

[0058] More preferably, a second dielectric layer 3 is sandwiched between the lateral protrusion 1 of the floating gate oxide layer and the lateral extension 2 of the first dielectric layer, such as Figure 3 and 5 -6. The three-layer stacking is more conducive to resisting the high voltage between the substrate and the control gate during the erase operation, avoiding breakdown between the substrate and the downward extension of the control gate, and ensuring smooth erase operation from the floating gate to the channel area in the substrate. In a preferred embodiment, the total thickness of the three-layer stacking is preferably More preferred

[0059] The first dielectric layer and its lateral extension portion 2 have the same thickness and material.

[0060] The thickness of the second dielectric layer 3 can be the same as or different from that of the lateral extension portion 2 of the first dielectric layer, and the material can be the same as or different from that of the lateral extension portion 2 of the first dielectric layer. Both can be selected from oxides, nitrides, or a combination thereof.

[0061] In the memory cell of the present invention, it is preferred that the source diffusion region and the floating gate do not overlap, and more preferably there is a gap between them, which can improve programming performance.

[0062] When one side of the stacked gate is aligned and the aligned side is adjacent to the select gate, the second dielectric layer 3 preferably does not extend laterally into the bottom of the floating gate, such as Figure 3 This ensures better programming performance.

[0063] Similarly, when the two sides of the stacked gate are not aligned, the second dielectric layer 3 between the floating gate and the common line preferably does not extend laterally into the bottom of the floating gate, thereby ensuring better programming performance.

[0064] When one side of the stacked gate is aligned and adjacent to the common line, an ion diffusion region exists directly beneath the lateral extension 2 of the first dielectric layer (or the second dielectric layer 3). This region is located in the substrate, between the bitline diffusion region and the source region, and contains the same ion type as the source diffusion region. This ion diffusion region reduces the resistance of the channel region beneath the dielectric layer, facilitating programming.

[0065] Similarly, when the two sides of the stacked gate are not aligned, there is an ion diffusion region directly below the lateral extension portion 2 of the first dielectric layer (or the second dielectric layer 3) between the floating gate and the select gate, located in the substrate, between the bit line diffusion region and the source region, and the ion type is the same as that of the source diffusion region.

[0066] When one side of the stacked gates is aligned and the aligned side is adjacent to the common line, the second dielectric layer 3 preferably extends laterally and protrudes into the bottom of the floating gate, such as Figure 6 The length of the protruding portion is preferably less than 1 / 2 of the length of the floating gate. This ensures smooth programming and erasing operations while reducing the working area of ​​the floating gate oxide layer involved in programming and erasing, thereby improving the data retention of the memory cell.

[0067] Similarly, when the two sides of the stacked gate are not aligned, the second dielectric layer 3 between the floating gate and the select gate preferably extends laterally and protrudes into the bottom of the floating gate, and the length of the protruding portion is preferably less than 1 / 2 of the length of the floating gate.

[0068] In the memory cell of the present invention, two bitline ion diffusion regions are further provided in the substrate, one on each side of the two select gates opposite the stacked gate, connected to the bit lines (BL). The ion type of the bitline ion diffusion regions is the same as that of the source diffusion region. The bitline ion diffusion regions may or may not overlap with the select gates.

[0069] Figures 8a-8g Shows the preparation Figure 2 The preferred method of the memory cell and its array is shown. Figure 2 In the memory cell shown, one side of the stacked gate is aligned and the aligned side is adjacent to the select gate.

[0070] like Figure 8a As shown in this method, on a P-type substrate including an N-well, a layer of oxide 5 is first formed by thermal oxidation to a thickness of about Then, a first polysilicon layer 6 is deposited on the oxide layer 5 to a thickness of Then, the polysilicon layer 6 is etched to the substrate to form several rows of silicon strips, each row of silicon strips being consistent with each row of memory cells to be formed on the substrate, and an intervening area (IA) is formed in the substrate between adjacent rows to separate adjacent rows of silicon strips.

[0071] Then, if Figure 8b As shown, etching is performed on each row of silicon strips to form the two initial floating gates of each memory cell and their spacing. For a memory cell, the specific etching steps are: depositing a layer of photoresist on the entire device, then passing a photolithography mask over the photoresist to cover the portion where the two floating gates of the cell are to be formed, leaving the corresponding Figure 2 The portion of the gap between the two floating gates in the cell shown. Next, using a photolithography process, the exposed silicon strip is anisotropically etched downward to the oxide layer 5, forming two initial floating gates (FG) and a recess between them. This intermediate recess corresponds to the gap between the two floating gates in the cell. The etching method can be dry etching. Then, a dielectric layer 7 is deposited on the device with a thickness of about The dielectric layer 7 may be pure oxide or nitride, or a combination of oxide, nitride, and oxide (ONO).

[0072] Then, if Figure 8c As shown, a second polysilicon layer 8 is deposited on the dielectric layer 7 with a thickness of about Etching is then performed to form the stacked gates. For a single memory cell, the specific etching steps are as follows: a layer of photoresist 9 is deposited on the second polysilicon layer 8. Two photomasks 10 are then placed over the photoresist, covering the portions intended to form the two stacked gates. The portions intended to form the common line and the select gate are left exposed on either side of each mask 10. Next, the uncovered portions are anisotropically etched downward to the substrate, forming a pair of vertically stacked control gates (CG) and floating gates (FG).

[0073] like Figure 8d As shown, in the pair of stacked gates formed by etching, the control gate is above the floating gate and extends downward along the misaligned side of the floating gate (the side adjacent to the common line) along with the dielectric layer 7. At the same time, the control gate extends in a direction perpendicular to each row of floating gate polysilicon stripes in the first polysilicon layer 6 and spans the isolation region (IA) between adjacent rows of silicon stripes.

[0074] Then, if Figure 8e As shown, an isolation dielectric 4 is formed on the sidewall of the stacked gate. The thickness of the isolation dielectric layer 4 is greater than the floating gate oxide layer 5 and is approximately Its material is nitride.

[0075] Then, if Figure 8f As shown, a common source region is formed in the substrate between the two stacked gates by ion implantation using P-type dopants. A dielectric oxide layer 11 is formed on the substrate on the side of the stacked gate opposite to the source region, with a thickness of approximately Then, a third polysilicon layer 12 is deposited on the entire device with a thickness of about

[0076] Finally, if Figure 8g As shown, the third polysilicon layer 12 is anisotropically etched to form select gates and common lines. The select gates and common lines are formed so that they are aligned with the stacked gates and parallel to the control gates. Like the control gates, they extend perpendicular to each row of floating gate polysilicon strips in the first polysilicon layer 6 and span the isolation region (IA) between adjacent rows of silicon strips. P-type dopants are then implanted into the substrate on the side of the select gate opposite the stacked gate to form the bitline (BL) diffusion region.

[0077] Afterwards, a glass material, such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG), is deposited over the entire wafer and then etched to form openings for the bitline (BL) contacts. Finally, a metal layer is deposited over the glass and patterned to form the bitlines and bitline contacts.

[0078] Figure 3The preparation method of the memory cell shown above Figure 2 The manufacturing method of the memory cell shown is substantially the same, except that a step of forming the second dielectric layer 3 is added. Figure 8b After the etching step (i.e., etching to form a recess corresponding to the distance between the two floating gates) and before depositing the dielectric layer 7, the oxide layer at the bottom of the recess exposed after etching is annealed using N2, O2, or N2O to improve the quality of the oxide layer at this location due to etching and increase its thickness, thereby forming a dielectric layer, i.e., the second dielectric layer 3. Then, the dielectric layer 7 is deposited over the entire device.

[0079] Figures 9a-9g Shows the preparation Figure 4 The preferred method of storing the unit shown. Figure 4 In the memory cell shown, one side of the stacked gate is aligned and the aligned side is adjacent to the common line. Figures 8a-8g The method shown is different only in that Figures 9b-9c The steps shown are the same as Figures 8b-8c The steps are different, and the other steps are the same.

[0080] exist Figure 9b In the steps shown, etching is performed on each row of silicon strips to form the initial floating gate in each memory cell. The total length of the initial floating gate (along the row direction of the silicon strips) is: the sum of the length of the two floating gates in the final stacked gate pair and the distance between them. For a memory cell, the specific etching steps are: depositing a layer of photoresist on the entire device, and then covering the portion of the initial floating gate to be left to form each memory cell through a photolithography mask on the photoresist, while exposing the two side portions. Then, using a photolithography process, anisotropically etch the exposed silicon strip portion downward to the oxide layer 5 to form the initial floating gate of each cell and the recesses on both sides thereof. The etching method can be dry etching. Then, along the two outer sides of the formed initial floating gate, P-type ion dopants are injected into the substrate to form two ion diffusion regions. Then, a dielectric layer 7 is deposited on the device with a thickness of approximately The dielectric layer 7 may be pure oxide or nitride, or a combination of oxide, nitride, and oxide (ONO).

[0081] Then, if Figure 9c As shown, a second polysilicon layer 8 is deposited on the dielectric layer 7 with a thickness of about Etching is then performed to form the stacked gate. For a memory cell, the specific etching steps are as follows: a layer of photoresist 9 is deposited on the second polysilicon layer 8. Two photomasks 10 are placed over the photoresist, covering only the portion intended to form the stacked gate. On either side of each mask 10, portions intended to form the common line and select gate are exposed. Next, the uncovered portions are anisotropically etched downward to the substrate, forming a pair of vertically stacked control gates (CG) and floating gates (FG).

[0082] like Figure 9d As shown, in the pair of stacked gates formed by etching, the control gate is above the floating gate and extends downward along the misaligned side of the floating gate (the side adjacent to the select gate) along with the dielectric layer 7. At the same time, the control gate extends in a direction perpendicular to each row of floating gate polysilicon stripes in the first polysilicon layer 6 and spans the isolation region (IA) between adjacent rows of silicon stripes.

[0083] Figure 5 The preparation method of the memory cell shown above Figure 4 The manufacturing method of the memory cell shown is substantially the same, except that a step of forming the second dielectric layer 3 is added. Figure 9b After the etching step (i.e., etching to form the floating gate portion of each cell and the recesses on both sides thereof) and before depositing the dielectric layer 7, the oxide layer at the bottom of the recess exposed after etching is annealed using N2, O2, or N2O to improve the quality of the oxide layer at this location due to etching and increase its thickness, thereby forming a dielectric layer, i.e., the second dielectric layer 3. Then, the dielectric layer 7 is deposited over the entire device.

[0084] Figures 10a-10e Is prepared Figure 6 The first few steps in the preferred method of the storage unit shown, and the subsequent steps, are the same as those described above. Figures 9c-9g The steps shown are exactly the same. Figure 6 In the memory cell shown, the second dielectric layer extends laterally and protrudes into the bottom of the floating gate.

[0085] like Figure 10a As shown, an oxide layer 5 is formed on a P-type substrate including an N-well.

[0086] Then, if Figure 10bAs shown, a recessed region is etched in the oxide layer 5 along the column direction of the array, corresponding to the floating gate portion of a column of memory cells. The lateral length (the row direction perpendicular to the columns in the array) of this recessed region is less than the total length of the floating gate portion of the memory cell along the row direction. The difference between the two lengths is twice the length of the second dielectric layer 3 protruding from the bottom of the floating gate. The total length of the floating gate portion of the memory cell along the row direction is the sum of the lengths of the two floating gates in the final stacked gate pair and the lateral length of the common line between them. The etching method is dry etching using a photoresist and a mask.

[0087] Then, if Figure 10c As shown, a dielectric layer 13 is deposited on the entire device. The material is preferably oxide, and is preferably the same as that of the oxide layer 5.

[0088] Then, if Figure 10d As shown, a first polysilicon layer 6 is deposited on the dielectric layer. Then, the polysilicon layer 6 is etched to the substrate to form several rows of silicon strips. Each row of silicon strips corresponds to each row of memory cells to be formed on the substrate. Between adjacent rows, an intervening area (IA) is formed in the substrate to separate adjacent rows of silicon strips.

[0089] Afterwards, if Figure 10e As shown, etching is performed on each row of silicon strips to form the initial floating gate in each memory cell, and two ion diffusion regions are formed in the substrate on opposite sides of the initial floating gate. Then, a dielectric layer 7 is deposited. This step is the same as the above Figure 9b Same as shown.

[0090] Subsequent preparation Figure 6 The steps of the storage unit are the same as above Figures 9c-9g The steps shown are exactly the same.

[0091] Figures 11a-11d Shows the preparation Figure 7 The first few steps of the preferred method of storing the unit shown, and the subsequent steps, are the same as those described above. Figures 9e-9g The steps shown are exactly the same. Figure 7 In the memory cell shown, both sides of the stacked gate are not aligned. The difference between this method and the method shown in 9a-9g above is only that Figures 11b-11c The steps shown are different from those in FIG. 9 b - 9 c , and the other steps are the same.

[0092] exist Figure 11bIn the steps shown, etching is performed on each row of silicon strips to form a floating gate (FG) in each memory cell. This step directly forms two floating gates in the final memory cell. For a memory cell, the specific etching steps are: depositing a layer of photoresist on the entire device, and then covering the portion to be left to form the two floating gates in the cell with a photolithography mask on the photoresist, while exposing the two side portions. Then, using a photolithography process, anisotropically etch the exposed silicon strip portion downward to the oxide layer 5 to form the two floating gates of the cell, and the middle recess and two outer recesses therebetween. The middle recess between the two floating gates corresponds to the spacing between the two floating gates in the cell. The etching method can be dry etching. Then, along the outer edges of the two floating gates formed, P-type ion dopants are injected into the substrate to form two ion diffusion regions. Then, a dielectric layer 7 is deposited on the device with a thickness of approximately The dielectric layer 7 may be pure oxide or nitride, or a combination of oxide, nitride, and oxide (ONO).

[0093] Then, if Figure 11c As shown, a second polysilicon layer 8 is deposited on the dielectric layer 7 with a thickness of about Etching is then performed to form the stacked gate. For a single memory cell, the specific etching steps are as follows: a layer of photoresist 9 is deposited on the second polysilicon layer 8. Two photomasks 10 are placed over the photoresist, covering only the portion intended to form the stacked gate. The portions intended to form the common line and the select gate are exposed on either side of each mask 10. Next, the uncovered portions are anisotropically etched downward to the substrate, forming a pair of vertically stacked control gates (CG) and floating gates (FG).

[0094] like Figure 11d As shown, in the pair of stacked gates formed by etching, the control gate is above the floating gate and extends downward along the two misaligned sides of the floating gate along with the dielectric layer 7. At the same time, the control gate 8 extends in a direction perpendicular to each row of floating gate polysilicon strips in the first polysilicon layer 6 and spans the isolation region (IA) between adjacent rows of silicon strips.

[0095] Refer to the following Figure 12 and Figure 13 , describing the operation and use of the memory cell array of the present invention.

[0096] Figure 12A circuit diagram of a memory cell array of the present invention is shown. The memory array is constructed on an N-well in a P-type substrate. The bit lines (BL) of the memory cells in each row are connected, and the word lines (WL) and common lines (COM) of the memory cells in each column are connected. The select gates and control gates corresponding to all memory cells in each column are connected together and parallel to the common line. By increasing and / or decreasing the number of rows and / or columns, arrays of different sizes can be formed. All memory cells in the array can be erased simultaneously, and programming is bit-selective.

[0097] The following describes the operation process by taking the four memory cells 400, 410, 420, and 430 in the array as an example. The specific structures of these four memory cells are as follows: Figure 2 shown.

[0098] Figure 13 The bias signals to which the four memory cells are connected during different operations are shown.

[0099] Memory cell 400 is selected for individual programming. During programming, electrons are injected into the floating gate from the channel region in the substrate near the source. Memory cell 400 is programmed by driving its BL to 5V, WL to 0V, CG to 3-5V, COM to 0V, and N-well to 4.5V.

[0100] In memory cell 400, the potential of word line WL is lower than that of bit line BL and the N-well. Furthermore, the potential of floating gate FG, coupled from control gate CG, is also lower than that of the N-well. Consequently, an inversion channel forms between the bit line diffusion region and the source region in the substrate. The voltage difference between the bit line diffusion region and the source region is 5V, creating a strong lateral electric field from the bit line diffusion region to the source region. Consequently, holes are accelerated from one side of the channel to the other, leading to impact ionization in the depletion region of the bit line diffusion region. Hot electrons generated by impact ionization are attracted to the forward-biased floating gate and injected into the floating gate. Consequently, the number of electrons in the floating gate increases during programming.

[0101] The word line WL of memory cell 410 is at a potential of 6.5V, higher than the bit line BL and the N-well, indicating that it is off. Although there is a potential difference between the bit line diffusion region and the source region, hole movement and impact ionization cannot occur. Therefore, programming is impossible.

[0102] The potentials of the bit line diffusion regions and source regions of memory cells 420 and 430 are both 0, no potential difference and no lateral electric field are formed, and programming does not occur.

[0103] During an erase operation, electrons tunnel from the floating gate of a selected cell to a channel region in the substrate below the floating gate under the action of a high voltage between the floating gate and the substrate below the floating gate.

[0104] Memory cells 400 and 420 share the same erase bias signal. Their bit lines BL are left floating, and the word lines WL are at the same potential as the N-well. The control gate CG is at a much lower potential than the source region and the N-well connected to the common line. The potential of the floating gate FG coupled to the control gate CG is also much lower than that of the source region and the N-well. Because the voltage between the floating gate and the N-well is greater than 10V, a high electric field is generated, sufficient to cause electrons trapped in the floating gate to tunnel into the channel. The tunneling mechanism is direct tunneling and / or Fowler-Nordheim tunneling.

[0105] The erase bias signals for memory cells 410 and 430 are the same. The control gate CG potential is 0, and the potential coupled to the floating gate FG is also 0. Since the voltage difference between the floating gate and the N-well is small, electrons in the floating gate cannot tunnel into the channel in the substrate.

[0106] Alternatively, the erase bias signals of the four memory cells are set to be consistent so that the four memory cells are erased simultaneously. In a read operation, the data in a row of memory cells can be read out simultaneously.

[0107] The bit lines BL of the memory cells 400 , 410 , 420 and 430 are selected, and the memory cell to be read is selected according to whether the word line WL is turned on or not.

[0108] The word line WL of memory cells 400 and 410 is at a lower potential than the bit line BL and the N-well. The floating gate FG, coupled to a potential of 0 from the control gate CG, is also lower than the bit line and the N-well. Consequently, an inversion channel forms between the bit line diffusion region and the source region in the substrate. Furthermore, a 2V potential difference exists between the bit line diffusion region and the source region, creating a lateral electric field. Consequently, a read current is generated.

[0109] The potentials of the bit line diffusion regions and source regions of the memory cells 420 and 430 are both 0, no lateral electric field is formed, and therefore no read current is generated.

[0110] Figure 13 The memory cells shown are connected to bias signals during different operations, not only for Figure 2 The specific memory cells shown are also applicable to memory cells of other structures within the scope of the present invention, such as Figure 3 、 Figure 4-7 The storage unit shown, or other storage units. Figure 3 The programming and erasing process of the memory cell shown is the same as that described above. Figure 2 The storage unit is exactly the same as Figure 2 compared to, Figure 3 There is a second dielectric layer in the device, which can make the erasing process more stable and smooth without affecting the operating bias required for programming and erasing. Figure 4-7 The programming and erasing process of the memory cell shown is also the same as that described above. Figure 2Specifically, the ion diffusion region in the substrate below the second dielectric layer, between the bit line diffusion region and the source region, reduces the resistance in the channel region, making programming more convenient and not affecting the operating bias required for programming and erasing. Figure 6 In the memory cell shown, the second dielectric layer protrudes into the bottom of the floating gate, which can reduce the working area of ​​the floating gate oxide layer involved in programming and erasing, further improve data retention, and does not affect the operating bias required for programming and erasing.

[0111] As is apparent from the foregoing, the present invention provides a novel and improved split-gate flash memory and its manufacturing process. Although only some currently preferred embodiments have been described in detail, as will be appreciated by those skilled in the art, other variations and modifications may be made without departing from the scope of the invention as defined in the appended claims.

Claims

1. A memory cell array of a flash memory, characterized in that include: a substrate, and at least one memory cell; The storage unit comprises: a common source diffusion region located in the substrate; a common line located on the substrate and directly above the source diffusion region; a pair of stacked gates, located on the substrate and arranged in a left-right mirror-symmetrical manner on both sides of the common line, wherein each stacked gate includes a control gate and a floating gate vertically stacked; Two selection gates are respectively located on a side of the stacked gate opposite to the common line, aligned with the stacked gate, and arranged in left-right mirror symmetry along the common line; In each stacked gate, the control gate has a lateral dimension larger than that of the floating gate, is located above the top of the floating gate and is aligned with one side of the floating gate; or both lateral ends of the control gate extend beyond the floating gate, so that both sides are misaligned; and the control gate extends toward the substrate below, between the floating gate and the common line and / or the select gate, along the misaligned side surfaces of the floating gate. A floating gate oxide layer is provided between the floating gate and the substrate, extending laterally from an end located on the misaligned side of the floating gate toward the common line and / or the select gate and protruding beyond the floating gate to isolate the substrate from the downwardly extending portion of the control gate; A first dielectric layer is provided between the control gate and the floating gate, and extends laterally between the downward extension portion of the control gate and the lateral protrusion portion of the floating gate oxide layer, isolating the substrate from the downward extension portion of the control gate.

2. The memory cell array according to claim 1, wherein: The thickness of the first dielectric layer is greater than the thickness of the floating gate oxide layer.

3. The memory cell array according to claim 1 or 2, wherein: A second dielectric layer is sandwiched between the laterally extending first dielectric layer and the laterally protruding portion of the floating gate oxide layer.

4. The memory cell array according to any one of claims 1 to 3, wherein: The source diffusion region does not overlap with the floating gate.

5. The memory cell array according to any one of claims 1 to 4, wherein: The programming channel of the memory cell is a channel region starting from a source diffusion region in the substrate to a floating gate region, and the erasing channel is a channel region from the floating gate to the substrate below the floating gate.

6. The memory cell array according to any one of claims 1 to 4, wherein: The control gate is aligned with one side of the floating gate, and the aligned side is adjacent to the selection gate. The lateral protrusion of the floating gate oxide layer, the laterally extended first dielectric layer, and the second dielectric layer are all located between the floating gate and the common line.

7. The memory cell array according to any one of claims 1 to 4, wherein: The control gate is aligned with one side of the floating gate, and the aligned side is adjacent to the common line. The lateral protrusion of the floating gate oxide layer, the laterally extended first dielectric layer, and the second dielectric layer are all located between the floating gate and the selection gate.

8. The memory cell array according to any one of claims 1 to 4, wherein: The control gate is misaligned with both sides of the floating gate, and the control gate extends toward the underlying substrate between the floating gate and the common line and the select gate along the misaligned side surfaces of the floating gate. The floating gate oxide layer of the floating gate extends laterally from both ends of the floating gate toward the common line and the select gate. The laterally protruding portion of the floating gate oxide layer, the laterally extending first dielectric layer, and the second dielectric layer are all located between the floating gate and the common line and the select gate.

9. The memory cell array according to claim 7, wherein: The second dielectric layer extends laterally and protrudes into the bottom of the floating gate, and the length of the protruding portion is less than 1 / 2 of the length of the floating gate.

10. The memory cell array according to claim 8, wherein: The second dielectric layer located between the floating gate and the selection gate extends laterally and protrudes into the bottom of the floating gate. The length of the protruding portion is less than 1 / 2 of the length of the floating gate.

11. The memory cell array according to claim 7, wherein: There is an ion diffusion region directly below the laterally extending first dielectric layer, located in the substrate, and the ion type is the same as that of the source diffusion region.

12. The memory cell array according to claim 8, wherein: There is an ion diffusion region located in the substrate just below the first dielectric layer extending laterally between the floating gate and the selection gate. The ion type is the same as that of the source diffusion region.

13. The memory cell array according to claim 1, wherein: There are two bit line ion diffusion regions in the substrate, which are respectively located on one side of the two selection gates opposite to the stacked gate, and the ion type of the bit line ion diffusion regions is the same as that of the source diffusion region.

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