Radar Signal Variable-Scale Parallel Processing Platform and Method Based on a Single FPGA

Abstract

The present invention discloses a variable-scale parallel processing platform and method for radar signals based on a single FPGA. The processing platform includes an FPGA chip, on which a data protocol processing module, a digital frequency conversion module, a DBF synthesis module, a radar signal transmission module, a radar signal reception module, a radar signal processing module, a target detection module, and a data transmission module are integrated. The radar signal processing module is used to perform pulse compression processing on the radar received echo signal according to the basic parameters, obtain the pulse compression processing result, and store it sequentially by row. Column conversion is performed on the pulse compression processing result based on the row-column conversion method, and correlation accumulation processing is performed on the pulse compression processing result after column conversion to obtain the final radar signal processing result. The present invention can not only meet the miniaturization requirements, but also improve the working efficiency of radar signal processing, and can also flexibly modify the implementation scheme according to actual needs.

Description

Technical Field

[0001] The present invention relates to the technical field of radar signal processing, and particularly to a variable-scale parallel processing platform and method for radar signals based on a single FPGA. Background Art

[0002] Currently, mainstream radar signal processing systems generally adopt embedded platforms such as DSP+FPGA. Generally, the FPGA platform completes the preprocessing process of radar signals, and the DSP completes data processing processes such as target detection, quantity estimation, and target track tracking.

[0003] The existing DSP+FPGA embedded radar signal processing platform involves the development of multiple chips. The entire system is complex and difficult, and the volume and power consumption of the device are limited, unable to meet the miniaturization requirements. Summary of the Invention

[0004] The purpose of the present invention is to provide a variable-scale parallel processing platform and method for radar signals based on a single FPGA. By integrating the processing of radar signals onto one FPGA and combining the design of DDR row-column conversion to achieve parallel processing; the present invention can not only meet the miniaturization requirements, but also improve the working efficiency of radar signal processing, and can flexibly modify the implementation scheme according to actual needs.

[0005] The present invention is realized through the following technical solutions:

[0006] In a first aspect, the present invention provides a variable-scale parallel processing platform for radar signals based on a single FPGA. The processing platform includes an FPGA chip, and a data protocol processing module, a digital frequency conversion module, a DBF synthesis module, a radar signal transmitting module, a radar signal receiving module, and a radar signal processing module are integrated on the FPGA chip;

[0007] The data protocol processing module is used to parse the control information and configuration information sent by the host computer into basic parameters according to the communication protocol and send them to each module;

[0008] The digital frequency conversion module is configured according to digital frequency conversion parameters, and performs digital down-conversion processing on N-channel radar echo signals sampled from an external ADC to obtain N-channel radar baseband signals;

[0009] The DBF synthesis module is configured according to DBF parameters, and performs digital beam synthesis on N-channel radar baseband signals to obtain M-channel digital synthesis signals; both N and M are positive integers, and N is greater than M;

[0010] The radar signal transmitting module is configured according to radar transmission control parameters to perform radar signal transmission control;

[0011] The radar signal receiving module is configured according to radar receiving control parameters, combines M-channel digital synthesized signals for radar receiving control, and sends the radar received echo signal to the radar signal processing module;

[0012] The radar signal processing module is used to perform pulse compression processing on the radar received echo signal according to the length of the fast Fourier transform (FFT) and the length of the inverse fast Fourier transform (IFFT), obtain the pulse compression processing result and store it sequentially by row; perform column conversion on the pulse compression processing result based on the row-column conversion method, and perform correlation accumulation processing on the pulse compression processing result after column conversion to obtain the final radar signal processing result.

[0013] Further, the basic parameters include digital frequency conversion parameters, DBF parameters, radar transmission control parameters, radar receiving control parameters, target detection parameters, and radar signal processing parameters;

[0014] The digital frequency conversion parameters are used to be sent to the digital frequency conversion module;

[0015] The DBF parameters are used to be sent to the DBF synthesis module;

[0016] The radar transmission control parameters are used to be sent to the radar signal transmission module;

[0017] The radar receiving control parameters are used to be sent to the radar signal receiving module;

[0018] The target detection parameters are used to be sent to the target detection module;

[0019] The radar signal processing parameters are used to be sent to the radar signal processing module.

[0020] Further, the transmission control parameters include the transmission pulse width and the transmission period;

[0021] The receiving control parameters include the pulse compression length, the number of coherent accumulation times, and the receiving period;

[0022] The digital frequency conversion parameters include the received intermediate frequency;

[0023] The target detection parameters include the CFAR average number of points, the CFAR protection number of points, and the CFAR threshold;

[0024] The radar signal processing parameters include the length of the fast Fourier transform (FFT) and the length of the inverse fast Fourier transform (IFFT).

[0025] Further, the length of the fast Fourier transform (FFT) is equal to the pulse compression length;

[0026] The length of the inverse fast Fourier transform (IFFT) is equal to the number of coherent integration times.

[0027] Furthermore, the processing platform further includes a target detection module and a data transmission module integrated on the FPGA chip;

[0028] The target detection module is used to read the final radar signal processing result row by row from the DDR memory, perform modulus operation on the final radar signal processing result while reading, calculate the average amplitude and signal peak within the pulse compression length, and obtain the target detection threshold in combination with the threshold parameter; compare the target detection threshold with the signal peak to obtain the target detection result; wherein, if the signal peak is greater than the detection threshold, it is considered that the radar signal is a true target, otherwise the radar signal is not a true target and the signal peak is discarded; in addition, the signal peak is searched while calculating the average amplitude, and the method is to compare the values of three consecutive points. If the value of the middle point is greater than the values of the two side points at the same time, it is considered as the signal peak;

[0029] The data transmission module is used to transmit the target detection result to the host computer.

[0030] Furthermore, the pulse compression processing includes:

[0031] Perform FFT operation on the radar received echo signal to obtain the first operation result;

[0032] Perform complex multiplication operation on the first operation result and the matched filtering coefficient to obtain the second operation result;

[0033] Perform IFFT operation on the second operation result to obtain the pulse compression processing result, and store the pulse compression processing result row by row in the DDR memory.

[0034] Wherein, the DDR memory is a double data rate memory.

[0035] Furthermore, the column conversion of the pulse compression processing result based on the row-column conversion method includes:

[0036] Assume that the pulse compression processing result is an M x N matrix, where M represents the size of the row and N represents the size of the column;

[0037] When writing to the DDR memory, first divide the DDR memory user address into a row area and a column area. Then, according to the read / write characteristics of the DDR memory and the requirements of parallel processing, convert the serially input pulse compression data with a bit width of x for n bits into a data with a bit width of n*x. Combining with the radar operation characteristics, when storing the pulse compression data, convert the row index into a column address and use the converted column index of the pulse compression as the row address when switching; where n is a positive integer greater than 0.

[0038] When reading from the DDR memory, read the data in the pulse compression processing result in the address order.

[0039] Further, the relevant accumulation processing of the pulse compression processing result after column conversion includes:

[0040] According to the pulse compression processing result after column conversion, read the pulse compression processing result from the DDR memory column by column, and perform coherent accumulation operation based on FFT operation to obtain the coherent accumulation operation result as the final radar signal processing result; and store the final radar signal processing result in the DDR memory in a scrambled order.

[0041] In a second aspect, the present invention further provides a variable-scale parallel processing method for radar signals based on a single FPGA, which is applied to the variable-scale parallel processing platform for radar signals based on a single FPGA; the method includes:

[0042] After the variable-scale parallel processing platform for radar signals based on a single FPGA is powered on, configure various basic parameters according to the control information and configuration information sent by the host computer, and enter the standby mode to wait for the radar work instruction;

[0043] When receiving the radar work instruction, the variable-scale parallel processing platform for radar signals based on a single FPGA performs the following radar signal processing according to the various basic parameters that have been configured:

[0044] According to the digital frequency conversion parameters, perform digital down-conversion processing on N radar echo signals sampled from the external ADC to obtain N radar baseband signals;

[0045] According to the DBF parameters and the radar baseband signals, perform digital beamforming on the N radar baseband signals to obtain M digital synthesized signals; both N and M are positive integers, and N is greater than M;

[0046] According to the radar transmission control parameters, perform radar transmission control; and according to the radar reception control parameters and the M digital synthesized signals, perform radar reception control, and send the radar received echo signal to the radar signal processing module;

[0047] According to the length of the Fast Fourier Transform (FFT) and the length of the Inverse Fast Fourier Transform (IFFT), perform pulse compression processing on the radar received echo signal, obtain the pulse compression processing result and store it sequentially by row; based on the row-column conversion method, perform column conversion on the pulse compression processing result, and perform correlation accumulation processing on the pulse compression processing result after column conversion to obtain the final radar signal processing result.

[0048] Further, the method further includes:

[0049] Perform target detection based on the final radar signal processing result to obtain the target detection result; and transmit the target detection result to the host computer.

[0050] Further, the performing pulse compression processing on the radar received echo signal, obtaining the pulse compression processing result and storing it sequentially by row; performing column conversion on the pulse compression processing result based on the row-column conversion method, and performing correlation accumulation processing on the pulse compression processing result after column conversion to obtain the final radar signal processing result includes:

[0051] Perform FFT operation on the radar received echo signal to obtain the first operation result;

[0052] Perform complex multiplication operation on the first operation result and the matched filtering coefficient to obtain the second operation result;

[0053] Perform IFFT operation on the second operation result to obtain the pulse compression processing result, and store the pulse compression processing result sequentially by row in the DDR memory;

[0054] Perform column conversion on the pulse compression processing result based on the row-column conversion method to obtain the pulse compression processing result after column conversion;

[0055] According to the pulse compression processing result after column conversion, read the pulse compression processing result from the DDR memory by column, and perform coherent accumulation operation based on FFT operation to obtain the coherent accumulation operation result as the final radar signal processing result; and store the final radar signal processing result in disorder in the DDR memory.

[0056] Wherein, the performing column conversion on the pulse compression processing result based on the row-column conversion method includes:

[0057] Assume that the pulse compression processing result is an M x N matrix, where M represents the size of the row and N represents the size of the column;

[0058] When writing to the DDR memory, first divide the DDR memory user address into a row area and a column area. Then, according to the read / write characteristics of the DDR memory and the requirements of parallel processing, convert the serially input pulse compression data with a bit width of x for n bits into a data with a bit width of n*x. Combining the characteristics of radar operations, when storing the pulse compression data, convert the row index into a column address and use the converted column index of the pulse compression as the row address when switching.

[0059] When reading from the DDR memory, simply read the data in the pulse compression processing result in address order.

[0060] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0061] The present invention relates to a radar signal variable-scale parallel processing platform and method based on a single FPGA. The present invention realizes a variable-scale FPGA real-time parallel processing method. One is the radar signal processing in a variable-scale parallel processing method, and the other is an implementation method of DDR row-column conversion designed to meet the radar signal processing characteristics and DDR usage efficiency characteristics. Through the rich computing resources and parallel processing characteristics of the FPGA, this system has completed the variable-scale radar signal parallel processing technology, which not only improves the working efficiency of radar signal processing but also has the characteristics of equipment miniaturization and low power consumption, and can adapt to the adaptation requirements of various platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, form a part of this application, and do not limit the embodiments of the present invention. In the drawings:

[0063] Figure 1 is the working flowchart of the radar signal variable-scale parallel processing platform based on a single FPGA of the present invention;

[0064] Figure 2 is the block diagram of the radar signal variable-scale parallel processing platform based on a single FPGA of the present invention;

[0065] Figure 3 is the flowchart of the data protocol processing module of the present invention;

[0066] Figure 4 is the block diagram of the digital frequency conversion module of the present invention;

[0067] Figure 5 is the block diagram of the DBF synthesis module of the present invention;

[0068] Figure 6 is the block diagram of the radar signal transmission module of the present invention;

[0069] Figure 7 is the block diagram of the radar signal reception module of the present invention;

[0070] Figure 8 This is the block diagram of the pulse compression processing of the present invention;

[0071] Figure 9 This is the block diagram of the coherent integration processing of the present invention;

[0072] Figure 10 This is the block diagram of the DDR read / write row-column conversion processing of the present invention;

[0073] Figure 11 This is the block diagram of the target detection module of the present invention. Detailed implementation manners

[0074] In the following, the term "comprise" or "may comprise" that may be used in various embodiments of the present invention indicates the presence of the functions, operations or elements of the present invention, and does not limit the addition of one or more functions, operations or elements. Further, as used in various embodiments of the present invention, the terms "comprise", "have" and their cognates are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as precluding the existence or addition of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items first.

[0075] In various embodiments of the present invention, the expression "or" or "at least one of A or / and B" includes any combination or all combinations of the recited words. For example, the expression "A or B" or "at least one of A or / and B" may include A, may include B, or may include both A and B.

[0076] Expressions (such as "first", "second", etc.) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but do not limit the corresponding constituent elements. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only for the purpose of distinguishing one element from other elements. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, without departing from the scope of various embodiments of the present invention, the first element may be referred to as the second element, and similarly, the second element may also be referred to as the first element.

[0077] It should be noted that: if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and a third constituent element may be "connected" between the first constituent element and the second constituent element. Conversely, when one constituent element is "directly connected" to another constituent element, it can be understood that there is no third constituent element between the first constituent element and the second constituent element.

[0078] The terms used in various embodiments of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the various embodiments of the present invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present invention pertain. The terms (such as those defined in a commonly used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or being overly formal, unless clearly defined in the various embodiments of the present invention.

[0079] To make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the embodiments and the accompanying drawings. The illustrative embodiments and descriptions thereof of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0080] Embodiment 1

[0081] As Figure 2 shown, the radar signal variable-scale parallel processing platform based on a single FPGA of the present invention includes an FPGA chip, and a data protocol processing module, a digital frequency conversion module, a DBF synthesis module, a radar signal transmission module, a radar signal reception module, a radar signal processing module, a target detection module, and a data transmission module are integrated on the FPGA chip;

[0082] The data protocol processing module is configured to parse the control information and configuration information sent by the host computer into basic parameters according to the communication protocol and send them to each module;

[0083] Among them, the basic parameters include digital frequency conversion parameters, DBF parameters, radar transmission control parameters, radar reception control parameters, target detection parameters, and radar signal processing parameters; the digital frequency conversion parameters are used to be sent to the digital frequency conversion module; the DBF parameters are used to be sent to the DBF synthesis module; the radar transmission control parameters are used to be sent to the radar signal transmission module; the radar reception control parameters are used to be sent to the radar signal reception module; the target detection parameters are used to be sent to the target detection module; the radar signal processing parameters are used to be sent to the radar signal processing module. As Figure 3As shown. Specifically, the transmission control parameters include the transmission pulse width and the transmission period; the reception control parameters include the pulse compression length, the number of coherent integration times, and the reception period; the digital frequency conversion parameters include the intermediate frequency of reception; the target detection parameters include the CFAR average number of points, the CFAR guard number of points, and the CFAR threshold; the radar signal processing parameters include the length of the fast Fourier transform (FFT) and the length of the inverse fast Fourier transform (IFFT).

[0084] Meanwhile, the FPGA chip reads the radar transmission waveform according to the pulse compression length in the reception control parameters and performs FFT calculation on it to obtain the pulse compression matching filter coefficients.

[0085] The digital frequency conversion module is configured according to the digital frequency conversion parameters to perform digital down-conversion processing on the N-channel radar echo signals sampled from the external ADC. The frequency accuracy is the processing clock divided by 2 to the nth power (n is the bit width of the frequency accuracy), supports multi-channel parallel processing, and can flexibly change the number of parallel processing according to the data format of the AD. Finally, N-channel radar baseband signals are obtained; the internal processing block diagram of the digital frequency conversion module is as Figure 4 shown.

[0086] The DBF synthesis module is configured according to the DBF parameters to perform digital beam synthesis on the N-channel radar baseband signals to obtain M-channel digital synthesis signals; both N and M are positive integers, and N is greater than M; specifically, the N-channel radar echo signals can be synthesized into M-channel data for subsequent radar signal processing. The internal processing block diagram of the DBF synthesis module is as Figure 5 shown.

[0087] The radar signal transmission module is used to set the transmission period and the number of transmissions according to the system requirements, and then perform radar transmission control according to the set radar transmission control parameters; the block diagram of the radar signal transmission module is as Figure 6 shown.

[0088] The radar signal reception module is used to perform radar reception control according to the radar reception control parameters and the M-channel digital synthesis signals, and send the radar received echo signals to the radar signal processing module; the block diagram of the radar signal reception module is as Figure 7 shown.

[0089] The radar signal processing module is used to perform pulse compression processing on the radar received echo signals according to the length of the fast Fourier transform (FFT) and the length of the inverse fast Fourier transform (IFFT), obtain the pulse compression processing results and store them sequentially by row; perform column conversion on the pulse compression processing results based on the row-column conversion method, and perform correlation accumulation processing on the pulse compression processing results after column conversion to obtain the final radar signal processing results.

[0090] Specifically, according to the lengths of the Fast Fourier Transform (FFT) and the Inverse Fast Fourier Transform (IFFT) set by the system parameters, perform pulse compression operations on the valid radar received echo signals, and send the obtained results to the DDR memory for caching, as Figure 8 shown. Then, perform coherent accumulation operations according to the setting of the length of the Inverse Fast Fourier Transform (IFFT), and finally send the processed results to the DDR memory for caching and waiting for the next step of processing.

[0091] The target detection module is used to read the final radar signal processing results from the DDR memory in row order. While reading, perform modulus operations on the final radar signal processing results, calculate the average amplitude and signal peak within the pulse compression length, and obtain the target detection threshold in combination with the threshold parameters; compare the target detection threshold with the signal peak to obtain the target detection result; wherein, if the signal peak is greater than the detection threshold, it is considered that the radar signal is a true target, otherwise the radar signal is not a true target, and the signal peak is discarded; in addition, while calculating the average amplitude, find the signal peak. The method is to compare the values of three consecutive points. If the value of the middle point is greater than the values of the two side points at the same time, it is considered the signal peak;

[0092] The data transmission module is used to transmit the target detection results to the host computer. The data transmission module can be flexibly adapted according to different user host computer interfaces, such as Ethernet, PCIE, or serial port, etc.

[0093] As a further implementation, the length of the Fast Fourier Transform (FFT) is equal to the pulse compression length;

[0094] The length of the Inverse Fast Fourier Transform (IFFT) is equal to the number of coherent accumulation times.

[0095] As a further implementation, as Figure 8 shown, the pulse compression process mainly includes the following steps:

[0096] Perform FFT operations on the radar received echo signals to obtain the first operation result;

[0097] Perform complex multiplication operations on the first operation result and the matched filtering coefficients to obtain the second operation result;

[0098] Perform IFFT operations on the second operation result to obtain the pulse compression processing result, and store the pulse compression processing result in the DDR memory in row order. Among them, the DDR memory is a double data rate memory.

[0099] As Figure 9As shown, the coherent accumulation operation mainly performs the FFT operation, but the data required for the operation is in the order of the pulse compression processing results sorted by "column"; while the pulse compression processing results are stored in the order of "row". How to appropriately convert "row" and "column" in combination with the characteristics of the DDR memory is the key point in the design.

[0100] Both the read and write operations of the DDR memory are burst read and write. In a single burst read and write, the read and write order is continuous, and the continuous read and write bandwidth can reach the full bandwidth. When reading and writing out of order, the bandwidth is only 25% of the continuous read and write bandwidth. At the same time, the radar signal processing has the order of "first row then column" during the operation. To adapt to the above two characteristics and meet the requirement of improving the processing efficiency, a row-column conversion design is carried out during the read and write of the DDR memory. Based on the row-column conversion method, the column conversion of the pulse compression processing results is performed. The specific design method is as follows:

[0101] Assume that the pulse compression processing result is an M x N matrix, where M represents the size of "row" and N represents the size of "column"; when writing to the DDR memory, first divide the DDR memory user address into "row" area and "column" area, and then according to the read and write characteristics of the DDR memory and the requirement of parallel processing, convert the n (n is a variable scale) serially input pulse compression data with a bit width of "x" into a data with a bit width of "n*x"; combined with the characteristics of radar operation, convert the "row" index into the "column" address when storing the pulse compression data, and convert the "column" index of the switched pulse compression into the "row" address for use; when reading from the DDR memory, read the data in the pulse compression processing result in the address order. As Figure 10 shown, Figure 10 is the block diagram of the row-column conversion processing for the DDR memory read and write.

[0102] The result of the above design is: when writing data to the DDR memory, although it is written out of order, the number of read and write operations to the DDR memory is reduced by using the data cache method, adapting to the read and write characteristics of the DDR memory. When reading, it is read in order, and the read and write bandwidth will be greatly improved. When the serialization coefficient n and the ratio of the number of read and write operations are greater than or equal to 4:1, the read and write bandwidth will reach the maximum value; when performing a single read of data, it is equivalent to reading n columns of data, so n-way parallel coherent accumulation processing can be performed, meeting the requirement of parallel processing and further improving the processing efficiency. After completing the pulse compression and coherent accumulation processing of the radar signal, the data is written back to the DDR memory again, waiting for the target detection module to process.

[0103] As a further implementation, the block diagram of the target detection module is shown in Figure 11, the execution process of the target detection module is as follows: First, read the coherent integration data "sequentially", then perform CFAR detection to find the "peak value", calculate the target distance and speed, and then calculate the target angle based on the "peak value" of the sum and difference channels.

[0104] The working principle is:

[0105] The present invention realizes a variable-scale FPGA real-time parallel processing method. One is the parallel processing method of radar signal processing on a variable scale, and the other is the implementation method of DDR row-column conversion designed to meet the characteristics of radar signal processing and the DDR usage efficiency characteristics. Through the rich computing resources and parallel processing characteristics of the FPGA, this system has completed the variable-scale radar signal parallel processing technology. While improving the working efficiency of radar signal processing, it also has the characteristics of equipment miniaturization and low power consumption, and can adapt to the adaptation requirements of various platforms.

[0106] Regarding the implementation method of DDR row-column conversion (i.e., the row-column conversion method), the present invention combines the read-write characteristics of the DDR memory with the characteristics of radar signal processing to realize the DDR read-write method of "row-column conversion".

[0107] DDR read-write characteristics: DDR particles are divided into bank (area), row, and column. The read-write operations of DDR can usually approach the theoretical bandwidth only when the addresses are continuous.

[0108] Radar signal processing characteristics: Radar signal processing is generally two-dimensional matrix data. When processing, it is necessary to perform read-write operations in the order of continuous "rows" or continuous "columns" of the matrix. Such a read-write order will inevitably lead to a reduction in the DDR read-write efficiency.

[0109] The DDR read-write method of the "row-column conversion method" proposed by the present invention is to encode the "row" write address as a "column" when the radar signal processing requires a "row" write operation, and at the same time match the data length with the effective bandwidth of the DDR during out-of-order read-write to achieve the purpose of improving the DDR read-write efficiency. The advantage of doing this is to cache multiple input data and perform a single write operation after reaching a certain quantity. In this way, even if the out-of-order write causes a reduction in bandwidth, the number of writes becomes smaller. If the number of writes is matched with the multiple of the bandwidth reduction, the problem of bandwidth reduction caused by out-of-order read-write will be offset by the single write operation of multiple data. Since the write operation is performed in the order of the "column" address, the read operation can be performed in the order of the "row" when reading. The continuous "row" reading can basically reach the theoretical bandwidth. At the same time, when reading data, multiple "columns" of data are read at a single time. Therefore, after multiple reads of the "columns" of data required for radar signal processing, the parallel processing of multiple "columns" of data can be completed.

[0110] The DDR read / write method of the "row-column conversion method" proposed by the present invention can flexibly configure the widths of the "row" and "column" addresses according to the size of the matrix, and can also flexibly configure the degree of parallel processing according to the number of channels of radar signal processing to further improve the signal processing efficiency.

[0111] Embodiment 2

[0112] As Figure 1 shown, the difference between this embodiment and Embodiment 1 is that this embodiment further provides a method for variable-scale parallel processing of radar signals based on a single FPGA, and this method is applied to the variable-scale parallel processing platform of radar signals based on a single FPGA; this method includes:

[0113] After the variable-scale parallel processing platform of radar signals based on a single FPGA is powered on, according to the control information and configuration information sent by the host computer, various basic parameters are configured, and it enters the standby mode to wait for the radar working instruction;

[0114] When receiving the radar working instruction, the variable-scale parallel processing platform of radar signals based on a single FPGA performs the following radar signal processing according to the configured basic parameters:

[0115] According to the digital frequency conversion parameters, N-channel radar echo signals sampled from an external ADC are subjected to digital down-conversion processing to obtain N-channel radar baseband signals;

[0116] According to the DBF parameters and the radar baseband signals, the N-channel radar baseband signals are subjected to digital beamforming to obtain M-channel digital composite signals; both N and M are positive integers, and N is greater than M;

[0117] According to the radar transmission control parameters, radar transmission control is performed; and according to the radar reception control parameters and the M-channel digital composite signals, radar reception control is performed, and the radar received echo signals are sent to the radar signal processing module;

[0118] According to the lengths of the fast Fourier transform FFT and the inverse fast Fourier transform IFFT, the radar received echo signals are subjected to pulse compression processing to obtain the pulse compression processing results and store them in sequence by row; based on the row-column conversion method, column conversion is performed on the pulse compression processing results, and correlation accumulation processing is performed on the pulse compression processing results after column conversion to obtain the final radar signal processing results.

[0119] As a further implementation, this method further includes:

[0120] Target detection is performed based on the final radar signal processing results to obtain target detection results; and the target detection results are transmitted to the host computer.

[0121] As a further implementation, the radar received echo signal is subjected to pulse compression processing to obtain a pulse compression processing result and store it sequentially by row; based on the row-column conversion method, the pulse compression processing result is subjected to column conversion, and the column-converted pulse compression processing result is subjected to correlation accumulation processing to obtain the final radar signal processing result, including:

[0122] Perform FFT operation on the radar received echo signal to obtain a first operation result;

[0123] Perform complex multiplication operation on the first operation result and the matched filtering coefficient to obtain a second operation result;

[0124] Perform IFFT operation on the second operation result to obtain a pulse compression processing result, and store the pulse compression processing result sequentially by row in the DDR memory;

[0125] Based on the row-column conversion method, perform column conversion on the pulse compression processing result to obtain a column-converted pulse compression processing result;

[0126] According to the column-converted pulse compression processing result, read the pulse compression processing result from the DDR memory by column, and perform coherent accumulation operation based on FFT operation to obtain a coherent accumulation operation result as the final radar signal processing result; and store the final radar signal processing result in the DDR memory in a scrambled order.

[0127] Among them, the column conversion of the pulse compression processing result based on the row-column conversion method includes:

[0128] Assume that the pulse compression processing result is an M x N matrix, where M represents the size of the row and N represents the size of the column;

[0129] When writing to the DDR memory, first divide the DDR memory user address into a row area and a column area, and then, according to the read-write characteristics of the DDR memory and the requirements of parallel processing, convert the serially input n pulse compression data with a bit width of x into a data with a bit width of n*x; combined with the radar operation characteristics, convert the row index into a column address when storing the pulse compression data, and convert the column index of the switched pulse compression into a row address for use;

[0130] When reading from the DDR memory, read the data in the pulse compression processing result in the address order.

[0131] Such as Figure 1As shown in the figure, the working process is as follows: After the processing platform is powered on, it will configure various parameters according to the control commands of the host computer, and then enter the standby mode to wait for the radar working instruction; when the radar working instruction is issued, the processing platform will work according to the configured parameters. The working process is as follows: The first step is to perform digital down-conversion on the received signal; the second step is to perform DBF synthesis on the down-converted received signal; the third step is to perform pulse compression operation on the received signal after DBF synthesis; the fourth step is to store the pulse compression operation result in "sequence"; the fifth step is to perform coherent accumulation operation after "out-of-order" reading of the stored pulse compression operation result; the sixth step is to store the coherent accumulation operation result in "out-of-order"; the seventh step is to "sequentially" read the coherent accumulation data, then perform CFAR detection to find the "peak value", calculate the target distance and speed, and then calculate the target angle according to the "peak value" of the sum and difference channels; the eighth step is to report the results of the seventh step according to the user-defined data protocol.

[0132] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A variable-scale parallel processing platform for radar signals based on a single FPGA, characterized in that, the processing platform includes an FPGA chip, and a data protocol processing module, a digital frequency conversion module, a DBF synthesis module, a radar signal transmission module, a radar signal reception module, and a radar signal processing module are integrated on the FPGA chip; The data protocol processing module is used to parse the control information and configuration information sent by the host computer into basic parameters according to the communication protocol and send them to each module; The digital frequency conversion module is used to be configured according to the basic parameters and perform digital down-conversion processing on N radar echo signals sampled from an external ADC to obtain N radar baseband signals; The DBF synthesis module is used to be configured according to the basic parameters and perform digital beam synthesis on N radar baseband signals to obtain M digital synthesis signals; Both N and M are positive integers; The radar signal transmission module is used to be configured according to the basic parameters and perform radar signal transmission control; The radar signal reception module is used to be configured according to the basic parameters, combine M digital synthesis signals to perform radar reception control, and send the radar received echo signal to the radar signal processing module; The radar signal processing module is used to perform pulse compression processing on the radar received echo signal according to the basic parameters, obtain the pulse compression processing result and store it sequentially by row; Perform column conversion on the pulse compression processing result based on the row-column conversion method, and perform correlation accumulation processing on the pulse compression processing result after column conversion to obtain the final radar signal processing result; The pulse compression processing includes: Performing FFT operation on the radar received echo signal to obtain a first operation result; Performing complex multiplication operation on the first operation result and the matched filtering coefficient to obtain a second operation result; Performing IFFT operation on the second operation result to obtain the pulse compression processing result, and storing the pulse compression processing result sequentially by row in the DDR memory; The column conversion of the pulse compression processing result based on the row-column conversion method includes: Assume that the pulse compression processing result is an M x N matrix, where M represents the size of the row and N represents the size of the column; When writing to the DDR memory, first divide the DDR memory user address into a row area and a column area, and then according to the read-write characteristics of the DDR memory and the requirements of parallel processing, convert the serial input n pulse compression data with a bit width of x into a data with a bit width of n*x; when storing the pulse compression data, convert the row index into a column address and use it when switching the column index of the pulse compression to a row address; where n is a positive integer; When reading from the DDR memory, read the data in the pulse compression processing result in the address order; The correlation accumulation processing of the pulse compression processing result after column conversion includes: According to the pulse compression processing results after column conversion, read the pulse compression processing results from the DDR memory column by column, and perform coherent integration operations based on FFT operations to obtain the coherent integration operation results as the final radar signal processing results; and disorderly store the final radar signal processing results in the DDR memory.

2. The variable-scale parallel processing platform for radar signals based on a single FPGA according to claim 1, characterized in that, the basic parameters include digital frequency conversion parameters, DBF parameters, radar transmission control parameters, radar reception control parameters, target detection parameters, and radar signal processing parameters; the digital frequency conversion parameters are used to be sent to the digital frequency conversion module; the DBF parameters are used to be sent to the DBF synthesis module; the radar transmission control parameters are used to be sent to the radar signal transmission module; the radar reception control parameters are used to be sent to the radar signal reception module; the target detection parameters are used to be sent to the target detection module; the radar signal processing parameters are used to be sent to the radar signal processing module.

3. The variable-scale parallel processing platform for radar signals based on a single FPGA according to claim 2, characterized in that, the transmission control parameters include the transmit pulse width and the transmit period; the reception control parameters include the pulse compression length, the number of coherent integration times, and the reception period; the digital frequency conversion parameters include the received intermediate frequency; the target detection parameters include the CFAR average number of points, the CFAR guard number of points, and the CFAR threshold; the radar signal processing parameters include the length of the fast Fourier transform FFT and the length of the inverse fast Fourier transform IFFT.

4. The variable-scale parallel processing platform for radar signals based on a single FPGA according to claim 3, characterized in that, the length of the fast Fourier transform FFT is equal to the pulse compression length; the length of the inverse fast Fourier transform IFFT is equal to the number of coherent integration times.

5. The variable-scale parallel processing platform for radar signals based on a single FPGA according to claim 1, characterized in that, the processing platform further includes a target detection module and a data transmission module integrated on the FPGA chip; The target detection module is used to read the final radar signal processing results from the DDR memory in row order, perform modulus operation on the final radar signal processing results while reading, calculate the average amplitude and the signal peak value within the pulse compression length, and combine the threshold parameters to obtain the target detection threshold; Compare the target detection threshold with the signal peak value to obtain the target detection result; wherein, if the signal peak value is greater than the detection threshold, it is considered that the radar signal is a real target, otherwise the radar signal is not a real target, and the signal peak value is discarded; The data transmission module is used to transmit the target detection result to the host computer.

6. The variable-scale parallel processing method for radar signals based on a single FPGA, characterized in that, the method includes: After the power-on of the radar signal variable-scale parallel processing platform based on a single FPGA, according to the control information and configuration information sent by the host computer, various basic parameters are configured, and it enters the standby mode to wait for the radar operation instruction; When receiving the radar operation instruction, the radar signal variable-scale parallel processing platform based on a single FPGA performs the following radar signal processing according to the configured basic parameters: According to the basic parameters, perform digital down-conversion processing on the N-channel radar echo signals sampled from the external ADC to obtain N-channel radar baseband signals; According to the basic parameters and the radar baseband signals, perform digital beamforming on the N-channel radar baseband signals to obtain M-channel digital composite signals; According to the basic parameters, perform radar transmission control; and according to the basic parameters and the M-channel digital composite signals, perform radar reception control, and send the radar received echo signals to the radar signal processing module; According to the basic parameters, perform pulse compression processing on the radar received echo signals, obtain the pulse compression processing results and store them sequentially by row; perform column conversion on the pulse compression processing results based on the row-column conversion method, and perform correlation accumulation processing on the pulse compression processing results after column conversion to obtain the final radar signal processing results; The performing pulse compression processing on the radar received echo signals, obtaining the pulse compression processing results and storing them sequentially by row; performing column conversion on the pulse compression processing results based on the row-column conversion method, and performing correlation accumulation processing on the pulse compression processing results after column conversion to obtain the final radar signal processing results includes: Perform FFT operation on the radar received echo signals to obtain the first operation result; Perform complex multiplication operation on the first operation result and the matched filtering coefficient to obtain the second operation result; Perform IFFT operation on the second operation result to obtain the pulse compression processing result, and store the pulse compression processing result sequentially by row in the DDR memory; Perform column conversion on the pulse compression processing result based on the row-column conversion method to obtain the pulse compression processing result after column conversion; According to the pulse compression processing result after column conversion, read the pulse compression processing result from the DDR memory by column, and perform coherent accumulation operation based on FFT operation to obtain the coherent accumulation operation result as the final radar signal processing result; and store the final radar signal processing result in the DDR memory in a scrambled order; The performing column conversion on the pulse compression processing result based on the row-column conversion method includes: Assume that the pulse compression processing result is an M x N matrix, where M represents the size of the row and N represents the size of the column; When writing to the DDR memory, first divide the DDR memory user address into a row area and a column area, and then according to the read-write characteristics of the DDR memory and the requirements of parallel processing, convert the serially input n pulse compression data with a bit width of x into a data with a bit width of n*x; when storing the pulse compression data, convert the row index into a column address and use it when switching the column index of the pulse compression to a row address; where n is a positive integer; When performing DDR memory reading, it is sufficient to read the data in the pulse compression processing result in address order.

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