A method for improving overlay precision of an incomplete area of a wafer edge

Abstract

The application discloses a method for improving overlay precision of incomplete area of wafer edge. A plurality of measurement points are taken from each incomplete area of wafer edge, and a plurality of measurement points are taken from two areas adjacent to the incomplete area, so that the total number of measurement points exceeds 13. Then, high-order fitting operation is performed on overlay data of all the taken measurement points to obtain high-order error compensation parameters. The obtained high-order error compensation parameters are fed back to an automatic control system to automatically correct lithography parameters of the incomplete area of wafer edge. The method disclosed by the application takes measurement points from the areas adjacent to the incomplete area, and the measurement points in the incomplete area form measurement data with more than 13 points, which are used for high-order fitting operation to achieve compensation of overlay precision and requirement of lithography process window, so that the overlay precision of the incomplete area of wafer edge is improved, the conductive performance of semiconductor devices is ensured, and the utilization rate of wafers is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for improving the overlay accuracy of incomplete areas at the edge of a wafer. Background Technology

[0002] In the manufacturing process of semiconductor devices, to form multiple conductive patterns on a semiconductor wafer, more than 20 different mask patterns are sequentially superimposed onto the wafer. The photolithography process for forming these mask patterns is a crucial step in semiconductor device manufacturing. To ensure the conductivity of the semiconductor device, each layer's pattern needs to have good overlay accuracy with the other layers. With the development of semiconductor technology, the feature size of circuit patterns continues to shrink, making the control of overlay accuracy increasingly difficult.

[0003] In integrated circuit manufacturing, the relative position between the current layer (photoresist pattern) and the reference layer (substrate pattern) on the wafer describes the deviation of the current pattern relative to the reference pattern along the X and Y directions and the distribution of this deviation on the wafer surface; it is also a key indicator for detecting the quality of the photolithography process.

[0004] Overlay accuracy requirements are not limited to the center of the wafer, but apply to the entire wafer. However, due to the numerous high-temperature, grinding, and thin-film processes involved in integrated circuit manufacturing, significant deviations in overlay accuracy can occur at the wafer's edges. Current photolithography methods for overlay compensation, in addition to performing linear compensation for the entire wafer, also employ higher-order calculations. By using overlay measurements from several points (13 points) or more within each region and applying formulas, higher-order parameters are obtained, thereby compensating for the overlay accuracy in each region.

[0005] Currently, many areas at the edge of a wafer are incomplete, and each area cannot have more than 13 overlay measurement points, thus preventing high-order calculations. The only options are to discard the edge areas or perform linear compensation on them. However, the overlay accuracy obtained through linear compensation cannot meet the requirements of the photolithography process window. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a method for improving the overlay accuracy of incomplete areas at the edge of a wafer, thereby increasing wafer utilization.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] A method for improving the overlay accuracy of incomplete regions at the wafer edge involves taking several measurement points for each incomplete region at the wafer edge, and taking several measurement points in each of the two regions adjacent to the incomplete region, so that the total number of measurement points exceeds 13. Then, the overlay data of all the above-mentioned measurement points are used to perform high-order fitting calculations to obtain high-order error compensation parameters. The obtained high-order error compensation parameters are fed back to the automatic control system to automatically correct the photolithography parameters of the incomplete regions at the wafer edge.

[0009] Preferably, 4-6 measurement points are taken in the incomplete area at the edge of the wafer, and 4-6 measurement points are taken in each of the two areas adjacent to the incomplete area.

[0010] Preferably, six measurement points are taken in the incomplete region at the edge of the wafer, and four measurement points are taken in each of the two regions adjacent to the incomplete region.

[0011] Through the above technical solution, the present invention provides a method for improving the overlay accuracy of incomplete areas at the edge of a wafer. Measurement points are taken in the area adjacent to the incomplete area, and together with the measurement points in the incomplete area, they form more than 13 measurement data points for high-order fitting calculations. This achieves compensation for the overlay accuracy of photolithography and meets the requirements of the photolithography process window, thereby improving the overlay accuracy of incomplete areas at the edge, ensuring the conductivity of semiconductor devices, and improving the utilization rate of the wafer. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0013] Figure 1 This is a schematic diagram of a method for improving the overlay accuracy of incomplete areas at the edge of a wafer, as disclosed in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0015] This invention provides a method for improving the overlay accuracy of incomplete areas at the edge of a wafer, such as... Figure 1 As shown, six measurement points are taken from the incomplete region A at the edge of the wafer, and four measurement points are taken from each of the two adjacent regions B and C. Then, the overlay data of all 14 measurement points are used to perform high-order fitting calculations to obtain high-order error compensation parameters. The obtained high-order error compensation parameters are fed back to the automatic control system to automatically correct the lithography parameters of the incomplete region at the edge of the wafer.

[0016] The automatic control system uses the higher-order error compensation parameters calculated above to automatically correct the parameters of the lithography equipment, thereby improving the overlay accuracy and reducing the overlay error.

[0017] The above methods effectively increase the number of measurement points collected, enabling the acquisition of more error information. In the application of nonlinear compensation technology, more accurate overlay error morphology can be obtained, thus improving the accuracy of feedback correction.

[0018] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for improving the overlay accuracy of incomplete areas at the edge of a wafer, characterized in that, For each incomplete region at the wafer edge, several measurement points are taken, and several measurement points are taken in each of the two regions adjacent to the incomplete region, so that the total number of measurement points exceeds 13. Then, the overlay data of all the above-mentioned measurement points are used to perform high-order fitting calculations to obtain high-order error compensation parameters. The obtained high-order error compensation parameters are fed back to the automatic control system to automatically correct the lithography parameters of the incomplete region at the wafer edge.

2. The method for improving the overlay accuracy of incomplete areas at the edge of a wafer according to claim 1, characterized in that, Take 4-6 measurement points in the incomplete region at the edge of the wafer, and take 4-6 measurement points in each of the two regions adjacent to the incomplete region.

3. The method for improving the overlay accuracy of incomplete areas at the edge of a wafer according to claim 1, characterized in that, Six measurement points are taken in the incomplete region at the edge of the wafer, and four measurement points are taken in each of the two regions adjacent to the incomplete region.

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