Control system, mine control system and method for time-of-flight calibration of a mine fuze

Abstract

The present application relates to the technical field of electronic circuit, particularly relates to a control system, a mine control system and a mine fuze running time calibration method, comprising a clock chip control power-on circuit, a clock chip circuit and a single-chip microcomputer, the clock chip control power-on circuit is used for outputting a power-on signal to the clock chip circuit, the clock chip circuit is used for outputting an interrupt signal to the single-chip microcomputer, and the single-chip microcomputer is used for outputting a control signal to the clock chip control power-on circuit.The mine fuze running time calibration method comprises a control system, under the condition of not relying on external equipment, the mine can check the state of the running time of the hardware clock chip in a time manner during the service process of the mine underwater.Moreover, when the hardware clock chip fails or the running time precision does not meet the requirements, the hardware clock chip can be self-adaptively calibrated, so that the safety timing and mine-destroying timing function and performance of the mine are ensured.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a control system, a mine control system, and a method for calibrating the timekeeping of mine fuses. Background Technology

[0002] Safety timing and mine-extinguishing timing are crucial functions of naval mines. Safety timing ensures that the mine will not mistakenly attack friendly vessels during deployment. Mine-extinguishing timing ensures the mine's self-destruction after combat, guaranteeing the safety of the sea area post-war. Therefore, the accuracy of both safety and mine-extinguishing timing is a vital indicator for naval mines. The timing of safety and mine-extinguishing timing is controlled by the mine's fuse, typically using a hardware clock chip.

[0003] Existing hardware clock chips are prone to failure and their timekeeping accuracy is insufficient. This prevents mines from fulfilling their safety and demining timekeeping functions, posing a threat to nearby vessels during mine deployment. Furthermore, the inability to complete safety timekeeping prevents the mines from entering combat readiness, and the failure to self-destruct after the designated demining timeout poses a threat to post-war maritime security. Therefore, there is an urgent need for a method to restart and calibrate the hardware clock chip in the event of failure. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a control system, a mine control system, and a method for calibrating the timing of mine fuses, which solves the problems of hardware clock chips in the prior art being prone to failure and having insufficient timing accuracy, mines being unable to perform the functions of safe timing and mine-extinguishing timing, posing a threat to nearby ships when mines are laid, or failing to complete safe timing and thus being unable to enter combat status, and failing to self-destruct after the specified mine-extinguishing timing, threatening the safety of the sea area after the war.

[0005] To achieve the above and other related objectives, the present invention provides a control system, including a clock chip control power-on circuit, a clock chip circuit, and a microcontroller, wherein:

[0006] The clock chip control power-on circuit is used to output a power-on signal to the clock chip circuit.

[0007] A clock chip circuit is used to output an interrupt signal to the microcontroller;

[0008] The microcontroller is used to output control signals to the clock chip to control the power-on circuit.

[0009] In one embodiment of the present invention, the clock chip control power-on circuit includes:

[0010] The voltage regulator chip has its signal input terminals connected to one end of a first capacitor, one end of a second capacitor, and a power supply, and is connected to the clock chip circuit through the power supply. The other ends of the first capacitor and the second capacitor are grounded.

[0011] The signal output terminal of the voltage regulator chip is connected to the power supply and one end of the fourth capacitor, respectively. The other end of the fourth capacitor is connected to one end of the third capacitor and grounded. The other end of the third capacitor is grounded.

[0012] The enable pin of the voltage regulator chip is connected to the microcontroller via a first resistor.

[0013] In one embodiment of the present invention, the clock chip circuit includes:

[0014] A clock chip, wherein its disconnected pin is connected to the microcontroller and one end of the second resistor, the other end of the second resistor is connected to the clock chip's power supply pin, one end of the fifth capacitor and the operating power supply, and the other end of the fifth capacitor is grounded;

[0015] The SCL and SDA pins of the clock chip are connected to one end of the third resistor and one end of the fourth resistor, respectively, and the other ends of the third resistor and the fourth resistor are connected to the power supply.

[0016] In one embodiment of the present invention, the voltage regulator chip is model SGM2019-3.0YN5G, and the clock chip is model JYC3231.

[0017] The present invention also provides a mine control system, including the control system described above.

[0018] The present invention also provides a method for calibrating the timekeeping of a mine fuze, comprising the aforementioned control system, wherein the method for calibrating the timekeeping of a mine fuze includes:

[0019] S1. Set parameters to enable hardware and software timekeeping;

[0020] S2. Determine whether the clock chip circuit alarms. If so, determine whether the hardware timekeeping meets the set error range. If it does, the hardware timekeeping is accurate. If it does not, the hardware timekeeping is invalid. Pull down the power-on control line of the clock chip control power-on circuit and power on again after a set delay.

[0021] S3. Calculate the remaining safe time of the hardware, reset the alarm time of the clock chip circuit, and enable the hardware to keep running.

[0022] S4. If the software timekeeping reaches the upper limit of the timekeeping range and the clock chip circuit still does not give an alarm, the hardware timekeeping fails. Pull down the power-on control line of the clock chip power-on control circuit and power on again after a set delay.

[0023] S5. Determine whether the hardware's safe time has been reached. If yes, end the safe timekeeping calibration. If not, return to step S2.

[0024] In one embodiment of the present invention, the setting parameters in step S1, enabling hardware timekeeping and software timekeeping, include:

[0025] S11, Initialize parameters;

[0026] S12. Set the hardware to the alarm count of the control system;

[0027] S13. The software setting is the timing counter used for the mine fuse timing calibration method;

[0028] S14. The clock chip control power-on circuit outputs a power-on signal to the clock chip circuit.

[0029] S15. Set the initial time and alarm time of the clock chip circuit;

[0030] S16. Set and start the timer in the microcontroller, and simultaneously start the hardware timekeeping and software timekeeping.

[0031] In one embodiment of the present invention, the alarm count of the control system is set to 10 times in step S12.

[0032] In one embodiment of the present invention, the set time in steps S2 and S4 is 250ms.

[0033] As described above, the control system, mine control system, and method for calibrating the travel time of mine fuses of the present invention have the following beneficial effects:

[0034] The mine fuse timing calibration method of the present invention includes a control system that enables the mine to periodically check the timing status of the hardware clock chip during underwater service without relying on external equipment.

[0035] The mine fuse timing calibration method of the present invention solves the problem of adaptive calibration of the hardware clock chip when the hardware clock chip fails or the timing accuracy does not meet the requirements, thus ensuring the safety timing and extinguishing timing functions and performance of the mine.

[0036] The mine fuse timing calibration method of the present invention can restart the hardware clock chip and calibrate the timing of the hardware clock chip in the event of hardware clock chip failure. It can also self-destruct after the specified timeout period for mine extinguishing, thus ensuring the safety of the sea area after war. Attached Figure Description

[0037] Figure 1 This is a structural diagram of a control system provided in an embodiment of this application.

[0038] Figure 2 This is a circuit diagram of a clock chip control power-on circuit for a control system provided in an embodiment of this application.

[0039] Figure 3 This is a circuit schematic diagram of a clock chip circuit for a control system provided in an embodiment of this application.

[0040] Figure 4 This is a flowchart illustrating a method for calibrating the travel time of a mine fuse, as provided in an embodiment of this application.

[0041] Figure 5 This is a flowchart of step S1 of a method for calibrating the travel time of a mine fuse, provided in an embodiment of this application.

[0042] Component designation explanation

[0043] 10. Clock chip controls power-on circuit

[0044] 20 Clock Chip Circuit

[0045] 30 microcontrollers

[0046] D1 voltage regulator chip

[0047] C1 First capacitor

[0048] C2, the second capacitor

[0049] C3 Third capacitor

[0050] C4 Fourth capacitor

[0051] C5, the fifth capacitor

[0052] R1 is the first resistor.

[0053] R1 is the second resistor.

[0054] R1 is the third resistor.

[0055] R1 Fourth resistor

[0056] U5 clock chip Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0058] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0059] Please see Figure 1 , Figure 1 This is a structural diagram of a control system provided in an embodiment of this application. The present invention provides a control system including a clock chip control power-on circuit 10, a clock chip circuit 20, and a microcontroller 30, wherein: the clock chip control power-on circuit 10 is used to output a power-on signal to the clock chip circuit 20; the clock chip circuit 20 is used to output an interrupt signal to the microcontroller 30; and the microcontroller 30 is used to output a control signal to the clock chip control power-on circuit 10.

[0060] Please see Figure 2 , Figure 2 This application provides a circuit diagram of a clock chip control power-on circuit for a control system. The clock chip control power-on circuit 10 includes: a voltage regulator chip D1, whose signal input terminals are respectively connected to one end of a first capacitor C1, one end of a second capacitor C2, and a power supply, and connected to the clock chip circuit 20 through the power supply; the other ends of the first capacitor C1 and the second capacitor C2 are grounded; the signal output terminals of the voltage regulator chip D1 are respectively connected to the power supply and one end of a fourth capacitor C4, the other end of the fourth capacitor C4 is connected to one end of a third capacitor C3 and grounded, and the other end of the third capacitor C3 is grounded; the enable terminal of the voltage regulator chip D1 is connected to the microcontroller 30 through a first resistor R1.

[0061] Specifically, the working principle of the clock chip control power-on circuit 10 of the present invention includes: when the software detects that the timing state of the hardware clock chip is abnormal, the IO port line of the microcontroller 30, which is the power-on control port line of the clock chip control power-on circuit 10, controls the voltage regulator chip D1. The voltage regulator chip D1 is an SGM2019-3.0YN5G manufactured by Shanghai Saint-Gobain, which regulates the working power supply 3.6V to the power supply VCC, thereby powering on the hardware clock chip.

[0062] Please see Figure 3 , Figure 3 This application provides a circuit diagram of a clock chip circuit for a control system. The clock chip circuit 20 includes: a clock chip U5, whose interrupted pin is connected to the microcontroller 30 and one end of a second resistor R2; the other end of the second resistor R2 is connected to the power supply pin of the clock chip U5, one end of a fifth capacitor C5, and the operating power supply; the other end of the fifth capacitor C5 is grounded; the SCL pin and SDA pin of the clock chip U5 are respectively connected to one end of a third resistor R3 and one end of a fourth resistor R4; the other ends of the third resistor R3 and the other ends of the fourth resistor R4 are connected to the operating power supply.

[0063] Specifically, the first capacitor C1 and the third capacitor C3 are 10uF power supply filter capacitors, the second capacitor C2, the fourth capacitor C4, and the fifth capacitor C5 are 0.1uF power supply filter capacitors, the first resistor R1 is a 0-ohm switching resistor, and the third resistor R3 and the fourth resistor R4 are 10-kiloohm pull-up resistors. The voltage regulator chip D1 converts the 3.6V operating power supply to the clock chip's 3.3V power supply, thereby powering on the clock chip. The clock chip U5, taking the JYC3231 manufactured by the China Electronics Technology Group Corporation (CETC) 54 Institute as an example, is a high-precision I2C interface real-time clock (RTC) that can maintain information on seconds, minutes, hours, day of the week, date, month, and year, and provides leap year compensation valid until 2100 to provide accurate clocking. The INT pin can generate an interrupt signal determined by alarm conditions and output it to the microcontroller 30. The maximum alarm time of the clock chip U5 is 30 days, but in this invention, the maximum alarm time is 1 day. Taking a safety timer set to 10 days and a lightning suppression timer set to 30 days as an example, the safety timer will trigger 10 alarms. Since the safety timer and the lightning suppression timer start at the same time, after the safety timer ends, the lightning suppression timer will have 20 days remaining after subtracting the safety timer timer. In other words, the lightning suppression timer will trigger 20 alarms.

[0064] The present invention also provides a mine control system, including the above-described control system.

[0065] Please see Figure 4 , Figure 4This invention provides a flowchart of a method for calibrating the timekeeping of a mine fuze, as illustrated in an embodiment of this application. The invention also provides a method for calibrating the timekeeping of a mine fuze, including the aforementioned control system. The method for calibrating the timekeeping of a mine fuze includes:

[0066] Step S1: Set parameters and enable hardware and software timekeeping.

[0067] Step S2: Determine whether the clock chip circuit 20 alarms. If so, determine whether the hardware timekeeping meets the set error range. If it does, the hardware timekeeping is accurate. If it does not, the hardware timekeeping is invalid. Pull down the power-on control line of the clock chip control power-on circuit 10 and power on again after a set delay.

[0068] Step S3: Calculate the remaining safe time of the hardware, reset the alarm time of the clock chip circuit 20, and start the hardware timekeeping.

[0069] Step S4: Determine whether the software timekeeping has reached the upper limit of the timekeeping range, and if the clock chip circuit 20 still does not give an alarm, then the hardware timekeeping fails. Pull down the power-on control line of the clock chip control power-on circuit 10, and power on again after a set delay.

[0070] Step S5: Determine whether the hardware's safe time has been reached. If yes, end the safe timekeeping calibration; otherwise, return to step S2.

[0071] Please see Figure 5 , Figure 5 This application provides a flowchart of step S1 of a time calibration method for mine fuses. The setting parameters in step S1, enabling both hardware and software timekeeping, include:

[0072] Step S11: Initialize parameters.

[0073] Step S12: Set the hardware to the alarm count of the control system.

[0074] Step S13: Set the software to be used for the timekeeping calibration method of mine fuses.

[0075] Step S14: The clock chip control power-on circuit 10 outputs a power-on signal to the clock chip circuit 20.

[0076] Step S15: Set the initial time and alarm time of the clock chip circuit 20.

[0077] Step S16: Set and enable the timer in the microcontroller 30, and simultaneously enable both hardware and software timekeeping.

[0078] The time calibration method for mine fuses of the present invention can be applied to mine control software.

[0079] Specifically, this invention can, but is not limited to, setting the safety timer to 10 days, wherein the detection and calibration method for the lightning suppression timer is consistent with the detection and calibration method for the safety timer. The software process begins by initializing and calculating the preset safety timer parameters. First, the hardware is set to the alarm count of the control system: following the usage of the JYC3231 clock chip, an alarm is triggered once a day, therefore the alarm count is 10. If set to 10 days and 5 hours, then the alarm count is 11. The first 10 days have 10 alarms, and the last 5 hours have 11 alarms in total. Next, the software timer counts. Taking the MSP430F1611 microcontroller as an example, the TimeA register is used to set an interrupt every 125ms. Therefore, 8 interrupt responses equal 1 second. The software count corresponding to the 10-day safety timer is 10 × 24 × 60 × 60 × 8 = 6912000, denoted as T.

[0080] After the safety timing parameters are calculated, the JYC3231 clock chip is powered on. Based on the calculated safety timing parameters, the JYC3231 clock chip is configured, and the timer of the microcontroller 30 is simultaneously set and enabled, with both software and hardware timekeeping enabled. When the clock chip issues an alarm signal, it is compared with the software timekeeping counter to determine if the software timekeeping has reached the upper limit of the timekeeping range. If the software timekeeping error is ±(5+t / 1000)s, where t is the set time in seconds, and the software timekeeping range is met, the hardware timekeeping is considered accurate. If the software timekeeping range is not met, the hardware timekeeping is considered to have failed. The clock chip's power-on control line is pulled low, and after a 250ms delay, the power is re-energized. By calculating the remaining time, the alarm time of the JYC3231 clock chip is reset, and the hardware timekeeping is enabled. Similarly, if the software timekeeping range upper limit is exceeded each day and the JYC3231 clock chip still does not issue an alarm signal, the hardware timekeeping is considered to have failed, and the operation steps are the same as above. Until the safety timeout period ends, the safety timeout waiting period ends and the safety timeout processing function is entered, ending the safety timeout calibration.

[0081] In summary, the mine fuse timing calibration method of the present invention includes a control system that enables the mine to periodically check the timing status of the hardware clock chip during underwater service without relying on external equipment. This solves the problem of adaptive calibration of the hardware clock chip when it fails or its timing accuracy does not meet requirements, thus ensuring the mine's safe timing and mine extinguishing timing functions and performance.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A control system, characterized in that, It includes a clock chip control power-on circuit (10), a clock chip circuit (20), and a microcontroller (30), wherein: The clock chip control power-on circuit (10) is used to output a power-on signal to the clock chip circuit (20). Clock chip circuit (20) is used to output an interrupt signal to the microcontroller (30). The microcontroller (30) is used to output control signals to the clock chip to control the power-on circuit (10). The clock chip control power-on circuit (10) includes: The voltage regulator chip (D1) has its signal input terminals connected to one end of the first capacitor (C1), one end of the second capacitor (C2), and the power supply, respectively, and is connected to the clock chip circuit (20) through the power supply. The other ends of the first capacitor (C1) and the second capacitor (C2) are grounded. The signal output terminal of the voltage regulator chip (D1) is connected to the power supply and one end of the fourth capacitor (C4), respectively. The other end of the fourth capacitor (C4) is connected to one end of the third capacitor (C3) and grounded. The other end of the third capacitor (C3) is grounded. The enable terminal of the voltage regulator chip (D1) is connected to the microcontroller (30) through the first resistor (R1). The clock chip circuit (20) includes: The clock chip (U5) has an interrupted pin connected to the microcontroller (30) and one end of the second resistor (R2). The other end of the second resistor (R2) is connected to the power supply pin of the clock chip (U5), one end of the fifth capacitor (C5), and the operating power supply. The other end of the fifth capacitor (C5) is grounded. The SCL and SDA pins of the clock chip (U5) are connected to one end of the third resistor (R3) and one end of the fourth resistor (R4), respectively. The other ends of the third resistor (R3) and the fourth resistor (R4) are connected to the power supply.

2. The control system according to claim 1, characterized in that: The voltage regulator chip (D1) is model SGM2019-3.0YN5G, and the clock chip (U5) is model JYC3231.

3. A mine control system, characterized in that: Includes the control system described in claim 1 or 2.

4. A method for calibrating the travel time of a mine fuse, characterized in that, Including the control system as described in claim 1 or 2, the method for calibrating the travel time of a mine fuse includes: S1. Set parameters to enable hardware and software timekeeping; S2. Determine whether the clock chip circuit (20) alarms. If so, determine whether the hardware timekeeping meets the set error range. If it does, the hardware timekeeping is accurate. If it does not, the hardware timekeeping fails. Pull down the power-on control line of the clock chip control power-on circuit (10) and power on again after a set delay. S3. Calculate the remaining time of the hardware's safety time, reset the alarm time of the clock chip circuit (20), and enable the hardware to run. S4. If the software timekeeping reaches the upper limit of the timekeeping range and the clock chip circuit (20) still does not give an alarm, the hardware timekeeping fails. Pull down the power-on control line of the clock chip control power-on circuit (10), and power on again after a set delay. S5. Determine whether the hardware's safe time has been reached. If yes, end the safe timekeeping calibration. If not, return to step S2.

5. The method for calibrating the travel time of a mine fuse according to claim 4, characterized in that, The setting parameters in step S1, enabling both hardware and software timekeeping, include: S11, Initialize parameters; S12. Set the hardware to the alarm count of the control system; S13. The software setting is the timing counter used for the mine fuse timing calibration method; S14. The clock chip control power-on circuit (10) outputs a power-on signal to the clock chip circuit (20). S15. Set the initial time and alarm time of the clock chip circuit (20); S16. Set and start the timer in the microcontroller (30), and start the hardware timer and software timer simultaneously.

6. The method for calibrating the travel time of a mine fuse according to claim 5, characterized in that: In step S12, the alarm count of the control system is set to 10.

7. The method for calibrating the travel time of a mine fuse according to claim 4, characterized in that: The set time in steps S2 and S4 is 250ms.

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