Reset and safety state logic generation in dual power flow devices

Abstract

This disclosure relates to reset and safety state logic generation in a dual-power-flow device. An electronic device includes: a first power domain; a second power domain; a third power domain, wherein during power-on, the third, second, and first power domains are configured to be sequentially powered, and wherein during standby exit, the first, second, and third power domains are configured to be sequentially powered; providing isolated paths for controlled signal transmission between the first, second, and third power domains, wherein each isolated path includes isolation circuitry between an input power domain and an output power domain of the isolated path; and control circuitry in the first power domain, wherein for each isolated path, the control circuitry is configured to generate isolation control signals for the isolation circuitry, wherein the isolation circuitry is configured to enable or disable signal transmission along the isolated path.

Description

[0001] Cross-references and priority requirements

[0002] This application is a continuation-into-file of U.S. Patent Application No. 17 / 537,010, filed November 29, 2021, entitled “Reset and Safe State Logic Generation in Dual Power Flow Devices,” which is incorporated herein by reference. Technical Field

[0003] The present invention generally relates to electronic circuits, and in certain embodiments to circuits for generating reset and isolation control signals in an electronic device having multiple power domains. Background Technology

[0004] Electronic devices such as computers, mobile phones, and home appliances can have multiple power domains for energy saving. For example, an electronic device may have a standby power domain, a low-power power domain, and a run mode power domain. The standby power domain, with its extremely low power consumption, may remain on after the electronic device is turned on, keeping it in standby mode and waiting for user input to exit. The low-power power domain can perform certain functions with reduced power consumption in a low-power mode. The run mode power domain can be used to perform full-power operation in run mode when the electronic device requires maximum performance. Electronic devices can switch between different operating modes (such as standby mode, low-power mode, and run mode) to achieve energy efficiency.

[0005] While providing energy efficiency, multiple power domains present certain challenges to the design of electronic devices. For example, since not all power domains are powered up simultaneously, signals from or into unpowered power domains may be unpredictable. Therefore, isolation paths may need to be implemented between multiple power domains to provide isolated data paths. Isolation paths are designed to allow digital signal transmission when both power domains on either side of the isolation path are powered (e.g., powered on), and to disable digital signal transmission when at least one power domain on either side of the isolation path is not powered (e.g., powered off). Furthermore, digital interfaces may need to be implemented in multiple power domains to correctly interact with the isolation paths in different operating modes. Summary of the Invention

[0006] In some embodiments, an electronic device having dual power flow modes includes: a first power domain; a second power domain; and a third power domain, wherein in a first power flow mode during power-on, the third power domain, the second power domain, and the first power domain are configured to be sequentially powered on, wherein in a second power flow mode during standby of the electronic device, the first power domain remains powered on, and the second and third power domains are configured to be sequentially powered on; and an isolation path for controlled signal transmission is provided between the first power domain, the second power domain, and the third power domain, wherein each isolation path includes an input power domain coupled to the isolation path and a third power domain of the isolation path. The circuitry includes an isolation circuit between the output power domains, two power domains in the first, second, and third power domains connected by an isolation path, and a reset and secure state logic generation (RSSLG) circuit in the first power domain. For each isolation path, the RSSLG circuitry is configured to generate an isolation control signal for the isolation circuitry in the isolation path, wherein the isolation circuitry is configured to allow signal transmission along the isolation path from the input power domain to the output power domain when the isolation control signal has a first value, and is configured to disable signal transmission along the isolation path when the isolation control signal has a second value.

[0007] In some embodiments, an electronic device includes: a first power domain, a second power domain, and a third power domain, wherein during a power-on process of the electronic device, the third power domain, the second power domain, and the first power domain are sequentially powered on, and wherein during a standby exit process of the electronic device, the first power domain, the second power domain, and the third power domain are sequentially powered on; isolation paths between the first and second power domains, between the second and third power domains, and between the first and third power domains, wherein each isolation path includes an isolation circuit controlled by an isolation control signal, wherein for each isolation path, when the isolation control signal has a first value, the isolation circuit allows digital signals to pass through the isolation circuit from the isolation path. The input power domain of the isolated path is transmitted to the output power domain of the isolated path, and the isolation circuit prevents digital signals from being transmitted through the isolation circuit when the isolation control signal has a second value, wherein the input power domain and the output power domain are two of the first, second, and third power domains connected to the isolated path; and a reset and secure state logic generation (RSSLG) circuit in the first power domain, wherein for each isolated path, the RSSLG circuit is configured to generate an isolation control signal with a first value when at least the input power domain and the output power domain of the isolated path are powered on, and is configured to generate an isolation control signal with a second value when the input power domain or the output power domain of the isolated path is powered off.

[0008] In some embodiments, an electronic device includes: a standby (STBY) power domain, a low power (LP) power domain, and an operating mode (RM) power domain, wherein in a first power flow mode of the electronic device, the RM power domain, the LP power domain, and the STBY power domain are sequentially powered, and wherein in a second power flow mode of the electronic device, the STBY power domain remains powered while the LP power domain and the RM power domain are sequentially powered; isolation paths between the STBY and LP power domains, between the LP and RM power domains, and between the STBY and RM power domains, wherein each isolation path includes an isolation circuit and provides a data path having isolation functionality between an input power domain and an output power domain of the isolation path, wherein the input power domain and the output power domain are connected to the isolation path. The power domain of the electronic device in the path, wherein for each isolation path, when the isolation control signal of the isolation circuit has a first value, the isolation circuit allows digital signals to be transmitted from the input power domain of the isolation path to the output power domain of the isolation path, and when the isolation control signal has a second value, the isolation circuit prevents digital signals from being transmitted from the input power domain of the isolation path to the output power domain of the isolation path; and a reset and secure state logic generation (RSSLG) circuit in the STBY power domain, wherein for each isolation path, the RSSLG circuit is configured to generate an isolation control signal with a first value when at least the input power domain and the output power domain of the isolation path are powered on, and is configured to generate an isolation control signal with a second value when either the input power domain or the output power domain of the isolation path is powered off. Attached Figure Description

[0009] Details of one or more embodiments of the present invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will be apparent from the description, the drawings, and the claims. In the drawings, the same reference numerals generally designate the same components in the various views and are generally not restated for the sake of brevity. For a more complete understanding of the invention, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 The illustration shows a block diagram of an electronic device having multiple power domains in one embodiment;

[0011] Figures 2A-2F The illustration shows one embodiment. Figure 1 Various isolation paths for electronic devices;

[0012] Figure 3 The illustration shows one embodiment. Figures 2A-2F Isolation circuits for various isolation paths in the circuit;

[0013] Figure 4 The illustration shows another embodiment. Figures 2A-2FIsolation circuits for various isolation paths in the circuit;

[0014] Figure 5 The illustration shows one embodiment. Figure 1 Block diagram of the reset and security state logic generation (RSSLG) circuit for electronic devices;

[0015] Figure 6 The diagram shows Figure 1 A timing diagram of an electronic device in one embodiment; and

[0016] Figure 7 The diagram shows Figure 1 Timing diagram of an electronic device in another embodiment. Detailed Implementation

[0017] The following discusses in detail the fabrication and use of the presently preferred embodiments. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0018] The invention will be described with reference to exemplary embodiments in a specific context, namely, circuitry for generating reset and isolation control signals in an electronic device having multiple power domains and dual power flow modes.

[0019] Figure 1 The illustration shows a block diagram of an electronic device 100 having multiple power domains in one embodiment. The electronic device 100 can be, for example, a computer, a mobile phone, a home appliance, etc. Figure 1 As illustrated, electronic device 100 includes three power domains, such as a first power domain 101, a second power domain 103, and a third power domain 105. In the illustrated example, the first power domain 101 is a standby (STBY) power domain and may be referred to as the standby / always-on power domain, or power domain PD0, in the discussion herein. The second power domain 103 is a low-power (LP) power domain and may be referred to as the low-power / smart power domain, or power domain PD1. The third power domain 105 is an operating mode power domain and may be referred to as power domain PD2. The first power domain 101, the second power domain 103, and the third power domain 105 may be collectively referred to as the power domains of electronic device 100.

[0020] In some embodiments, each power domain (e.g., 101, 103, and 105) is powered by one or more power supplies, such as switch-mode power supplies (SMPS). Examples of SMPS include buck converters, boost converters, and so on. The power supply for each power domain may be formed within its respective power domain, and the power supplies in all power domains (e.g., 101, 103, and 105) may be controlled by a controller of electronic device 100. The power supply for each power domain may include one or more power switches, wherein the power switches(s) are alternately turned on and off by corresponding control signals (e.g., pulse width modulation (PWM) control signals) to provide a power supply voltage to the power domain. When its power is turned on (e.g., a power supply voltage is provided), the power domain is referred to as being powered on or supplied with power. When the power switches(s)(s) are turned off (e.g., no longer switching between on and off states, but remaining in the off state), the power is turned off, and the corresponding power domain is referred to as being de-powered or not supplied with power.

[0021] In some embodiments, each power domain (e.g., 101, 103, 105) includes its corresponding electrical components and / or circuitry that perform certain functions. For example, a standby power domain 101 with very low power consumption may be powered on in the standby mode of the electronic device 100, while the low-power power domain 103 and the operating mode power domain 105 are powered off to save energy. In some embodiments, the standby power domain 101 monitors user input during standby mode and, in response to detected user input, exits standby mode and enters, for example, a low-power mode or an operating mode. The low-power power domain 103 may perform certain functions with reduced power consumption in low-power mode. In low-power power mode, standby power domain 101 and low-power power domain 103 are powered on, while the operating mode power domain 105 is powered off. When maximum performance of the electronic device 100 is required, the operating mode power domain 105 may be used to perform full-power operation in operating mode. The electronic device 100 may exit low-power mode to enter operating mode. In the operating mode, the standby power domain 101, the low power domain 103, and the operating mode power domain 105 are all powered on.

[0022] Electronic device 100 is a device with dual power flow modes. For example, during the power-on period of electronic device 100 or during the reset period of electronic device 100, the power flow in electronic device 100 (e.g., a startup sequence or power-on sequence) occurs in the first power flow direction, and when electronic device 100 exits standby mode and enters operating mode, the power flow occurs in the second power flow direction. Figure 1The diagram illustrates a first power flow path 107 (e.g., 107A, 107B) in the first power flow direction and a second power flow path 109 (e.g., 109A, 109B) in the second power flow direction. In the first power flow direction, the third power domain 105, the second power domain 103, and the first power domain 101 are sequentially powered on during power-on (or reset). After power-on (or reset), the third power domain 105 is de-powered when the electronic device 100 enters a low-power mode. Furthermore, the second power domain 103 is also de-powered when the electronic device 100 enters a standby mode. When the electronic device 100 exits the standby mode to enter the operating mode, power flow occurs in the second power flow direction, where only the first power domain 101 is initially powered on (e.g., in standby mode), then the second power domain 103 is powered on during standby exit, and subsequently, the third power domain 105 is powered on during low-power mode exit to enter the operating mode.

[0023] Figure 1 Further illustrations show multiple isolation paths 111, 112, 113, 114, 115, and 116. Each isolation path electrically couples two power domains (e.g., 101 and 103, 103 and 105, or 101 and 105) and provides a controlled data path between the two power domains. The controlled data path allows digital signal transmission within the isolation path when the isolation control signal of the isolation path has a first value (e.g., a logic high value) that allows (e.g., enables) digital signal transmission. When the isolation control signal has a second value (e.g., a logic low value), the controlled data path blocks (e.g., disallows, disables, prohibits) digital signal transmission within the isolation path. In the illustrated embodiment, each isolation path is a unidirectional path that, when enabled by the corresponding isolation control signal, allows digital signals to be transmitted from the input power domain of the isolation path to the output power domain of the isolation path. Here, the input power domain refers to the power domain on which digital signals are transmitted to the isolation path, while the output power domain refers to the power domain on which digital signals are received from the isolation path. For example, isolation path 111 provides a controlled data path between third power domain 105 and first power domain 101. The arrows on isolation path 111 indicate the direction of data transmission, and therefore, third power domain 105 is the input power domain of isolation path 111, and first power domain 101 is the output power domain of isolation path 111. Note that in some embodiments, each isolation path may be a data bus carrying one or more parallel digital signals, and isolation control signals for each isolation path enable or disable all digital signal transmissions on the data bus.

[0024] Since power domains 101, 103, and 105 may not be powered on simultaneously, signals transmitted to or received in an unpowered power domain may be at unknown voltage levels and are therefore unpredictable. In some embodiments, isolation paths 111, 112, 113, 114, 115, and 116 ensure signal integrity and proper operation of electronic device 100 by disabling signal transmission when the input or output power domain of the isolation path is not powered and by allowing signal transmission only when at least the input and output power domains of the isolation path are powered. In the discussion herein, isolation paths 111, 112, 113, 114, 115, and 116 may be referred to as first isolation path 111, second isolation path 112, third isolation path 113, fourth isolation path 114, fifth isolation path 115, and sixth isolation path 116, respectively.

[0025] Figure 1 The isolation control signals for controlling the isolation path are further illustrated (in...). Figure 1 (It is marked as ISO_CTRLS). Please note that, for simplicity, Figure 1 The diagram illustrates each pair of isolated paths (e.g., 111 and 112, 113 and 114, or 115 and 116) controlled by an isolation control signal, but it should be understood that each isolated path is controlled by its own isolation control signal, as shown in the reference below. Figures 2A-2F The above discussion. Note that in the illustrated embodiment, all isolation control signals are generated by the first power domain 101, and no isolation control signals are generated by the second power domain 103 or the third power domain 105.

[0026] Figures 2A-2F The illustration shows one embodiment. Figure 1 Various isolation paths for electronic devices 100. Specifically, Figures 2A-2F The diagrams show the diagrams respectively. Figure 1 The isolation paths 111-116 each include an input signal path, an output signal path, and an isolation circuit 121 between the input signal path and the output signal path. The isolation circuit 121 in each isolation path is controlled by a corresponding isolation control signal. For example, Figure 2A The diagram shows Figure 1 An isolation path 111 provides a controlled data path from power domain PD2 to power domain PD0. Input signal path 111A is coupled to the input power domain (e.g., PD2) to receive signals from the input power domain. Output signal path 111B is coupled to the output power domain (e.g., PD0). For illustrative and ease-of-understanding purposes, Figure 2A The isolation circuit 121 in the diagram is illustrated as a buffer. The isolation circuit 121 can be as follows: Figure 3 The AND gate shown in the figure or as shown Figure 4 The diagram shows an OR gate with an inverting input terminal. The isolation control signal 131 for the isolation circuit 121 is... Figure 2A The signal is labeled ISO_CTRL1 and applied to the control terminal of the isolation circuit 121. Depending on the value of the isolation control signal 131, the isolation circuit 121 can transmit the signal from the input signal path 111A to the output signal path 111B, or disconnect the input signal path 111A from the output signal path 111B.

[0027] Figure 2A The example illustrates an input signal path (e.g., 111A) and an output signal path (e.g., 111B) in isolation path 111. Those skilled in the art will readily appreciate that isolation path 111 may include multiple parallel signal paths, in which case each signal path may include isolation circuitry 121, and isolation control signal 131 may be used to control all isolation circuitry 121 in isolation path 111. Figures 2B-2F Isolation path and Figure 2A Similar to the previous examples, the details will not be repeated here. In some embodiments, the output signal of each isolation path is stored in one or more buffers located in the output power domain of the isolation path.

[0028] Figure 3 The illustration shows a method for use in one embodiment. Figures 2A-2F The isolation circuit 303 for various isolation paths. In Figure 3 In the example, isolation path 300 is illustrated, which includes input signal path 301A, output signal path 301B and isolation circuit 303. Figure 3 In the example, the isolation circuit 303 is an AND gate, wherein the first input terminal of the AND gate 303 is coupled to an isolation control signal (labeled ISO_CTRL). n The AND gate 303 is coupled to the second input terminal of the AND gate 303 to the input signal path 301A. The output terminal of the AND gate 303 is coupled to the output signal path 301B. Those skilled in the art will readily understand that when the isolation control signal has a logic low value, the AND gate 303 is closed, thereby forcing the output signal of the AND gate 303 to a fixed, known state (e.g., a logic low value) and disabling signal transmission through the isolation path. When the isolation control signal has a logic high value, the AND gate 303 is turned on, thereby allowing signal transmission from the input signal path 301A to the output signal path 301B. Figure 3 The isolation path 300 utilizes an AND gate as an isolation circuit 303 and the isolation control signal ISO_CTRL. n (n = 1, 2, ..., or 6) can be used as Figures 2A-2F The nth isolation path in isolation paths 111-116.

[0029] Figure 4 The illustration shows another embodiment. Figures 2A-2F The isolation circuit 305 for various isolation paths. In Figure 4 In the example, isolation path 400 is illustrated, which includes input signal path 301A, output signal path 301B and isolation circuit 305. Figure 4 The isolation circuit 305 in the example is an OR gate with an inverting terminal and a non-inverting terminal, wherein the inverting input of the OR gate 305 is coupled to an isolation control signal (labeled ISO_CTRL). n The non-inverting input terminal of OR gate 305 is coupled to input signal path 301A. The output terminal of OR gate 305 is coupled to output signal path 301B. Those skilled in the art will readily understand that when the isolation control signal has a logic low value, the corresponding input of OR gate 305 (after being inverted at the inverting input terminal) is logic high, which forces the output signal gate 305 to a fixed, known state (e.g., a logic high value), thereby disabling signal transmission through the isolation path. When the isolation control signal has a logic high value, OR gate 305 is turned on, thereby allowing signal transmission from input signal path 301A to output signal path 301B. Figure 4 The isolation path 400 utilizes an OR gate as an isolation circuit 305 and utilizes the isolation control signal ISO_CTRL. n (n = 1, 2, ..., or 6) can be used as Figures 2A-2F The nth isolation path in isolation paths 111-116.

[0030] Figure 5 The illustration shows one embodiment. Figure 1 A block diagram of the reset and security state logic generation (RSSLG) circuit 200 of the electronic device 100. The RSSLG circuit 200 is implemented in the first power domain 101 (e.g., as part of the circuitry of the first power domain 101) and is used to provide... Figure 1 The isolation paths 111-116 generate isolation control signals (e.g., Figures 2A-2F (Referring to pages 131-136). Please note that, for simplicity, Figure 5 Not all features of the RSSLG circuit 200 are illustrated.

[0031] like Figure 5 As shown in the diagram, the RSSLG circuit 200 includes a power management control circuit 210, which in turn includes circuit 215 and multiple circuits 219. n Where n = 1, 2, ..., 6. The RSSLG circuit 200 also includes multiple circuits 217 coupled to the power management control circuit 210.n Where n = 1, 2, ..., 6. For simplicity, Figure 5 Only circuit 219 is shown in the diagram. n One of the circuits 217 n one.

[0032] In the illustrated embodiment, circuit 217 n and the corresponding circuit 219 n They work together to generate reset (e.g., power-on reset) signals and / or isolation control signals (also referred to as safety state control signals) for the electronic device 100 in the corresponding isolation path (e.g., the nth isolation path). For example, circuits 2171 and 2191 work together to generate an isolation control signal for the first isolation path 111, and circuits 2172 and 2192 work together to generate an isolation control signal for the second isolation path 112, and so on.

[0033] In the illustrated embodiment, the first power domain 101 has a low-voltage (LV) power supply (also referred to as a PD0LV power supply) for supplying a low supply voltage (e.g., 1V) to the first power domain 101, and a high-voltage (HV) power supply (also referred to as a PD0 HV power supply, or HV power supply) for supplying a high supply voltage (e.g., 5V) to the first power domain 101. In contrast, the second power domain 103 has only an LV power supply (also referred to as a PD1 LV power supply), and the third power domain 105 has only a low-voltage power supply (also referred to as a PD2LV power supply). In other words, the second power domain 103 and the third power domain 105 do not have HV power supplies. In some embodiments, the PD0LV power supply, the PD1 LV power supply, and the PD2 LV power supply have the same voltage level, which is lower than the voltage level of the HV power supply of the PD0 power domain.

[0034] exist Figure 5 In the middle, circuit 217 n This includes a reset generation circuit 201, an isolation test control circuit 207, an isolation function control circuit 209, and a multiplexer (MUX) 211. In some embodiments, during power-up, the PDO LV power supply rises from a logic low level (e.g., zero volts). During the period when the PDO LV power supply rises but remains below the threshold voltage for logic high, the reset generation circuit 201 generates a reset signal 203 with, for example, a "0" output (e.g., a logic low value). Figure 5 The power-on reset signal (marked as DEVICE_POR) is used to initialize (e.g., reset) the isolation test control circuit 207 and the isolation function control circuit 209. The reset signal 203 can also be used to reset the electronic device 100 or a part of the electronic device 100.

[0035] In the illustrated embodiment, the isolation test control circuit 207 is a test module such as a Design for Testability (DFT) module and can be controlled via a digital interface (e.g., a JTAG interface) in the PDO power domain during the test mode of the electronic device 100. During normal operation of the electronic device 100 (e.g., non-test mode), the output signal 208 of the isolation test control circuit 207 is "0" (e.g., a logic low value), selecting the output of the isolation function control circuit 209 as the output signal 205 of the MUX 211. (From circuit 217) n The output signal 205 is also known as the Enable for the nth isolation path. n Signal (Enable) n Signal).

[0036] In some embodiments, the isolation function control circuit 209 is a state machine that controls entering / exiting a low-power mode or a standby mode. In some embodiments, during power-on, the output signal (e.g., Enable) of the isolation function control circuit 209 for the nth isolation path... n The signal remains low until the PD0 LV, PD1 LV, and PD2 LV power supplies rise to a logic high voltage, at which point Enable is enabled. n The signal becomes a logic high value. Note that in the illustrated embodiment, after power-on is complete (e.g., when the PD0 LV power supply, HV power supply, PD1 LV power supply, and PD2 LV power supply rise above a logic high level), the PD0 power domain remains on (e.g., the PD0 LV power supply and HV power supply remain powered on) until the electronic device 100 is turned off or reset. After power-on is complete, the controller of the electronic device 100 can instruct the electronic device 100 to enter standby mode or low-power mode by turning off the PD1 power domain (e.g., turning off the PD1 LV power supply) and / or turning off the PD2 power domain (e.g., turning off the PD2 low-voltage power supply).

[0037] In some embodiments, after power-on is complete, when the input power domain of the nth isolation path or the output power domain of the nth isolation path is de-energized, the isolation function control circuit 209 is configured to generate a function for Enable. nThe signal's logic low value. Note that in this discussion, de-energizing a power domain (e.g., PD0, PD1, PD2) means de-energizing (e.g., turning off) all voltage supplies in that power domain. For example, de-energizing the PD0 LV and HV supplies in the PD0 power domain, de-energizing the PD1 LV supply in the PD1 power domain, and de-energizing the PD2 LV supply in the PD2 power domain. Similarly, energizing a power domain means energizing (e.g., turning on) all voltage supplies in that power domain. For example, energizing the PD0 LV and HV supplies in the PD0 power domain, energizing the PD1 LV supply in the PD1 power domain, or energizing the PD2 LV supply in the PD2 power domain.

[0038] In some embodiments, to improve the safety margin of the isolated path operation, during entry into low-power mode or standby mode, before the power domain is powered down (e.g., the PD2 power domain is powered down to enter low-power mode), the isolation function control circuit 209 enables the corresponding function by a certain time (e.g., a predetermined amount of time) before the supply voltage (e.g., the PD2 LV power supply) in that power domain begins to drop. n The signal generates a low logic value to preemptively disable all isolated paths connected to that power domain (e.g., see [link]). Figure 6 (See line 603 with arrows and the discussion below). Similarly, during exiting low-power mode or standby mode, the isolation function control circuit 209 enables the nth isolation path after a certain time (e.g., a predetermined amount of time) following all power supply voltages (e.g., PD2 LV power supply and / or PD1 LV power supply) in the input power domain and output power domain of the nth isolation path being at logic high. n Signal generation (delayed) logic high value (see Figure 6 The lines with arrows in the middle are 604 and 605, and the discussion below.

[0039] Still referencing Figure 5 Enable n The signal is sent to circuit 219 n There, its level is shifted from the PD0 LV supply voltage level to the HV supply voltage level by the low-to-high (L2H) voltage converter 227. The output of the L2H voltage converter 227 (e.g., the level-shifted Enable) nThe signal is gated by AND gate 223 using the output signal 222 of the set / reset circuit 221. The level of the output signal 224 of AND gate 223 is then level-shifted from the HV power supply voltage to the PDm LV power supply voltage level for the high-to-low (H2L) voltage converter 229 of the nth isolation path, where m = 0, 1, or 2, and the PDmLV power supply is the LV power supply of the output power domain of the nth isolation path. The output of the H2L voltage converter 229 (e.g., the level-shifted output signal 224) is the isolation control signal 213 (also referred to as the ISO_CTRLn signal) for the nth isolation path. In some embodiments, the ISO_CTRLn signal for the nth isolation path is buffered in the output power domain of the nth isolation path.

[0040] In the illustrated embodiment, circuit 219 n The setup / reset circuit 221 is configured to generate a "1" output (e.g., a logic high value) only when the HV power supply, input power domain, and output power domain of the nth isolation path are powered on; and is configured to generate a "0" output (e.g., a logic low value) if the input power domain or output power domain of the nth isolation path is powered off.

[0041] exist Figure 5 In this embodiment, the H2L voltage converter 229 has an enable terminal coupled to the output signal 226 of the AND gate 225. In the illustrated embodiment, when the signal at the enable terminal is "0" (e.g., logic low), the H2L voltage converter 229 is disabled and its output is forced to "0". When the signal at the enable terminal is "1" (e.g., logic high), the H2L voltage converter 229 is enabled and its output (e.g., Enable) is... n The signal is a level-shifted output signal 224. Figure 5 In the example, AND gate 225 is configured to generate an enable signal for H2L voltage converter 229 based on the HV supply voltage and LV supply voltage (e.g., PD0 LV supply, PD1 LV supply, or PD2 LV supply) of the output power domain of the nth isolation path. In some embodiments, AND gate 225 generates an enable signal of "1" when the HV supply voltage and LV supply voltage of the output power domain of the nth isolation path are at a logic high level.

[0042] Figure 5Further illustration shows circuitry 215 within the power management control circuitry 210. Circuitry 215 includes a voltage monitor and other logic circuitry (not shown). The voltage monitor monitors the power supply voltages (e.g., HV power, PD0 LV power, PD1 LV power, and PD2 LV power) of the power domains PD0, PD1, and PD2. The logic circuitry can implement other functions of the RSSLG circuitry 200. In the illustrated embodiment, the voltage monitor and other logic circuitry operate at the HV power supply voltage level, and therefore, circuitry 215 includes multiple L2H voltage converters 241 to shift various signal levels in the RSSLG circuitry 200 from the PD0 voltage level to the HV power supply voltage level for processing. The outputs of the voltage monitor and other logic circuitry are then downshifted to the PD0 LV power supply voltage level by an H2L voltage converter 243. At least some of the downshifted signals at the output of the H2L voltage converter 243, such as the voltage monitor output, are sent out as control signal 231, which is sent to the input terminal of the reset generation circuitry 201. Control signal 231 can also be isolated by function control circuit 209 and circuit 217. n use.

[0043] Figure 6 The illustration shows one embodiment. Figure 1 Timing diagram of electronic device 100. In Figure 6 In the diagram, the waveforms labeled PD2LV, PD1LV, PDOLV, and HV respectively illustrate the voltage levels of the PD2LV, PD1LV, PD0LV, and HV power supplies. Please note that... Figure 6 In the example, the HV power supply is powered on after the PD0 LV power supply, PD1 LV power supply, and PD2 LV power supply are powered on. It is marked as Enable. n Each waveform (n = 1, 2, ..., or 6) shows the Enable signal for the nth isolation path (e.g., Figure 5 The output signal 205 is shown in the diagram. Each waveform, labeled 222_n (n = 1, 2, ..., 6), is illustrated. Figure 5 The output signal 222 of the nth isolation path is shown. Similarly, the waveform labeled 224_n (n = 1, 2, ... or 6) is shown. Figure 5 The waveform of the output signal 224 of the nth isolation path, labeled 226_n (n = 1, 2, ..., 6), is shown below. Figure 5 The output signal 226 of the nth isolation path is marked as ISO_CTRL. n The waveforms (n = 1, 2, ..., or 6) are shown Figure 5 The isolation control signal 213 for the nth isolation path.

[0044] like Figure 6 As shown in the diagram, at the moment indicated by the arrowed line 601, the PD0 LV power supply, PD1 LV power supply, and PD2 LV power supply rise to a logic high level, resulting in Enable... n The (n = 1, 2, ..., 6) signal changes from logic low to logic high. At the moment indicated by the arrowed line 602, the HV power supply rises to logic high, and the output of the set / reset circuit 221 of the isolated path marked as waveform 222_n (n = 1, 2, ..., 6) changes from logic low to logic high. At this time, waveform 226_n (n = 1, 2, ..., 6) is already at logic high, and therefore, ISO_CTRL... n (n=1,2,…,6) When the signal changes from logic low to logic high, it indicates that the power-on (also known as startup) process is complete.

[0045] At the time instant indicated by the arrow on line 603, the PD2 LV power supply begins to decrease. This corresponds to the electronic device 100 entering a low-power mode, where the PD2 LV power supply begins to be de-energized. Note that, as discussed above, to ensure all isolated paths connected to the PD2 power domain (e.g., Figure 1 When PD2 power domain (111, 112, 113, and 114) is disabled, the isolation function control circuit 209 preemptively sets the Enable1, Enable2, Enable3, and Enable4 signals low at the moment corresponding to the tail of the arrowed line 603, thereby forcing the ISO_CTRL1, ISO_CTRL2, ISO_CTRL3, and ISO_CTRL4 signals low to disable isolation paths 111, 112, 113, and 114. Note that in low-power mode, the PD2 LV power supply is de-energized, while the PD0 LV and PD1 LV power supplies are energized, and therefore, the Enable5 and Enable6 signals are logic high, while Enable1, Enable2, Enable3, and Enable4 are logic low.

[0046] Still referencing Figure 6 At the moment indicated by the arrow on line 604, the PD1 LV power supply begins to decrease, indicating that electronic device 100 begins to enter standby mode, where the PD1 LV power supply begins to be de-energized. Note that, as discussed above, to ensure that all isolation paths connected between the PD1 power domain and the PD0 power domain (e.g., ...) are disconnected when the PD1 power domain is de-energized... Figure 1Since isolation paths 115 and 116 have been disabled, the isolation function control circuit 209 preemptively sets the Enable5 and Enable6 signals low at the moment corresponding to the tail of the arrowed line 604, thereby forcing the ISO_CTRL5 and ISO_CTRL6 signals to low to disable isolation paths 115 and 116. At the moment indicated by the arrowed line 605, the PD1 LV power supply rises back to logic high, indicating that the electronic device 100 now exits standby mode and enters low-power mode. Note that, as discussed above, the isolation function control circuit 209 delays the rise of the Enable5 and Enable6 signals for a predetermined period of time. After the delay, at the moment indicated by the arrowed line 606, the isolation function control circuit 209 changes the Enable5 and Enable6 signals from low to high, which makes the ISO_CTRL5 and ISO_CTRL6 signals high, thereby enabling isolation paths 115 and 116. At the moment indicated by line 607 with arrows, the PD2 LV power supply rises back to logic high, indicating that electronic device 100 now exits low-power mode and enters operating mode. Note that, as discussed above, the isolation function control circuit 209 delays the rise of the Enable1, Enable2, Enable3, and Enable4 signals for a predetermined period of time. After the delay, at the moment indicated by line 608 with arrows, the isolation function control circuit 209 changes the Enable1, Enable2, Enable3, and Enable4 signals from low to high, thereby making the ISO_CTRL1, ISO_CTRL2, ISO_CTRL3, and ISO_CTRL4 signals high, thus enabling isolation paths 111, 112, 113, and 114.

[0047] Figure 7 The illustration shows another embodiment. Figure 1 Timing diagram of electronic device 100. Figure 7 The timing diagram and Figure 6 The timing diagrams are similar, but in Figure 7 In this process, the HV power supply is powered on before the PD0 LV power supply, PD1 LV power supply, and PD2 LV power supply are powered on. Figure 7 The operation of the RSSLG circuit 200 in Figure 6 The operation of the RSSLG circuit is the same or similar, so the details will not be elaborated further.

[0048] The disclosed embodiments offer numerous advantages. For example, in the disclosed embodiments, the RSSLG circuit 200 for generating isolation control signals for all isolation paths is implemented in the PD0 power domain, and no isolation control signals are generated in the PD1 or PD2 power domains. By splitting the implementation in both the LV and HV power domains, this disclosure allows the implementation of reset and safety state logic for a single power flow (e.g., along the direction from the PD0 power domain to the PD2 power domain) in the LV power domain to also be used in dual-power-flow designs. Compared to the reset and safety state logic designed for a single power flow, the current design involves only minor changes in implementation and therefore requires little or no additional verification overhead. Without the currently disclosed design, the reset and safety state logic for a single power flow might have to be replicated in all power domains of the electronic device, significantly increasing the design area and cost, and requiring more development time due to the increased workload of verifying the additional modules implemented in all power domains.

[0049] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0050] Example 1. In one embodiment, an electronic device having dual power flow modes includes: a first power domain; a second power domain; a third power domain, wherein in a first power flow mode during power-on, the third power domain, the second power domain, and the first power domain are configured to be sequentially powered, wherein in a second power flow mode during a standby mode of the electronic device, the first power domain remains powered, and the second and third power domains are configured to be sequentially powered; and an isolation path that provides controlled signal transmission between the first power domain, the second power domain, and the third power domain, wherein each isolation path includes an input power domain coupled to the isolation path and an isolation... An isolation circuit path between the output power domains of the isolation path, the input power domain and the output power domain being two power domains in a first, second and third power domain connected by the isolation path; and a reset and secure state logic generation (RSSLG) circuit in the first power domain, wherein for each isolation path, the RSSLG circuit is configured to generate an isolation control signal for the isolation circuit in the isolation path, wherein the isolation circuit is configured to allow signal transmission along the isolation path from the input power domain to the output power domain when the isolation control signal has a first value, and is configured to disable signal transmission along the isolation path when the isolation control signal has a second value.

[0051] Example 2. The electronic device according to Example 1, wherein for each isolation path, the RSSLG circuit is configured to generate an isolation control signal with a second value when the input power domain or output power domain of the isolation path is de-energized.

[0052] Example 3. The electronic device according to Example 2, wherein for each isolation path, the RSSLG circuit is configured to generate an isolation control signal having a first value when at least the input power domain and the output power domain of the isolation path are powered on.

[0053] Example 4. An electronic device according to Example 3, wherein no isolation control signal is generated by the second power domain or the third power domain.

[0054] Example 5. An electronic device according to Example 1, wherein the isolation circuit is an AND gate, wherein a first input terminal of the AND gate is coupled to an isolation control signal, a second input terminal of the AND gate is coupled to an input power domain, and an output terminal of the AND gate is coupled to an output power domain.

[0055] Example 6. An electronic device according to Example 1, wherein the isolation circuit is an OR gate having an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is coupled to an isolation control signal, the non-inverting input terminal is coupled to an input power domain, and the output terminal of the OR gate is coupled to an output power domain.

[0056] Example 7. An electronic device according to Example 1, wherein a first power domain has a first low-voltage (LV) power supply and a first high-voltage (HV) power supply, wherein a second power domain has a second LV power supply, and a third power domain has a third LV power supply, wherein the first LV power supply, the second LV power supply, and the third LV power supply have the same first voltage level, which is lower than the second voltage level of the HV power supply.

[0057] Example 8. An electronic device according to Example 7, wherein the second power domain and the third power domain have no HV power supply.

[0058] Example 9. An electronic device according to Example 7, wherein the RSSLG circuit includes a first circuit for generating a first isolation control signal for a first isolation path in an isolation path, the first circuit including: an isolation function control circuit configured to generate an enable signal at the output of an isolation function control circuit; a low-to-high (L2H) voltage converter coupled to the output of the isolation function control circuit and configured to convert the enable signal from a first voltage level to a second voltage level; a set / reset circuit configured to generate a first control signal at the second voltage level at the output of the set / reset circuit; an AND gate, wherein a first input terminal of the AND gate is coupled to the output of the L2H voltage converter and a second input terminal of the AND gate is coupled to the output of the set / reset circuit; and a high-to-low (H2L) voltage converter coupled to the output terminal of the AND gate, wherein the H2L voltage converter is configured to generate the isolation control signal for the first isolation path by converting the output signal from the AND gate from the second voltage level to the first voltage level.

[0059] Example 10. An electronic device according to Example 9, wherein the isolation function control circuit is configured to: generate a first logic value for an enable signal when the first LV power supply, the second LV power supply and the third LV power supply are powered on; and generate a second logic value for an enable signal when the input power domain or the output power domain of the first isolation path is powered off.

[0060] Example 11. An electronic device according to Example 10, wherein the set / reset circuit is configured to: generate a first logic value for a first control signal when the first power domain HV power supply, the input power domain and the output power domain of the first isolation path are powered on; and generate a second logic value for the first control signal when the input power domain or the output power domain of the first isolation path is powered off.

[0061] Example 12. In one embodiment, an electronic device includes: a first power domain, a second power domain, and a third power domain, wherein during a power-on process of the electronic device, the third power domain, the second power domain, and the first power domain are sequentially powered, and wherein during a standby exit process of the electronic device, the first power domain, the second power domain, and the third power domain are sequentially powered; isolation paths between the first and second power domains, between the second and third power domains, and between the first and third power domains, wherein each isolation path includes an isolation circuit controlled by an isolation control signal, wherein for each isolation path, when the isolation control signal has a first value, the isolation circuit allows digital signals to pass through the isolation circuit from... The input power domain of the isolation path is passed to the output power domain of the isolation path, and the isolation circuit prevents digital signals from being transmitted through the isolation circuit when the isolation control signal has a second value, wherein the input power domain and the output power domain are two power domains connected to the first, second, and third power domains of the isolation path; and a reset and secure state logic generation (RSSLG) circuit in the first power domain, wherein for each isolation path, the RSSLG circuit is configured to generate an isolation control signal with a first value when at least the input power domain or the output power domain of the isolation path is powered on, and is configured to generate an isolation control signal with a second value when the input power domain or the output power domain of the isolation path is powered off.

[0062] Example 13. An electronic device according to Example 12, wherein no isolation control signal is generated by a second power domain or a third power domain.

[0063] Example 14. An electronic device according to Example 12, wherein the isolation circuit includes an AND gate or an OR gate.

[0064] Example 15. An electronic device according to Example 12, wherein the first power domain is a standby power domain, the second power domain is a low power domain, and the third power domain is an operating mode power domain.

[0065] Example 16. An electronic device according to Example 15, wherein in the standby mode of the electronic device, a first power domain is powered on and a second power domain and a third power domain are powered off; wherein in the low power mode of the electronic device, the first power domain and the second power domain are powered on and the third power domain is powered off; and wherein in the operating mode of the electronic device, the first power domain, the second power domain, and the third power domain are powered on.

[0066] Example 17. In one embodiment, an electronic device includes: a standby (STBY) power domain, a low power (LP) power domain, and an operating mode (RM) power domain, wherein in a first power flow mode of the electronic device, the RM power domain, the LP power domain, and the STBY power domain are sequentially powered, and wherein in a second power flow mode of the electronic device, the STBY power domain remains powered, while the LP power domain and the STBY power domain and the RM power domain are sequentially powered; isolation paths between the STBY and LP power domains, between the LP and RM power domains, and between the STBY and RM power domains, wherein each isolation path includes isolation circuitry and provides a data path having isolation functionality between an input power domain and an output power domain of the isolation path, wherein the input power domain and the output power domain... It is a power domain of an electronic device connected to an isolation path, wherein for each isolation path, when the isolation control signal of the isolation circuit has a first value, the isolation circuit allows digital signals to be transmitted from the input power domain of the isolation path to the output power domain of the isolation path, and when the isolation control signal has a second value, the isolation circuit prevents digital signals from being transmitted from the input power domain of the isolation path to the output power domain of the isolation path; and a reset and secure state logic generation (RSSLG) circuit in the STBY power domain, wherein for each isolation path, the RSSLG circuit is configured to generate an isolation control signal with a first value when at least the input power domain and the output power domain of the isolation path are powered on, and is configured to generate an isolation control signal with a second value when either the input power domain or the output power domain of the isolation path is powered off.

[0067] Example 18. An electronic device according to Example 17, wherein no isolation control signal is generated by the LP power domain or the RM power domain.

[0068] Example 19. An electronic device according to Example 18, wherein the STBY power domain has a first low-voltage (LV) power supply and a first high-voltage (HV) power supply, wherein the LP power domain has a second LV power supply, and the RM power domain has a third LV power supply, wherein the first LV power supply, the second LV power supply and the third LV power supply have the same voltage level, which is lower than the voltage level of the HV power supply.

[0069] Example 20. An electronic device according to Example 19, wherein the LP power domain and RM power domain have no HV power supply.

[0070] While the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method of operating an electronic device having a dual power flow mode, the method comprising: in a first power flow mode of the dual power flow mode, sequentially powering up a third power domain, a second power domain, and a first power domain of the electronic device, wherein the electronic device has isolation paths that provide controlled signal transfer between the first power domain, the second power domain, and the third power domain, wherein each isolation path includes an isolation circuit coupled between an input power domain of the isolation path and an output power domain of the isolation path, wherein the input power domain and the output power domain are two of the first power domain, the second power domain, and the third power domain connected by the isolation path; in a second power flow mode of the dual power flow mode, sequentially powering up the second power domain and the third power domain while maintaining the first power domain powered; and generating, using a reset and safe state logic of the electronic device in the first power domain, an RSSLG circuit, an isolation control signal for the isolation circuit in each of the isolation paths, wherein the isolation circuit is configured to enable signal transfer along the isolation path from the input power domain to the output power domain when the isolation control signal has a first value, and is configured to disable signal transfer along the isolation path when the isolation control signal has a second value.

2. The method of claim 1, wherein the first power flow mode corresponds to a power up procedure of the electronic device, and the second power flow mode corresponds to a standby exit procedure of the electronic device.

3. The method of claim 1, wherein generating the isolation control signal comprises: generating the isolation control signal having the second value when the input power domain or the output power domain of the isolation path is powered down.

4. The method of claim 3, wherein generating the isolation control signal comprises: generating the isolation control signal having the first value when at least the input power domain and the output power domain of the isolation path are powered up.

5. The method of claim 1, wherein the first power domain has a first low voltage power supply and a high voltage power supply, wherein the second power domain has a second low voltage power supply, and the third power domain has a third low voltage power supply, wherein the high voltage power supply has a higher voltage level than the first low voltage power supply, the second low voltage power supply, and the third low voltage power supply.

6. The method of claim 5, wherein the second power domain and the third power domain are free of the high voltage power supply.

7. The method of claim 5, wherein the RSSLG circuit includes a plurality of first circuits, wherein each first circuit of the plurality of first circuits is configured to generate the isolation control signal for a corresponding isolation path, wherein for each isolation path, generating the isolation control signal includes: generating, using an isolation function control circuit of the first circuit corresponding to the isolation path, a first enable signal having a first voltage level; generating, using a first voltage level control circuit of the first circuit corresponding to the isolation path, a first voltage level control signal having a second voltage level; and generating, using a second voltage level control circuit of the first circuit corresponding to the isolation path, a second voltage level control signal having a third voltage level. converting the first enable signal to a second enable signal having a second voltage level using a low-to-high L2H voltage translator of the first circuit, the second voltage level being higher than the first voltage level; gating the second enable signal using a control signal generated by a set / reset circuit of the first circuit; and converting the gated second enable signal to the isolation control signal having a third voltage level different from the second voltage level using a high-to-low H2L voltage translator of the first circuit.

8. The method of claim 7, wherein the first voltage level is a voltage level of the first low voltage power supply of the output power domain of the isolation path, the second voltage level is a voltage level of the high voltage power supply of the output power domain of the isolation path, and the third voltage level is a voltage level of the first low voltage power supply, the second low voltage power supply, or the third low voltage power supply of the output power domain of the isolation path.

9. The method of claim 7, wherein generating the first enable signal comprises: generating a first logic value for the first enable signal using the isolation function control circuit of the first circuit when the first low voltage power supply, the second low voltage power supply, and the third low voltage power supply are powered up; and generating a second logic value for the first enable signal when the input power domain or the output power domain of the isolation path is powered down.

10. The method of claim 7, wherein gating the second enable signal comprises: gating the second enable signal using an AND gate with the control signal generated by the set / reset circuit.

11. The method of claim 10, further comprising generating the control signal using the set / reset circuit, comprising: generating a first logic value for the control signal when the high voltage power supply of the first power domain, the input power domain, and the output power domain of the isolation path are powered up; and generating a second logic value for the control signal when the input power domain or the output power domain of the isolation path is powered down.

12. A method of operating an electronic device, the electronic device comprising a first power domain, a second power domain, and a third power domain, the method comprising: sequentially powering up the third power domain, the second power domain, and the first power domain during a power up process of the electronic device; during a standby exit procedure of the electronic device, sequentially powering up the first power domain, the second power domain, and the third power domain, wherein the electronic device comprises an isolation path between the first power domain and the second power domain, between the second power domain and the third power domain, and between the first power domain and the third power domain, wherein each of the isolation paths is controlled by an isolation control signal, wherein depending on a value of the isolation control signal, the isolation path allows or prevents digital signal transmission from an input power domain of the isolation path to an output power domain of the isolation path, wherein the input power domain and the output power domain are two of the first power domain, the second power domain, and the third power domain connected to the isolation path; and generating the isolation control signal for each isolation path using a reset and safety state logic in the first power domain comprises: generating the isolation control signal with a first value to enable the digital signal transmission when at least the input power domain and the output power domain of the isolation path are powered up; and generating the isolation control signal with a second value to prevent the digital signal transmission when the input power domain or the output power domain of the isolation path is powered down.

13. The method of claim 12, wherein each of the isolation paths comprises an isolation circuit controlled by an isolation control signal, wherein the isolation circuit comprises an AND gate or an OR gate.

14. The method of claim 13, wherein when the isolation circuit comprises the AND gate, generating the isolation control signal comprises: generating a logic high value as the first value of the isolation control signal; and generating a logic low value as the second value of the isolation control signal.

15. The method of claim 13, wherein when the isolation circuit comprises the OR gate, generating the isolation control signal comprises: generating a logic low value as the first value of the isolation control signal; and generating a logic high value as the second value of the isolation control signal.

16. The method of claim 12, wherein the first power domain is a standby power domain, the second power domain is a low power power domain, and the third power domain is a full power power domain.

17. A method of operating an electronic device, the electronic device comprising a standby STBY power domain, a low power LP power domain, and a run mode RM power domain, the method comprising: in a first power flow mode of the electronic device, sequentially powering up the RM power domain, the LP power domain, and the STBY power domain; ​ ​ in a second power flow mode of the electronic device, maintaining the STBY power domain powered while sequentially powering up the LP and RM power domains, wherein the electronic device includes isolation paths between the STBY and the LP power domains, between the LP and the RM power domains, and between the STBY and the RM power domains, wherein each isolation path provides a data path having an isolation function between an input power domain of the isolation path and an output power domain of the isolation path, wherein the input power domain and the output power domain are power domains of the electronic device connected to the isolation path; disabling digital signal transfer from the input power domain of the isolation path to the output power domain of the isolation path when the input power domain or the output power domain of the isolation path is powered down; and enabling digital signal transfer from the input power domain of the isolation path to the output power domain of the isolation path when at least the input power domain and the output power domain of the isolation path are powered up.

18. The method of claim 17, wherein each isolation path is controlled by an isolation control signal, the disabling digital signal transfer and the enabling digital signal transfer comprising: generating, using a reset and safe state logic in the STBY power domain, an RSSLG circuit, generating the isolation control signal having a first value when at least the input power domain and the output power domain of the isolation path are powered up, and generating the isolation control signal having a second value when the input power domain or the output power domain of the isolation path is powered down.

19. The method of claim 18, wherein the generating the isolation control signal having the first value comprises: generating, using the RSSLG circuit, the isolation control signal having the first value at a first time, the first time being a first predetermined time period after the input power domain and the output power domain of the isolation path are powered up.

20. The method of claim 19, wherein the generating the isolation control signal having the second value comprises: generating, using the RSSLG circuit, the isolation control signal having the second value at a second time, the second time being a second predetermined time period before the input power domain or the output power domain of the isolation path is powered down. ​

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