A method for rapidly predicting integrated circuit yield

Abstract

This invention relates to a method for rapidly predicting integrated circuit yield, comprising: S1. establishing a layout correction model based on machine learning and training the model; S2. identifying representative layout structures in the full-chip layout of the integrated circuit; S3. performing optical proximity correction on the identified layout structures to obtain a corrected layout structure shape that can be formed on the wafer; S4. inputting the obtained corrected layout structure shape into the layout correction model to obtain the predicted correction amount; S5. analyzing the obtained correction amount to identify the structures that affect the yield of the integrated circuit and calculating the yield of the integrated circuit. This method can quickly calculate the distortion of the integrated circuit chip pattern after optical proximity correction, thereby predicting the impact of this distortion on the yield of the integrated circuit chip, and is particularly applicable to advanced nodes.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a method for rapidly predicting the yield of integrated circuits. Background Technology

[0002] With the rapid development of integrated circuit manufacturing technology, the integration density of integrated circuits is increasing rapidly, the manufacturing process and steps are becoming increasingly complex, and the process size is constantly shrinking. Design for Manufacturability (DFM) can directly improve the yield of integrated circuit chips and reduce the production cost of chips.

[0003] Photolithography is one of the most important steps in integrated circuit manufacturing, and its principle is as follows: Figure 1 As shown. In chip manufacturing, when the linewidth on the wafer is smaller than the exposure wavelength, proximity correction must be applied to the pattern on the mask to avoid pattern distortion after imaging on the silicon wafer due to optical interference, diffraction, and other complex processes. Optical proximity correction uses optical calculations to modify the pattern on the mask to compensate for the difference between the lithography wavelength and the linewidth of the manufactured chip, such as... Figure 2 .

[0004] The applicant discovered that the basic principle of optical proximity correction (OPC) is to simulate the corresponding photolithography process and then use numerical optimization methods to iteratively optimize the mask pattern to achieve the resolution required for integrated circuit manufacturing. Because complex and accurate optical models are needed to achieve sub-nanometer simulation accuracy, the computational load is enormous and grows exponentially with the advancement of Moore's Law. For example, for each new node (e.g., 14 nanometers), the layout density per unit area increases more than twice compared to the previous node (e.g., the node preceding 14 nanometers was 22 nanometers), while the corresponding computational load per unit area only increases by about 25%.

[0005] Because optical proximity correction (OPC) technology cannot perfectly resolve all pattern distortions in silicon wafer imaging caused by optical interference, diffraction, and other complex processes, and because OPC computation is enormous (accounting for approximately half the time in advanced node tape-out processes), and the computation time for OPC increases exponentially with the continuous shrinking of integrated circuit process dimensions, this method is becoming increasingly unsuitable for the research and development and production of advanced nodes. Therefore, how to quickly predict the impact of such distortion on integrated circuit chip yield has become a problem that must be solved. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a method for rapidly predicting integrated circuit yield.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] This invention provides a method for rapidly predicting integrated circuit yield, comprising:

[0009] S1. Establish a layout correction model based on machine learning and complete the training of the layout correction model;

[0010] S2. Locate representative layout structures in the full-chip layout of integrated circuits;

[0011] S3. Perform optical proximity correction on the layout structure found in S2 to obtain the corrected layout structure shape that can be formed on the wafer;

[0012] S4. Input the corrected layout structure shape obtained in S3 into the layout correction model trained in S1 to obtain the difference between the contour generated after OPC and the full-chip layout of the integrated circuit, i.e. the predicted correction amount.

[0013] S5. Analyze the correction amount obtained in S4, find the structure that affects the yield of the integrated circuit, and calculate the yield of the integrated circuit.

[0014] Furthermore, the patternclassification method in S2 searches for representative layout structures in the geometry of the full-chip layout of the integrated circuit.

[0015] Furthermore, in S4, after inputting the corrected layout structure shape, the layout correction model converts the corrected layout structure shape into a pixel representation, and / or performs optical simulation on the corrected layout structure shape to calculate the light intensity distribution, and extracts light intensity features from the light intensity distribution.

[0016] Furthermore, in S1, a CNN model architecture is used to establish a layout correction model. Then, the established layout correction model is trained by inputting the layout structure of an existing good integrated circuit full-chip layout and its correction amount.

[0017] Beneficial effects of this invention:

[0018] By employing the above-mentioned technical solution, this invention can quickly calculate the distortion of integrated circuit chip patterns after optical proximity correction, thereby predicting the impact of this distortion on the yield of integrated circuit chips, which is particularly applicable to advanced nodes. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of existing photolithography processes;

[0020] Figure 2This is a schematic diagram of the existing optical proximity correction principle;

[0021] Figure 3 This is a flowchart illustrating the method for rapidly predicting integrated circuit yield according to the present invention.

[0022] Figure 4 This is a schematic diagram of the layout correction model in the method for rapidly predicting integrated circuit yield described in this invention;

[0023] Figure 5 This is an example of a method for rapidly predicting integrated circuit yield described in this invention, which uses pattern classification to find representative layout structures in the geometry of a full-chip integrated circuit layout.

[0024] Figure 6 The layout correction model in the method for rapidly predicting integrated circuit yield described in this invention is based on... Figure 5 The example demonstrates how the corrected layout structure shape is represented in pixel format;

[0025] Figure 7 The layout correction model in the method for rapidly predicting integrated circuit yield described in this invention is based on... Figure 5 The example shows the light intensity distribution map obtained by optical simulation calculation of the corrected layout structure shape;

[0026] Figure 8 The layout correction model in the method for rapidly predicting integrated circuit yield described in this invention is based on... Figure 5-7 Example of the predicted correction amount obtained from the example. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0028] like Figure 3 As shown in the figure, the method for rapidly predicting integrated circuit yield according to the present invention specifically includes the following steps:

[0029] Step S1. Establish a machine learning-based layout correction model and complete its training; specifically, this machine learning-based layout correction model is built using a CNN model architecture, for example... Figure 4 After the model is established, the layout correction model is trained by inputting previously collected experimental data (experimental data of the same integrated circuit process and similar layouts) such as the layout structure of existing good integrated circuit full-chip layouts and their correction amounts.

[0030] Step S2. Locate representative layout structures in the full-chip layout of the integrated circuit; specifically, pattern classification (pattern recognition) methods can be used to find representative layout structures in the geometry of the full-chip layout of the integrated circuit, for example... Figure 5 .

[0031] Step S3. Perform optical proximity correction on the layout structure found in S2 to obtain the corrected layout structure shape that can be formed on the wafer.

[0032] Step S4. Input the corrected layout structure shape obtained in S3 into the layout correction model trained in S1 to obtain the difference between the contour (the shape of the structure formed on the wafer by optical simulation of the corrected layout) generated by the OPC (overspeed protection control unit) and the full-chip layout of the integrated circuit, i.e., the predicted correction amount. In other words, the layout correction model outputs the correction amount of the corresponding layout structure after optical proximity correction, for example... Figure 8 , Figure 8 The red portion represents the predicted modification amount; specifically, after inputting the modified layout structure shape into the trained layout correction model, the layout correction model converts the modified layout structure shape into a pixel representation (e.g., ...). Figure 6 This facilitates the use of the modified layout structure shape as input to subsequent neural networks, and / or, for calculating the light intensity distribution after optical simulation (e.g., ...). Figure 7 The process of converting the corrected layout structure shape into pixels, performing optical simulation on the corrected layout structure shape to calculate the light intensity distribution, and extracting light intensity features from the light intensity distribution are all existing technologies and will not be described in detail here.

[0033] Step S5. Analyze the correction amount obtained in S4 to find the structure that affects the yield of the integrated circuit and calculate the yield of the integrated circuit. Since the full-chip layout of the designed integrated circuit is an ideal case, the impact on the yield can be analyzed by comparing the difference (correction amount) between the contour and the full-chip layout of the integrated circuit. For example, if the contour is broken, the corresponding circuit is an open circuit; or if the contour is smaller than the corresponding target, the corresponding resistance, capacitance and other parameters can be calculated to calculate the impact on the electrical performance of the circuit. There are many ways to find the structure that affects the yield of the integrated circuit. For example, if the circuit is open or short-circuited, it can be found by searching for the corresponding problem; if it is an impact on electrical performance, the corresponding analysis software (such as SPICE) must be used for calculation. These methods are commonly used methods and will not be elaborated on here. The yield calculation method of integrated circuit can be calculated by calculating and analyzing the electrical performance of the circuit. This calculation method is also a mature method and will not be elaborated on here.

[0034] The core of the method for rapidly predicting integrated circuit yield described in this invention is a layout correction model based on machine learning. This layout correction model predicts the amount of optical proximity correction on the integrated circuit layout, thereby enabling rapid analysis of the impact of this distortion on the integrated circuit chip yield. Moreover, since this method avoids the use of time-consuming optical proximity correction steps, it can greatly reduce the amount of computation and time cost, making it particularly suitable for predicting the yield of integrated circuits at advanced nodes.

[0035] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for rapidly predicting integrated circuit yield, characterized in that, include: S1. Establish a layout correction model based on machine learning and complete the training of the layout correction model; S2. Locate representative layout structures in the full-chip layout of integrated circuits; S3. Perform optical proximity correction on the layout structure found in S2 to obtain the corrected layout structure shape that can be formed on the wafer; S4. Input the corrected layout structure shape obtained in S3 into the layout correction model trained in S1 to obtain the difference between the contour generated after OPC and the full-chip layout of the integrated circuit, i.e. the predicted correction amount. S5. Analyze the correction amount obtained in S4, find the structure that affects the yield of the integrated circuit, and calculate the yield of the integrated circuit.

2. The method according to claim 1, characterized in that, The pattern classification method in S2 identifies representative layout structures within the geometry of a full-chip integrated circuit layout.

3. The method according to claim 1, characterized in that, In S4, after inputting the corrected layout structure shape, the layout correction model converts the corrected layout structure shape into a pixel representation, and / or performs optical simulation on the corrected layout structure shape to calculate the light intensity distribution, and extracts light intensity features from the light intensity distribution.

4. The method according to claim 1 or 2, characterized in that, In S1, a CNN model architecture is used to establish a layout correction model. Then, the established layout correction model is trained by inputting the layout structure of an existing good integrated circuit full-chip layout and its correction amount.

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