Multilayer ceramic capacitor

Abstract

The present disclosure provides a multilayer ceramic capacitor. The multilayer ceramic capacitor includes a main body including dielectric layers and first and second internal electrodes alternately disposed and the dielectric layers interposed between the first and second internal electrodes, a first external electrode disposed on the main body and connected to the first internal electrode, and a second external electrode disposed on the main body and connected to the second internal electrode. The dielectric layers include first dielectric layers adjacent to the first internal electrodes, second dielectric layers adjacent to the second internal electrodes, and third dielectric layers disposed between the first and second dielectric layers. D1 < D3 and D2 < D3, where D1 is an average particle diameter of dielectric grains included in the first dielectric layers, D2 is an average particle diameter of dielectric grains included in the second dielectric layers, and D3 is an average particle diameter of dielectric grains included in the third dielectric layers.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2021-0165493, filed November 26, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety for all purposes. TECHNICAL FIELD

[0002] The disclosure relates to a multilayer ceramic capacitor. BACKGROUND

[0003] A multilayer ceramic capacitor (MLCC), which is a type of multilayer electronic component, is a chip capacitor mounted on a printed circuit board of various types of electronic products, such as display devices (including liquid crystal displays (LCDs) and plasma display panels (PDPs)), computers, smart phones, cellular phones, etc., to charge and discharge electric charges therein.

[0004] MLCCs, which have advantages such as compactness, guaranteeing high capacitance, and ease of mounting, can be used as components of various electronic devices. Recently, as various electronic devices have become smaller and have achieved higher performance, the importance of ensuring high reliability of multilayer ceramic capacitors has increased.

[0005] Recently, in multilayer ceramic capacitors, dielectric layers or internal electrode layers have been thinned in order to achieve miniaturization and high capacitance.

[0006] As such, when the thickness of the dielectric layers of the multilayer ceramic capacitor is reduced, the electrical properties, such as capacitance, can be improved, but the frequency of electrostriction damage due to electrostriction can increase and high-temperature reliability can be weakened.

[0007] In addition, in order to alleviate the phenomenon of a decrease in reliability in the case of forming thin dielectric layers, a method of reducing the grain size of the dielectric layers to be more refined has been considered, but a problem of not being able to achieve the desired capacitance due to a low dielectric constant can occur. SUMMARY

[0008] Exemplary embodiments weaken the phenomenon of electrostriction damage due to the electrostriction phenomenon when the dielectric layers are formed to be thin in order to improve electrical properties, such as capacitance, and solve the problem of a decrease in high-temperature reliability.

[0009] Exemplary embodiments solve the problem of a decrease in dielectric constant when the grain size of the dielectric layers is reduced in order to improve the reliability of the multilayer ceramic capacitor.

[0010] According to an exemplary embodiment, a multilayer ceramic capacitor includes a main body including dielectric layers and first and second internal electrodes alternately disposed with the dielectric layers interposed between the first and second internal electrodes, a first external electrode disposed on the main body and connected to the first internal electrode, and a second external electrode disposed on the main body and connected to the second internal electrode. The dielectric layers include a first dielectric layer adjacent to the first internal electrode, a second dielectric layer adjacent to the second internal electrode, and a third dielectric layer disposed between the first and second dielectric layers. D1 < D3 and D2 < D3, where D1 is an average particle diameter of dielectric grains included in the first dielectric layer, D2 is an average particle diameter of dielectric grains included in the second dielectric layer, and D3 is an average particle diameter of dielectric grains included in the third dielectric layer.

[0011] According to an exemplary embodiment, a multilayer ceramic capacitor includes a main body including dielectric layers and internal electrodes alternately disposed with the dielectric layers interposed between the internal electrodes, and an external electrode disposed on the main body and connected to the internal electrodes. The dielectric layers include a fourth dielectric layer and a fifth dielectric layer including dielectric grains having an average particle diameter greater than an average particle diameter of dielectric grains included in the fourth dielectric layer. t4 < t5, where t4 is an average thickness of the fourth dielectric layer and t5 is an average thickness of the fifth dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and other aspects, features, and advantages of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a schematic perspective view of a multilayer ceramic capacitor according to an exemplary embodiment of the present disclosure;

[0014] Figure 2 is a schematic cross-sectional view taken along line I-I' in Figure 1

[0015] Figure 3 is a schematic cross-sectional view taken along line II-II' in Figure 1

[0016] Figure 4 is an exploded perspective view schematically showing a main body of a dielectric layer and an internal electrode stack according to an exemplary embodiment or another exemplary embodiment of the present disclosure;

[0017] Figure 5 is an enlarged view of a region "P1" in Figure 2

[0018] is an enlarged view of a region "P1" in​​Figure 6 is according to another exemplary embodiment of the present disclosure Figure 2 is an enlarged view of a region "P2" in

[0019] Figure 7 is a graph showing a state in which an electrostriction phenomenon occurs when average particle diameters of dielectric grains do not significantly differ; and

[0020] Figure 8 is a graph showing a state in which an electrostriction phenomenon occurs when average particle diameters of dielectric grains significantly differ. DETAILED DESCRIPTION

[0021] Exemplary embodiments of the inventive concept will be described below in detail with reference to the accompanying drawings. However, the inventive concept can be embodied in various ways and will not be interpreted as being limited to the specific exemplary embodiments described herein. Rather, the exemplary embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the shapes and sizes of elements can be exaggerated for clarity, and the same reference numbers will be always used throughout the specification for the same or similar elements.

[0022] For the clarity of the present disclosure, parts not related to the description are omitted and the same reference numbers always indicate the same elements in the specification, and in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for the clarity. Further, in the drawings, similar reference numbers indicate similar elements although shown in different drawings. Throughout the specification, unless explicitly described to the contrary, the words such as "comprise" and "include" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0023] In the drawings, a first direction can be defined as a stacking direction or a thickness direction, a second direction can be defined as a length direction, and a third direction can be defined as a width direction.

[0024] Multilayer ceramic capacitor

[0025] The following will be described with reference to Figures 1 to 8 A multilayer ceramic capacitor according to exemplary embodiments of the present disclosure will be described in detail.

[0026] A multilayer ceramic capacitor includes a main body including dielectric layers and first and second internal electrodes alternately disposed with the dielectric layers interposed between the first and second internal electrodes, a first external electrode disposed on the main body and connected to the first internal electrode, and a second external electrode disposed on the main body and connected to the second internal electrode. The dielectric layers include first dielectric layers adjacent to the first internal electrodes, second dielectric layers adjacent to the second internal electrodes, and third dielectric layers disposed between the first and second dielectric layers, D1 < D3 and D2 < D3, where D1 is an average particle diameter of dielectric grains included in the first dielectric layers, D2 is an average particle diameter of dielectric grains included in the second dielectric layers, and D3 is an average particle diameter of dielectric grains included in the third dielectric layers.

[0027] Referring to Figure 2 In the main body 110, the dielectric layers 111 and the first and second internal electrodes 121 and 122 are alternately stacked.

[0028] The specific shape of the main body 110 is not particularly limited, but, as shown in FIG. 1, the main body 110 can have a hexahedral shape or a shape similar to the hexahedral shape. Due to the shrinkage (or tightening) of ceramic powder particles included in the main body 110 during a sintering process, the main body 110 can have a substantially hexahedral shape, rather than a hexahedral shape with perfect straight lines. Figure 1

[0029] The main body 110 can have a first surface 1 and a second surface 2 opposite to each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first and second surfaces 1 and 2 and opposite to each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first, second, third, and fourth surfaces 1, 2, 3, and 4 and opposite to each other in a third direction.

[0030] The plurality of dielectric layers 111 forming the main body 110 are in a sintered state, and adjacent dielectric layers 111 can be integrated such that a boundary between adjacent dielectric layers 111 is not easily distinguished without using a scanning electron microscope (SEM).

[0031] According to an exemplary embodiment of the disclosure, a raw material forming the dielectric layers 111 is not limited as long as a sufficient electrostatic capacitance can be obtained. For example, a barium titanate-based material, a lead complex perovskite-based material, or a strontium titanate-based material can be used as the raw material forming the dielectric layers 111. The barium titanate-based material can include BaTiO3-based ceramic powder particles, examples of which can include BaTiO3and (Ba 1-x Ca x )TiO3(0 < x < 1), Ba(Ti 1-y Ca​y )O3(0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1 and 0 < y < 1) or Ba(Ti 1-y Zr y )O3(0 < y < 1).

[0032] According to the purpose of the present disclosure, various ceramic additives, organic solvents, binders, dispersants, etc. can be added to a powder such as barium titanate (BaTiO3) as a material for forming the dielectric layer 111.

[0033] The main body 110 can include a capacitor forming portion A formed inside the main body 110 and forming a capacitor by disposing the first internal electrode 121 and the second internal electrode 122 to face each other with the dielectric layer 111 interposed therebetween, and upper and lower cover portions 112 and 113 formed above and below the capacitor forming portion A.

[0034] In addition, the capacitor forming portion A is a portion that contributes to forming a capacitor, and can be formed by repeatedly stacking a plurality of first internal electrodes 121 and a plurality of second internal electrodes 122 with the dielectric layer 111 interposed between the first internal electrode 121 and the second internal electrode 122.

[0035] The upper cover portion 112 and the lower cover portion 113 can be formed by stacking a single dielectric layer, two dielectric layers, or more dielectric layers on the upper surface and the lower surface of the capacitor forming portion A in the thickness direction, respectively, and can substantially serve to prevent damage to the internal electrode due to physical or chemical stress.

[0036] The upper cover portion 112 and the lower cover portion 113 can not include the internal electrode, and can include the same material as that of the dielectric layer 111.

[0037] That is, the upper cover portion 112 and the lower cover portion 113 can include a ceramic material, for example, a barium titanate (BaTiO3)-based ceramic material.

[0038] In addition, the edge portions 114 and 115 can be disposed on the side surfaces of the capacitor forming portion A.

[0039] The edge portions 114 and 115 can include the edge portion 114 providing the sixth surface 6 of the main body 110 and the edge portion 115 providing the fifth surface 5 of the main body 110. That is, the edge portions 114 and 115 can be disposed on both side surfaces of the capacitor forming portion A in the width direction.

[0040] As Figure 3As shown, the edge portions 114 and 115 can refer to regions between the two ends of the first and second internal electrodes 121 and 122 and the boundary surface of the main body 110 in a cross section of the main body 110 taken in the width-thickness direction.

[0041] The edge portions 114 and 115 can substantially serve to prevent damage to the internal electrodes due to physical stress or chemical stress.

[0042] The edge portions 114 and 115 can be formed when the internal electrodes are formed by applying a conductive paste on portions of a ceramic green sheet other than regions where the edge portions are to be formed.

[0043] In addition, to suppress a step difference caused by the internal electrodes 121 and 122, the edge portions 114 and 115 can be formed by, after stacking, performing cutting to expose the internal electrodes to both side surfaces of the capacitor forming portion A in the width direction, and then stacking a single dielectric layer, two dielectric layers, or more dielectric layers on both side surfaces of the capacitor forming portion A in the width direction.

[0044] The internal electrodes 121 and 122 can be alternately disposed with the dielectric layer 111.

[0045] The internal electrodes 121 and 122 can include a first internal electrode 121 and a second internal electrode 122. The first and second internal electrodes 121 and 122 can be alternately disposed opposite each other with the dielectric layer 111 of the main body 110 interposed therebetween, and the first and second internal electrodes 121 and 122 can be in contact with a first external electrode on the third surface 3 of the main body 110 and a second external electrode on the fourth surface 4 of the main body 110, respectively.

[0046] Referring to Figure 2 , the first internal electrode 121 can be spaced apart from the fourth surface 4 and can be in contact with the first external electrode 131 on the third surface 3, and the second internal electrode 122 can be spaced apart from the third surface 3 and can be in contact with the second external electrode 132 on the fourth surface 4.

[0047] In this case, the first and second internal electrodes 121 and 122 can be electrically isolated from each other by the dielectric layer 111 interposed therebetween.

[0048] Referring to Figure 4 , the main body 110 can be formed by alternately stacking ceramic green sheets on which the first internal electrode 121 is printed and ceramic green sheets on which the second internal electrode 122 is printed, and then sintering the ceramic green sheets.

[0049] The conductive metal included in the internal electrodes 121 and 122 can be one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, but the present disclosure is not limited thereto.

[0050] In addition, the internal electrodes 121 and 122 can be formed by printing a conductive paste on a ceramic green sheet, and a screen printing method or a gravure printing method can be used as a printing method for the conductive paste of the internal electrodes.

[0051] Further, the external electrodes 131 and 132 can be formed using any material as long as the corresponding material has electrical conductivity, such as a metal, and a specific material can be determined in consideration of electrical characteristics and structural stability. Further, the external electrodes 131 and 132 can have a multi-layer structure.

[0052] For example, the external electrodes 131 and 132 can include electrode layers 131a and 132a disposed on the body 110 and plating layers 131b and 132b formed on the electrode layers 131a and 132a, respectively.

[0053] As a more specific example of the electrode layers 131a and 132a, the electrode layers 131a and 132a can be sintered electrodes including a conductive metal and glass, or resin-based electrodes including a conductive metal and resin.

[0054] In addition, the electrode layers 131a and 132a can have a form in which a sintered electrode and a resin-based electrode are sequentially formed on the body 110. In addition, the electrode layers 131a and 132a can be formed by transferring a sheet including a conductive metal to the body or transferring a sheet including a conductive metal to a sintered electrode.

[0055] A material having excellent electrical conductivity can be used as the conductive metal included in the electrode layers 131a and 132a, but the material is not particularly limited. For example, the conductive metal can be one or more of nickel (Ni), copper (Cu), and alloys thereof.

[0056] The plating layers 131b and 132b serve to improve mounting properties. The type of the plating layers 131b and 132b is not particularly limited, and the plating layers 131b and 132b can be plating layers including at least one of Ni, Sn, Pd, and alloys thereof, and the plating layers 131b and 132b can be formed with a plurality of layers.

[0057] As a more specific example of the plating layers 131b and 132b, the plating layers 131b and 132b can be Ni plating layers or Sn plating layers, can have a form in which a Ni plating layer and a Sn plating layer are sequentially formed on the electrode layers 131a and 132a, or can have a form in which a Sn plating layer, a Ni plating layer, and a Sn plating layer are sequentially formed on the electrode layers 131a and 132a. In addition, the plating layers 131b and 132b can include a plurality of Ni plating layers and / or a plurality of Sn plating layers.

[0058] The size of the multilayer electronic component 100 need not be particularly limited.

[0059] However, in order to achieve both miniaturization and high capacitance, the number of stacked layers should be increased by reducing the thickness of the dielectric layers and the internal electrodes, and thus the effects of improving reliability and insulation resistance can be more significant in a multilayer electronic component having a 0402 size (length x width, 0.4 mm x 0.2 mm).

[0060] Therefore, when the distance between the third surface and the fourth surface of the main body is defined as a length and the distance between the fifth surface and the sixth surface is defined as a width, the length can be 0.4 mm or less and the width can be 0.2 mm or less. That is, the multilayer electronic component 100 can be a multilayer electronic component having a 0402 size (length x width, 0.4 mm x 0.2 mm) or less.

[0061] In the case of a multilayer ceramic capacitor, in order to obtain a high energy density and a capacitance, a ferroelectric material such as PZT and BaTiO3 is often used as a dielectric material. These materials mechanically deform in response to an external electric field, and this phenomenon is referred to as a flexoelectricity effect.

[0062] In a conventional multilayer ceramic capacitor in which a dielectric layer is thinly formed for miniaturization and a high capacitance, the dielectric layer disposed between internal electrodes of the capacitor is sintered using powder particles having the same size.

[0063] Therefore, after sintering, the particle size of the dielectric grains of the dielectric layer can also be within a certain distribution.

[0064] When an alternating electric field is applied from the outside, the ferroelectric particles forming the dielectric layer continuously vibrate due to the flexoelectricity effect. Therefore, if the particle size of the dielectric grains forming the dielectric layer does not significantly differ, the vibrations generated due to the flexoelectricity effect cannot be canceled out (or compensated for).

[0065] Therefore, continuous stress can be applied to the multilayer ceramic capacitor to form an electrostrictive crack inside the multilayer ceramic capacitor, and such a crack can cause degradation in reliability at high temperatures.

[0066] A multilayer ceramic capacitor according to an exemplary embodiment of the present disclosure can include a main body 110 including dielectric layers 111 and first and second internal electrodes 121 and 122 alternately disposed with the dielectric layers 111 interposed between the first and second internal electrodes 121 and 122, a first external electrode 131 disposed on the main body 110 and connected to the first internal electrode 121, and a second external electrode 132 disposed on the main body 110 and connected to the second internal electrode 122. The dielectric layers 111 can include first dielectric layers 111a adjacent to the first internal electrode 121, second dielectric layers 111b adjacent to the second internal electrode 122, and third dielectric layers 111c disposed between the first and second dielectric layers 111a and 111b. D1 < D3 and D2 < D3, where D1 is an average particle diameter of dielectric grains included in the first dielectric layers 111a, D2 is an average particle diameter of dielectric grains included in the second dielectric layers 111b, and D3 is an average particle diameter of dielectric grains included in the third dielectric layers 111c.

[0067] Figure 7 An example in which an electrostriction phenomenon occurs when there is no significant difference in the average particle diameter of dielectric grains included in each region of a dielectric layer is shown, Figure 8 is a graph showing a case in which the average particle diameter of dielectric grains included in each region of a dielectric layer has a significant difference.

[0068] Referring to Figure 7 and Figure 8 , in the case of Figure 7 , there is no significant difference in the particle diameter of dielectric grains, so it is difficult to cancel the electrostriction effect. In addition, in the case of Figure 8 , because the particle diameter of dielectric grains constituting each region of a dielectric layer has a significant difference, the pattern in which the electrostriction effect occurs can be different for each region. Specifically, in a region in which the average particle diameter is large, the frequency of vibration caused by electrostriction is high and the amplitude is small. In addition, in a region in which the average particle diameter is small, the frequency of vibration caused by electrostriction is low and the amplitude is large. Therefore, when the average particle diameter of dielectric grains included in each region constituting a dielectric layer has a significant difference, the effect of canceling vibration due to the electrostriction effect can occur.

[0069] In order to obtain the effect of canceling vibration due to electrostriction, the difference in the average particle diameter of dielectric grains constituting each region is preferably 50 nm or more, but is not limited thereto.

[0070] Therefore, in a multilayer ceramic capacitor according to an exemplary embodiment of the present disclosure, because a dielectric layer is formed with a plurality of layers and the average particle diameter of dielectric grains constituting each layer is different from each other, the effect of canceling electrostriction can be induced.

[0071] In addition, by forming the first dielectric layer and the second dielectric layer including dielectric grains having a small particle diameter in a portion of the dielectric layer, breakdown voltage (BDV) characteristics and direct current bias (DC-BIAS) characteristics can be improved, and by forming the third dielectric layer including dielectric grains having a relatively large particle diameter between the first dielectric layer and the second dielectric layer, capacitance can be ensured.

[0072] Referring to Figure 5 The first dielectric layer 111a, the second dielectric layer 111b, and the third dielectric layer 111c can be units for dividing the dielectric layer 111 including dielectric grains having different average particle diameters.

[0073] The particle diameters of the dielectric grains constituting each region can be substantially the same within each region according to a manufacturing method thereof, or can be adjusted to be within a certain distribution.

[0074] In addition, an average particle diameter D1 of the dielectric grains included in the first dielectric layer 111a, an average particle diameter D2 of the dielectric grains included in the second dielectric layer 111b, and an average particle diameter D3 of the dielectric grains included in the third dielectric layer 111c can be different from each other or can be substantially the same.

[0075] When D1, D2, and D3 are different from each other, each region can be easily distinguished from each other by observing the dielectric layer using a scanning electron microscope (SEM).

[0076] Here, a difference in the average particle diameter of the dielectric grains included in each region is preferably 50 nm or more.

[0077] Here, the first dielectric layer 111a can refer to a region from a lower surface of the first internal electrode 121 to an upper surface of the third dielectric layer 111c, and the second dielectric layer 111b can refer to a region from an upper surface of the second internal electrode 122 to a lower surface of the third dielectric layer 111c.

[0078] The edge portion, the cover portion, and the dielectric layer of the multilayer ceramic capacitor can include dielectric grains, and the "average particle diameter" of the dielectric grains can refer to an average value obtained by imaging a length-thickness direction cross section at the center of the multilayer ceramic capacitor, taking 10 points at equal intervals in the length direction, and then calculating using an image analysis program (LASX Grain Expert manufactured by Leica Microsystems). Even if not described in the present disclosure, other measurement methods and / or tools recognized by those of ordinary skill in the art can be used.

[0079] According to an exemplary embodiment, a ratio (D3 / D1) of D3 to D1 can satisfy a range of 1.3 to 2.3, and a ratio (D3 / D2) of D3 to D2 can satisfy a range of 1.3 to 2.3.

[0080] If D3 / D1 and D3 / D2 are less than 1.3, the difference in the particle size of the dielectric grains of the adjacent regions can be too small, and it can be difficult to induce the effect of canceling the electrostriction.

[0081] If D3 / D1 and D3 / D2 are greater than 2.3, the difference in the particle size of the dielectric grains of the adjacent regions can be too large, and it can cause deterioration in high-temperature reliability.

[0082] By adjusting D3 / D1 and D3 / D2 to be within the above range, the electrostriction phenomenon can be further canceled and deterioration in high-temperature reliability can be prevented.

[0083] According to exemplary embodiments, when the average thickness of the first dielectric layer 111a is t1, the average thickness of the second dielectric layer 111b is t2, and the average thickness of the third dielectric layer 111c is t3, t1 < t3 can be satisfied and t2 < t3 can be satisfied.

[0084] The first dielectric layer 111a and the second dielectric layer 111b are formed using dielectric grains having an average particle size smaller than the average particle size in the third dielectric layer 111c, and thus are used to improve reliability, such as improving DC-bias characteristics and TCC characteristics and improving short-circuit defects.

[0085] Meanwhile, because the third dielectric layer 111c is formed using dielectric grains having an average particle size larger than the average particle size in the first dielectric layer 111a and the second dielectric layer 111b, it can be used to secure high capacitance of the multilayer ceramic capacitor.

[0086] Because the first dielectric layer 111a and the second dielectric layer 111b can contribute to improvement in reliability, and the third dielectric layer 111c is interposed between the first dielectric layer 111a and the second dielectric layer 111b, even if the thickness t1 of the first dielectric layer 111a and the thickness t2 of the second dielectric layer 111b are 1 / 10 to 1 / 3 of the thickness t3 of the third dielectric layer 111c, an effect of improving reliability can be obtained.

[0087] Thus, by regularly controlling the respective thicknesses t1, t2, and t3 of the corresponding regions (the first dielectric layer 111a, the second dielectric layer 111b, and the third dielectric layer 111c) of the dielectric layer 111, high capacitance can be secured, and in addition, the reliability of the multilayer ceramic capacitor is improved.

[0088] The average thickness of the dielectric layer 111 and the first dielectric layer 111a, the second dielectric layer 111b, and the third dielectric layer 111c can be measured by an image of a cross section in the length-thickness direction scanned by a 10000 times magnified scanning electron microscope (SEM). More specifically, the average thickness can be an average of the measured thicknesses, which are measured by dividing a portion in which the average grain size of the dielectric grains of the dielectric layer 111 is varied by 1.3 to 2.3 times in the thickness direction into the first dielectric layer 111a, the second dielectric layer 111b, and the third dielectric layer 111c, and measuring the thicknesses at 10 points in the length direction at which the capacitor forming portions A are equally spaced in the scanned image.

[0089] In the related art, when the dielectric layer 111 is a thin film having an average thickness of 0.41 μm or less, more cracks due to the electrostriction can occur and it can be difficult to secure a high capacitance.

[0090] However, according to the present exemplary embodiment, even when the average thickness of the dielectric layer 111 is 0.41 μm or less, the electrostriction phenomenon can be offset to suppress the occurrence of the electrostriction cracks and to secure a sufficient capacitance, if D1 < D3 and D2 < D3 are satisfied.

[0091] Here, the average thickness of the dielectric layer 111 of 0.41 μm or less does not mean that the average thickness of the dielectric layer 111 should be 0.41 μm or less, but can mean that the dielectric layer 111 is thinner than the dielectric layer of the multilayer ceramic capacitor of the related art.

[0092] If the difference between the average grain size D3 of the dielectric grains included in the third dielectric layer 111c and the average grain sizes D1 and D2 of the dielectric grains included in the first dielectric layer 111a and the second dielectric layer 111b is less than 50 nm, the offset effect of the electrostriction can be insufficient, so that it can be difficult to prevent the occurrence of the electrostriction cracks and it can be difficult to distinguish the first dielectric layer 111a, the second dielectric layer 111b, and the third dielectric layer 111c.

[0093] According to the exemplary embodiment, the difference between D3 and D1 can be adjusted to 50 nm or more, and the difference between D3 and D2 can be adjusted to 50 nm or more, so that a sufficient electrostriction effect offset effect is secured and the occurrence of the electrostriction cracks is suppressed.

[0094] Further, the upper limit values of the difference between D3 and D1 and the difference between D3 and D2 can be determined in consideration of the thickness of the dielectric layer 111.

[0095] As described above, the third dielectric layer 111c has a larger grain size of the dielectric grains than the first dielectric layer 111a and the second dielectric layer 111b, and thus can be used to increase the capacitance of the multilayer ceramic capacitor.

[0096] Therefore, when the first dielectric layer 111a and the second dielectric layer 111b are provided on the upper surface and the lower surface of the third dielectric layer 111c, it is possible to easily secure reliability, but if the thickness t3 of the third dielectric layer 111c is not sufficient with respect to the thickness td of the dielectric layer, it can be difficult to secure a high capacitance of the multilayer ceramic capacitor.

[0097] According to an exemplary embodiment, when the thickness (e.g., average thickness) of the dielectric layer is td, the ratio of t1 to td (t1 / td) can be adjusted to 1 / 4 or less and the ratio of t2 to td (t2 / td) can be adjusted to 1 / 4 or less, and thus, even if the first dielectric layer 111a and the second dielectric layer 111b are provided on the upper surface or the lower surface of the third dielectric layer 111c, it is possible to secure a high capacitance of the multilayer ceramic capacitor and to improve the reliability thereof.

[0098] Hereinafter, a multilayer ceramic capacitor according to another exemplary embodiment of the disclosure will be described in detail, but a description of the multilayer ceramic capacitor according to the exemplary embodiment will be omitted.

[0099] The multilayer ceramic capacitor according to another exemplary embodiment of the disclosure includes a main body including dielectric layers and internal electrodes alternately disposed with the dielectric layers interposed between the internal electrodes, and an external electrode provided on the main body and connected to the internal electrodes. The dielectric layers include a fourth dielectric layer and a fifth dielectric layer having dielectric grains having a larger average grain diameter than dielectric grains included in the fourth dielectric layer. t4 < t5, where t4 is an average thickness of the fourth dielectric layer and t5 is an average thickness of the fifth dielectric layer. A ratio of t4 to td can be 1 / 4 or less, where td is an average thickness of the dielectric layer.

[0100] Referring to Figure 6 The dielectric layers 111 can include a fourth dielectric layer 111d and a fifth dielectric layer 111e having dielectric grains having different average grain diameters.

[0101] That is, the average grain diameter D5 of the dielectric grains included in the fifth dielectric layer 111e can be greater than the average grain diameter D4 of the dielectric grains included in the fourth dielectric layer 111d.

[0102] Here, D5 being greater than D4 can mean that there is a sufficient difference for the cancellation effect of the above-described electrostriction phenomenon to occur, and preferably, there is a difference of 50 nm or more, or a ratio (D5 / D4) of the average grain diameter D5 of the dielectric grains included in the fifth dielectric layer 111e to the average grain diameter D4 of the dielectric grains included in the fourth dielectric layer 111d can be 1.3 or more. As an example, D5 / D4 can be in the range of 1.3 to 2.3. In Figure 6In the present example embodiment, the fourth dielectric layer 111d is formed on the upper portion of the dielectric layer 111, and the fifth dielectric layer 111e is formed on the lower portion of the dielectric layer 111, but the present disclosure is not limited to this, and the positions of the fourth dielectric layer 111d and the fifth dielectric layer 111e can be exchanged.

[0103] Therefore, the dielectric layer 111 can include the fourth dielectric layer 111d adjacent to one end surface of the internal electrode in the stacking direction and the fifth dielectric layer 111e adjacent to the other end surface of the internal electrode in the stacking direction, but the present disclosure is not limited to this, and the dielectric layer 111 can include the fourth dielectric layer 111d and the fifth dielectric layer 111e including dielectric grains having an average particle diameter larger than the average particle diameter of the dielectric grains included in the fourth dielectric layer 111d.

[0104] Further, the average particle diameter D4 of the dielectric grains included in the fourth dielectric layer 111d can be smaller than the average particle diameter D5 of the dielectric grains included in the fifth dielectric layer 111e.

[0105] Here, D5 and D4 can differ by 50 nm or more, and due to this difference, the dielectric layers can be sufficiently distinguished when observed using a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0106] Further, the upper limit value of the difference between D5 and D4 can be determined in consideration of the thickness of the dielectric layer 111.

[0107] Because the average particle diameter D4 of the dielectric grains of the fourth dielectric layer 111d is smaller than the average particle diameter D5 of the dielectric grains of the fifth dielectric layer 111e, the fourth dielectric layer 111d can be used to improve high-temperature reliability.

[0108] Because the average particle diameter D5 of the dielectric grains of the fifth dielectric layer 111e is larger than the average particle diameter D4 of the dielectric grains of the fourth dielectric layer 111d, the fifth dielectric layer 111e can be used to ensure capacitance.

[0109] The fourth dielectric layer 111d contributes to improving reliability, and even if its thickness is 1 / 10 to 1 / 3 of the thickness of the fifth dielectric layer 111e, an effect of improving reliability can be obtained, whereas the fifth dielectric layer 111e needs to occupy a sufficient portion in the entire dielectric layer 111 to ensure sufficient capacitance.

[0110] In the multilayer ceramic capacitor according to the present example embodiment of the present disclosure, because the average thickness t5 of the fifth dielectric layer 111e including dielectric grains having a relatively large average particle diameter is larger than the average thickness t4 of the fourth dielectric layer 111d including dielectric grains having a relatively small average particle diameter, it is possible to ensure the reliability of the multilayer ceramic capacitor and also to ensure sufficient capacitance.

[0111] According to an exemplary embodiment, a ratio (t4 / t5) of an average thickness t4 of the fourth dielectric layer 111d to an average thickness t5 of the fifth dielectric layer 111e can be in a range of 1 / 10 to 1 / 3.

[0112] Accordingly, as described above, it is possible to secure sufficient capacitance and to improve high-temperature reliability.

[0113] As described above, if D5 / D4 is less than 1.3, the difference in the particle size of the dielectric grains of each region can be too small to induce the effect of canceling the effect of the electrostriction.

[0114] In addition, if D5 / D4 is greater than 2.3, the difference in the particle size of the dielectric grains of each region can be too large to cause degradation in high-temperature reliability.

[0115] According to an exemplary embodiment, because a ratio (D5 / D4) of an average particle size D5 of the dielectric grains included in the fifth dielectric layer 111e to an average particle size D4 of the dielectric grains included in the fourth dielectric layer 111d satisfies a range of 1.3 to 2.3, it is possible to secure a sufficient difference between D4 and D5 to induce the canceling effect of the electrostriction phenomenon and, at the same time, to prevent degradation in high-temperature reliability.

[0116] According to an exemplary embodiment, the average thickness of the dielectric layer 111 can be 0.41 μm or less.

[0117] In the related art, if the average thickness of the dielectric layer 111 is thin to 0.41 μm or less, more cracks due to the vibration of the electrostriction can occur and it can be difficult to secure high capacitance.

[0118] However, according to the present exemplary embodiment, even when the average thickness of the dielectric layer 111 is 0.41 μm or less, it is possible to cancel the electrostriction phenomenon to suppress the occurrence of the electrostriction cracks and to secure sufficient capacitance, by satisfying D4 < D5 and t4 < t5.

[0119] Here, the average thickness of the dielectric layer 111 being 0.41 μm or less does not necessarily mean that the average thickness of the dielectric layer 111 should be 0.41 μm or less, but can mean that the dielectric layer 111 is thinner than the dielectric layer of the multi-layer ceramic capacitor of the related art.

[0120] Method of manufacturing a multilayer ceramic capacitor

[0121] A method of manufacturing a multi-layer ceramic capacitor according to an exemplary embodiment of the present disclosure will be described below, and the manufacturing method to be described below can be similarly applied to the case of manufacturing a multi-layer ceramic capacitor according to another exemplary embodiment of the present disclosure.

[0122] First, a plurality of ceramic green sheets are prepared.

[0123] The ceramic green sheet is used to form the dielectric layer 111 of the main body 110. A slurry is prepared by mixing ceramic powder particles, a polymer, and a solvent, and the slurry can be made into a sheet having a predetermined thickness (e.g., a thickness of 0.41 μm or less) by a method such as a doctor blade method.

[0124] In general, the dielectric layer between the internal electrodes is formed using one layer of ceramic green sheet, but several layers of the same ceramic green sheet can be stacked in order to ensure a sufficient thickness.

[0125] In addition, according to an exemplary embodiment of the present disclosure, the dielectric layer between the internal electrodes can be formed using two or more different ceramic green sheets.

[0126] Here, the different ceramic green sheets can refer to different compositions and / or sizes of powder particles used as raw materials.

[0127] According to an exemplary embodiment of the present disclosure, a first ceramic green sheet can be formed on the upper surface of the PET film using a fine particle base material. Alternatively, the material for the first ceramic green sheet can further include Mg, Dy, or Tb capable of inhibiting grain growth.

[0128] Thereafter, a second ceramic green sheet can be formed on the upper surface of the first ceramic green sheet using a coarse particle base material. The size of the powder particles of the coarse particle base material for the second ceramic green sheet can be greater than the size of the powder particles of the fine particle base material for the first ceramic green sheet.

[0129] According to a modified example, the size of the powder particles of the base material for the second ceramic green sheet can be the same as the size of the powder particles of the base material for the first ceramic green sheet, the material for the first ceramic green sheet further includes Mg, Dy, or Tb capable of inhibiting grain growth, and the material for the second ceramic green sheet does not include Mg, Dy, or Tb capable of inhibiting grain growth.

[0130] Next, a third ceramic green sheet having the same composition as the first ceramic green sheet is formed on the upper surface of the second ceramic green sheet.

[0131] In this case, the base material included in the ceramic green sheet can be a barium titanate (BaTiO3)-based compound, and preferably, the molar content ratio Ba / Ti of Ba to Ti can be in the range of 0.9950 to 1.0050, but is not limited thereto.

[0132] Therefore, as described above, with reference to Figure 5 After sintering, the region corresponding to the first ceramic green sheet can be a first dielectric layer of the dielectric layer, the region corresponding to the second ceramic green sheet can be a third dielectric layer of the dielectric layer, and the region corresponding to the third ceramic green sheet can be a second dielectric layer of the dielectric layer.

[0133] In one example, one of the first and third ceramic green sheets can be omitted. Thus, as described above, referring to FIG. 1, the first and third ceramic green sheets can be omitted. Figure 6 After sintering, a region corresponding to the other one of the first and third ceramic green sheets can be a fourth dielectric layer of the dielectric layer, and a region corresponding to the second ceramic green sheet can be a fifth dielectric layer of the dielectric layer.

[0134] The position at which each region of the dielectric layer is formed, the thickness of each region, and the grain size of the dielectric grains can be adjusted using the method described above, but the present disclosure is not limited thereto.

[0135] Thereafter, internal electrodes are formed by printing a conductive paste for internal electrodes having a predetermined thickness (e.g., 0.41 μm or less) on at least one surface of each or a plurality of laminated ceramic green sheets.

[0136] The conductive paste for internal electrodes can include 94.0 wt% to 99.6 wt% of nickel (Ni) and 0.4 wt% to 6.0 wt% of copper (Cu). For example, the conductive paste for internal electrodes can be formed by mixing Ni powder and Cu powder or including Ni-Cu alloy powder. In this case, the conductive paste for internal electrodes can include Ni-Cu alloy powder and can not include a ceramic material.

[0137] A screen printing method or a gravure printing method can be used as a method of printing the conductive paste for internal electrodes.

[0138] Referring to FIG. 1, Figure 4 The ceramic green sheet on which the first internal electrode 121 is printed and the ceramic green sheet on which the second internal electrode 122 is printed can be alternately stacked and then pressed in a stacking direction, so that the plurality of stacked ceramic green sheets and the internal electrodes formed on the ceramic green sheets can be pressed together to form a stack.

[0139] In addition, the cover portions 112 and 113 can be formed by stacking at least one layer of ceramic green sheets on the upper and lower surfaces of the stack, respectively.

[0140] The cover portions 112 and 113 can have the same composition as that of the dielectric layer 111 located inside the stack, and differ from the dielectric layer 111 in that the cover portions 112 and 113 do not include internal electrodes.

[0141] Thereafter, the stack is cut so that each region corresponds to one capacitor to form a green sheet, and then sintered at a high temperature to complete the main body 110.

[0142] Thereafter, the first and second external electrodes 131 and 132 can be formed to cover exposed portions of the first and second internal electrodes exposed at the end surfaces of the main body 110, respectively, so as to be electrically connected to the first and second internal electrodes, respectively.

[0143] In this case, if necessary, the surfaces of the first external electrode 131 and the second external electrode 132 may be plated with nickel or tin.

[0144] (Exemplary Example)

[0145] After preparing the sample sheet, the dielectric layer in the effective region (capacitor forming part) of the multilayer ceramic capacitor is divided into a fourth dielectric layer and a fifth dielectric layer with different average grain sizes of dielectric grains. Table 1 below shows the measurement results of the high-temperature accelerated lifetime and the frequency of electrostrictive crack occurrence based on the change of the ratio of the average grain size D5 of the dielectric grains included in the fifth dielectric layer to the average grain size D4 of the dielectric grains included in the fourth dielectric layer.

[0146] The average grain size of the dielectric grains in each region can be measured as follows.

[0147] The “average grain size” of dielectric grains can be obtained by taking an image of the cross-section at the center of a multilayer ceramic capacitor along the length-thickness direction, taking 10 points at equal intervals along the length direction, and then calculating it using an image analysis program (Leica Microsystems’ LAS X Grain Expert).

[0148] In high-temperature accelerated life testing, the accelerated life of 400 samples for each test number was evaluated under conditions of 150°C, 2.0V, and 24 hours to detect the number of failed samples. Regarding failure, an insulation resistance of 10 Ω·cm was used in the high-temperature accelerated life evaluation. 4 A value of Ω or less is considered a failure.

[0149] The frequency of electrostrictive crack occurrence can be detected based on the displacement caused by voltage. To evaluate electrostrictive cracks, a sample is mounted on a substrate to which a voltage can be applied. When mounting the sample on the substrate, for example, it can be done by applying a paste to a plated portion of the substrate, followed by heat treatment to fix it to the substrate. Electrostrictive cracks can be detected by mounting a displacement sensor on top of the cover portion of the body and applying a voltage. By setting the voltage rise rate to 20V / min, the voltage at which cracks occur when a voltage is applied from 0V to 350V can be detected, and the electrostrictive crack voltages relative to the D5 / D4 ratio can be compared.

[0150] [Table 1]

[0151]

[0152] *Comparison Example

[0153] In Test Nos. 1 and 2 in which D5 / D4 is greater than 2.3, it can be seen that the effect of improving high-temperature accelerated life is insufficient or missing.

[0154] In Test Nos. 9 and 10 in which D5 / D4 is less than 1.3, it can be seen that the effect of canceling the electrostriction phenomenon is missing or insufficient, and in Test Nos. 11 and 12, it can be seen that the effect of improving high-temperature accelerated life is insufficient.

[0155] Therefore, preferably, D5 / D4 satisfies the range of 1.3 to 2.3, and more preferably, D5 / D4 satisfies the range of 1.5 to 2.3.

[0156] One of the various effects of the present disclosure is to attenuate the electrostriction breakdown phenomenon caused by the electrostriction phenomenon when the dielectric layer is formed thin and solve the problem of high-temperature reliability reduction.

[0157] One of the various effects of the present disclosure is to solve the problem of dielectric constant reduction when the grain size of the dielectric layer is reduced in order to improve the reliability of the multilayer ceramic capacitor.

[0158] However, the various advantageous effects and advantages of the present disclosure are not limited to the above-mentioned, and will be more readily appreciated as the specific exemplary embodiments of the present disclosure are described in detail.

[0159] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure defined by the appended claims.

Claims

1. A multilayer ceramic capacitor, comprising: The main body includes alternating dielectric layers and a first inner electrode and a second inner electrode, wherein the dielectric layers are located between the first inner electrode and the second inner electrode; A first external electrode is disposed on the main body and connected to the first internal electrode; as well as The second external electrode is disposed on the main body and connected to the second internal electrode. The dielectric layer includes: a first dielectric layer adjacent to the first inner electrode, a second dielectric layer adjacent to the second inner electrode, and a third dielectric layer disposed between the first dielectric layer and the second dielectric layer. D1 < D3 and D2 < D3, where D1 is the average grain size of the dielectric grains included in the first dielectric layer, D2 is the average grain size of the dielectric grains included in the second dielectric layer, and D3 is the average grain size of the dielectric grains included in the third dielectric layer. The difference between D3 and D1 is 50nm or greater, and the difference between D3 and D2 is 50nm or greater.

2. The multilayer ceramic capacitor according to claim 1, wherein, The ratio of D3 to D1, D3 / D1, is in the range of 1.3 to 2.3, and the ratio of D3 to D2, D3 / D2, is in the range of 1.3 to 2.

3.

3. The multilayer ceramic capacitor according to claim 1, wherein, t1 < t3 and t2 < t3, where t1 is the average thickness of the first dielectric layer, t2 is the average thickness of the second dielectric layer, and t3 is the average thickness of the third dielectric layer.

4. The multilayer ceramic capacitor according to claim 3, wherein, The ratio of t1 to t3, t1 / t3, is in the range of 1 / 10 to 1 / 3, and the ratio of t2 to t3, t2 / t3, is in the range of 1 / 10 to 1 / 3.

5. The multilayer ceramic capacitor according to claim 3, wherein, The ratio of t1 to td, t1 / td, is 1 / 4 or less, and the ratio of t2 to td, t2 / td, is 1 / 4 or less, where td is the average thickness of the dielectric layer.

6. The multilayer ceramic capacitor according to claim 1, wherein, The average thickness of the dielectric layer is 0.41 μm or less.

7. The multilayer ceramic capacitor according to claim 1, wherein, The third dielectric layer is in contact with the first dielectric layer and also with the second dielectric layer.

8. The multilayer ceramic capacitor according to claim 7, wherein, The first dielectric layer is in contact with the first inner electrode, and the second dielectric layer is in contact with the second inner electrode.

9. A multilayer ceramic capacitor, comprising: The main body includes alternating dielectric layers and inner electrodes, wherein the dielectric layers are located between the inner electrodes; as well as An external electrode is disposed on the main body and connected to the internal electrode. The dielectric layer includes a fourth dielectric layer and a fifth dielectric layer. The fifth dielectric layer includes dielectric grains having an average grain size D5 that is larger than the average grain size D4 of the dielectric grains included in the fourth dielectric layer, and the ratio of D5 to D4, D5 / D4, satisfies a range greater than 1.5 and less than or equal to 2.

3. t4 < t5, where t4 is the average thickness of the fourth dielectric layer and t5 is the average thickness of the fifth dielectric layer.

10. The multilayer ceramic capacitor according to claim 9, wherein, The ratio of t4 to t5, t4 / t5, is in the range of 1 / 10 to 1 / 3.

11. The multilayer ceramic capacitor according to claim 9, wherein, The average thickness of the dielectric layer is 0.41 μm or less.

12. The multilayer ceramic capacitor according to claim 9, wherein, The difference between D5 and D4 is 50nm or greater.

13. The multilayer ceramic capacitor according to any one of claims 9-12, wherein, The ratio of t4 to td is 1 / 4 or less, where td is the average thickness of the dielectric layer.

14. The multilayer ceramic capacitor according to claim 9, wherein, The fourth dielectric layer is disposed on the fifth dielectric layer.

15. The multilayer ceramic capacitor according to claim 9, wherein, The fourth dielectric layer is disposed below the fifth dielectric layer.

16. The multilayer ceramic capacitor according to claim 9, wherein, The fourth dielectric layer is in contact with the fifth dielectric layer.

17. The multilayer ceramic capacitor according to claim 16, wherein, The fourth dielectric layer is in contact with one of the inner electrodes, and the fifth dielectric layer is in contact with the other of the inner electrodes.

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