A lateral hybrid carrier control device

Abstract

The present invention discloses a hybrid carrier control device, belonging to the technical field of power semiconductors. It includes a main working unit, a PMOS region, a carrier distribution region, an insulating region, and a substrate region; the main working unit and the PMOS structure are respectively arranged on both sides of the isolation region. The present invention solves the problems of the existing lateral power devices, such as small current density, large on-state power consumption, poor trade-off relationship between on-state voltage drop and turn-off loss, and poor practicability. On the basis of the conventional lateral thyristor device, the present invention utilizes two P-type regions with different doping concentrations and areas, and additionally introduces a low-doped P-type region on the left side of the high-doped P-type region to form a depletion-type PMOS structure, so as to achieve the purpose of shunt control of electron and hole carriers.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and particularly to a lateral hybrid carrier control device. Background Art

[0002] A conventional MCT is a composite device formed by simply combining a MOSFET structure and a thyristor structure. Due to the very high resistance of the MOS gate insulating layer, the input power of the device is very small, the gate drive circuit is simple, and the switching speed becomes fast. The thyristor device has an extremely low conduction voltage drop and a strong high-current load capacity. Therefore, the MCT device combining a MOS transistor and a thyristor effectively improves the controllability problem of a conventional thyristor and increases the current load capacity. However, such a simple combination results in a large loss when the device is turned off. At the same time, for a lateral power device, since the current flows on the surface of the device. Therefore, its current is relatively small, the conduction loss is large, and it can only be applied in the low-voltage and low-power fields. In order to improve these defects of the device and enhance the device performance, some improved structures have been proposed subsequently. These improved devices can simplify the gate drive circuit to a certain extent and reduce the device turn-off time. However, generally speaking, the turn-off performance of the device can still be further improved.

[0003] Subsequently, with the development of IGBT devices, and since the main structure of the MCT device is similar to that of the IGBT device, the mutual reference between the MCT device and the IGBT device has become one of the important means to optimize the MCT device at present. Currently, the relatively popular RC-IGBT device and CIGBT device are to combine a thyristor and an IGBT together, utilize their respective excellent characteristics to better control the switching process. Such a new device has a small conduction voltage drop, and the excess carriers during turn-off can also quickly flow to the cathode region, accelerating the turn-off speed and reducing the turn-off loss.

[0004] Since the thyristor device plays a crucial role in power conversion, but during the process of converting electrical energy, the thyristor itself will also consume a part of the energy and generate energy loss. At the same time, the turn-off speed of the device itself is too slow, and the tail current is too long, which will reduce the working efficiency of the entire system. Moreover, the conduction loss of the lateral device is too large, the voltage and power used are relatively small, and the applicable range becomes narrow. On the other hand, in the power conversion system, it is inevitable to use capacitor or inductor components, which increases the parasitic effects in the system and the working stability of the system cannot be guaranteed.

[0005] Previously, in order to reduce the turn-off loss and improve the device performance, a vertical hybrid carrier control device was proposed. Two P-type regions with different doping concentrations and areas were used. Additionally, a lightly doped P-type region was introduced in the upper right region of the device to form a depletion-type PMOS structure, which diverted a part of the hole carriers during the turn-on process and reduced the conductance modulation effect of the device. During turn-off, a carrier extraction channel was formed, and all the excess carriers inside the device flowed away through this channel, accelerating the carrier extraction speed and reducing the turn-off loss. The problems of poor trade-off relationship between on-state voltage drop and turn-off loss, weak electromagnetic interference resistance, and poor practicability were solved. However, there are still limitations in the connection method of vertical devices in the circuit, resulting in less extensive use than horizontal carrier devices, and horizontal carrier devices have a higher reverse breakdown voltage. Summary of the Invention

[0006] In view of the above deficiencies of the prior art, the present invention provides a lateral hybrid carrier control device, which solves the problems of large on-state loss, small current density, narrow application range, poor trade-off relationship between on-state voltage drop and turn-off loss, weak electromagnetic interference resistance, and poor practicability of existing lateral power devices.

[0007] To achieve the above invention purpose, the technical solution adopted by the present invention is as follows:

[0008] Provide a lateral hybrid carrier control device, which includes a main working unit, a PMOS region, a carrier distribution region, an insulating region, and a substrate region; the insulating region is disposed above the substrate region, and the main working unit includes a second electrode, a third electrode, a first insulating material, a second electrode heavily doped ohmic contact region, a second electrode base region, a third electrode base region, a first conductivity type semiconductor, and an isolation region;

[0009] The PMOS region includes a second electrode, a fourth electrode, a second insulating material, a second conductivity type semiconductor, a fourth electrode heavily doped ohmic contact region, and a fourth electrode base region;

[0010] The carrier distribution region includes a drift region, a buffer region, a first electrode heavily doped ohmic contact region, and a first electrode;

[0011] The second electrode base region, the third electrode base region, the drift region, and the buffer region are disposed on the insulating region and are horizontally arranged in sequence along the length direction on the insulating region;

[0012] The second electrode is disposed above the second electrode base region; the second electrode heavily doped ohmic contact region is disposed in the second electrode base region, and the second electrode heavily doped ohmic contact region contacts the second electrode;

[0013] The second electrode base region and the third electrode base region are connected to the isolation region beside them, and the isolation region is distributed along the width direction of the insulation region. A semiconductor of the first conduction type is provided between the third electrode base region and the drift region, and the semiconductor of the first conduction type is connected to the third electrode base region and the isolation region;

[0014] The second electrode penetrates and connects the second electrode heavily doped ohmic contact region, the second electrode base region and the isolation region; A third electrode is provided above the third electrode base region, and a first insulating material is provided between the third electrode and the third electrode base region, and the first insulating material contacts the second electrode heavily doped ohmic contact region; A fourth electrode is provided above the insulation region, and a second insulating material is provided between the fourth electrode and the insulation region;

[0015] Above the buffer region, a first electrode heavily doped ohmic contact region and a first electrode are sequentially stacked. A fourth electrode heavily doped ohmic contact region is provided in the fourth electrode base region, and the upper end of the fourth electrode heavily doped ohmic contact region contacts the second electrode and the second insulating material. A semiconductor of the second conduction type is connected beside the fourth electrode base region. The fourth electrode base region and the semiconductor of the second conduction type are arranged along the length direction of the insulation region, and the semiconductor of the first conduction type and the semiconductor of the second conduction type are arranged along the width direction of the insulation region.

[0016] Furthermore, the cross-section of the first electrode heavily doped ohmic contact region is a quarter-circular structure, the cross-section of the buffer region is a quarter-circular ring structure, and the first electrode is provided on the upper surface of the first electrode heavily doped ohmic contact region.

[0017] Furthermore, the first electrode, the second electrode, the third electrode, the fourth electrode, the first insulating material, and the second insulating material are all cuboid structures, and the heights of the first electrode and the second electrode, the third electrode and the fourth electrode, the first insulating material and the second insulating material are the same;

[0018] The heights of the first electrode and the second electrode are greater than the heights of the first insulating material, the second insulating material, the third electrode, and the fourth electrode;

[0019] The widths of the first electrode and the second electrode, the first insulating material and the third electrode, and the second insulating material and the fourth electrode are the same;

[0020] The widths of the first electrode and the second electrode are greater than the widths of the third electrode and the fourth electrode, the width of the third electrode is greater than the width of the fourth electrode, and the lengths of the first insulating material and the third electrode, and the second insulating material and the fourth electrode are the same.

[0021] Furthermore, the first insulating material, the second insulating material, and the insulation region are all silicon dioxide; the second electrode heavily doped ohmic contact region, the third electrode base region, the drift region, and the buffer region are all N-type doped silicon;

[0022] The second electrode base region, the first-conductivity-type semiconductor, the first electrode heavily doped ohmic contact region, the substrate region, the fourth electrode heavily doped ohmic contact region, the fourth electrode base region, and the second-conductivity-type semiconductor are all P-type doped silicon.

[0023] Furthermore, the first insulating material and the second insulating material doped with silicon dioxide form an oxide layer structure to isolate the third electrode and the fourth electrode above the first insulating material and the second insulating material from the doped regions.

[0024] Furthermore, the length of the insulating region is the same as the length of the substrate region, and the width of the insulating region is the same as the width of the substrate region; the thickness of the second electrode base region is the same as that of the third electrode base region, the first-conductivity-type semiconductor, the second-conductivity-type semiconductor, the fourth electrode base region, the drift region, and the buffer region.

[0025] The beneficial effects of the present invention are as follows: On the basis of a conventional lateral thyristor device, the present invention utilizes two P-type regions with different doping concentrations and areas, and additionally introduces a low-doped P-type region on the left side of the high-doped P-type region to form a depletion-type PMOS structure, achieving the purpose of shunt control of electron and hole carriers.

[0026] Two parallel channels are formed in the device of the present invention; when turned on, the two channels work simultaneously, and carriers flow through the two channels, reducing the charge accumulated near the gate electrode and effectively reducing the transient current during the device turn-on process.

[0027] The carrier distribution region provided on the right side of the main working unit and the PMOS region, since both electron and hole carriers flow through this region, a conductance modulation effect is formed in this region, reducing the on-state voltage drop of the device; when turned off, the excess carriers in the device can be quickly extracted, effectively solving the contradictory relationship between the on-state voltage drop and the turn-off loss, and improving the performance of the device during turn-on and turn-off. The structure of the present invention is no longer limited to the use in low-power and low-voltage fields only, and its application range becomes wider. Moreover, the present invention has good process compatibility and can be easily fabricated by existing processes.

[0028] After applying an appropriate voltage to the third electrode, a conductive channel is formed in the second electrode base region and the first-conductivity-type semiconductor. All the electrodes are located on the surface of the device, making the connection more convenient. After applying an appropriate voltage to the third electrode, a conductive channel can be formed in the region below the electrode, and the formed channel area is large. Therefore, the electrons injected from the cathode can flow through the device quickly, enabling the device to turn on quickly. At the same time, the isolation region successfully separates the main working area from other parts, enabling the device to control carriers, and the carriers flowing through the main working area are not interfered by other regions.

[0029] During the conduction of the entire device, a part of the hole carriers flow through the PMOS region, realizing the control effect on the hole carriers. When turned off, the excess carriers in the device flow through the PMOS region, accelerating the turn-off speed and reducing the turn-off loss. All the electrodes are set on the surface of the chip, making it very easy to connect each region through the electrodes, greatly simplifying the circuit and facilitating the realization of the device functions.

[0030] Both electrons and hole carriers flow through the carrier distribution region to realize the conduction of the device. At the same time, the electron carriers injected from the cathode and the hole carriers injected from the anode both pass through the drift region, where a conductivity modulation effect can be formed, effectively reducing the on-state voltage drop of the device. Compared with the vertical device, the drift region of the present invention can also form a conductivity modulation effect. The buffer region improves the breakdown voltage of the device and enhances its breakdown voltage capability.

[0031] The insulation region isolates the upper region from the underlying substrate, resulting in a high device integration degree and strong anti-latch-up ability. Description of the Drawings

[0032] Figure 1 It is a schematic structural diagram of a lateral hybrid carrier control device.

[0033] Figure 2 It is Figure 1 the schematic cross-sectional structure diagram along AA' in

[0034] Figure 3 It is Figure 1 the schematic cross-sectional structure diagram along BB' in

[0035] Figure 4 It is Figure 1 the schematic cross-sectional structure diagram along CC' in

[0036] Figure 5 It is Figure 1 the schematic cross-sectional structure diagram along DD' in

[0037] Figure 6 It is Figure 1 the schematic cross-sectional structure diagram along EE' in

[0038] Figure 7 It is Figure 1 the schematic cross-sectional structure diagram along FF' in

[0039] Figure 8 It is a schematic structural diagram of a device with an increased area of the second-conductivity-type semiconductor.

[0040] Figure 9 It is a schematic structural diagram of a device with an increased area of the fourth electrode.

[0041] Figure 10 Schematic diagram of a device structure for increasing the area of the third electrode.

[0042] Figure 11 Schematic diagram of a device structure for increasing the area of the semiconductor of the first conductivity type.

[0043] Figure 12 Schematic diagram of a device structure for reducing the area of the semiconductor of the first conductivity type.

[0044] Figure 13 Schematic diagram of a device structure with the semiconductors of the second conductivity type disposed on both sides.

[0045] Figure 14 Schematic diagram of a structure for increasing the area of the fourth electrode disposed separately.

[0046] Figure 15 Schematic diagram of a device structure with the semiconductors of the first conductivity type disposed on both sides.

[0047] Among them, 101 - the first electrode, 111 - the second electrode, 121 - the third electrode, 131 - the fourth electrode, 201 - the first insulating material, 211 - the second insulating material, 301 - the heavily doped ohmic contact region of the second electrode, 401 - the base region of the second electrode, 311 - the base region of the third electrode, 411 - the semiconductor of the first conductivity type, 431 - the semiconductor of the second conductivity type, 441 - the heavily doped ohmic contact region of the fourth electrode, 451 - the base region of the fourth electrode, 321 - the drift region, 331 - the buffer region, 421 - the heavily doped ohmic contact region of the first electrode, 501 - the insulating region, 511 - the substrate region, 221 - the isolation region. Detailed implementation manners

[0048] The following describes the detailed implementation manners of the present invention to facilitate the understanding of the present invention by those skilled in the art of the present technology. However, it should be clear that the present invention is not limited to the scope of the detailed implementation manners. For those ordinary skilled in the art of the present technology, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concept of the present invention are within the scope of protection.

[0049] Embodiment 1

[0050] As Figures 1 to 7 shown, the lateral hybrid carrier control device of this solution includes a main working unit, a PMOS region, a carrier distribution region, an insulating region, and a substrate region; the main working unit and the PMOS region are respectively disposed on both sides of the isolation region; the main working unit, the PMOS region, the isolation region, and the carrier distribution region are disposed on the insulating region.

[0051] In this embodiment, the main working units include a second electrode 111, a third electrode 121, a first insulating material 201, a second electrode heavily doped ohmic contact region 301, a second electrode base region 401, a third electrode base region 311, a first conductivity type semiconductor 411, and an isolation region 221;

[0052] The third electrode 121 is disposed above the first insulating material 201. The second electrode base region 401 is disposed at the lower ends of the second electrode 111 and the first insulating material 201. The second electrode heavily doped ohmic contact region 301 is disposed inside the second electrode base region 401 and at the lower ends of the second electrode 111 and the first insulating material 201. The third electrode base region 311 is disposed on the right side of the second electrode base region 401 and at the lower end of the first insulating material 201. The isolation region 221 is disposed behind the second electrode base region 401 and the third electrode base region 311. The first conductivity type semiconductor 411 is disposed on the right side of the third electrode base region 311 and the isolation region 221 and at the lower end of the first insulating material 201. The second electrode heavily doped ohmic contact region 301 contacts the second electrode 111 and the first insulating material 201.

[0053] Through the above design, two NMOS transistor structures will be formed in the present invention. After applying a positive voltage to the fourth electrode 131, a large number of electron carriers will be quickly injected into the formed NMOS transistor, prompting the device to turn on.

[0054] In this embodiment, the PMOS region includes a second electrode 111, a fourth electrode 131, a second insulating material 211, a second conductivity type semiconductor 431, a fourth electrode heavily doped ohmic contact region 441, and a fourth electrode base region 451;

[0055] The fourth electrode 131 is disposed above the second insulating material 211. The second electrode 111 and the second insulating material 211 are disposed above the fourth electrode base region 451. The fourth electrode heavily doped ohmic contact region 441 is disposed inside the fourth electrode base region 451 and below the second electrode 111 and the second insulating material 211. The second conductivity type semiconductor 431 is disposed on the right side of the fourth electrode base region 451.

[0056] Through the above design of the present invention, during conduction, a part of the hole carriers flow into the second conductivity type semiconductor 431, and then pass through the fourth electrode base region 451 and the fourth electrode heavily doped ohmic contact region 441 and finally reach the fifth electrode. A new current path is formed inside the device of the present invention, which plays a role in shunting the hole carriers in the structure, reducing the conductance modulation effect during conduction of the present invention, effectively reducing the saturation current of the present invention, and increasing the safe operating area. During turn-off, all the hole carriers pass through the second conductivity type semiconductor and all enter the fourth electrode base region 451 and the fourth electrode heavily doped ohmic contact region 441 and finally reach the second electrode 111, accelerating the extraction speed of the excess carriers and reducing the turn-off loss.

[0057] In this embodiment, the carrier distribution region includes a drift region 321, a buffer region 331, a first electrode heavily doped ohmic contact region 421, and a first electrode 101;

[0058] The drift region 321 is disposed on the right side of the first conductivity type semiconductor 411 and the second conductivity type semiconductor 431. The buffer region 331 is disposed on the right side of the drift region 321. The first electrode heavily doped ohmic contact region 421 is disposed inside the buffer region 331 and at the lower end of the first electrode 101. Through the above design, the present invention realizes the conduction of carriers in the device, and at the same time, effectively improves the breakdown voltage of the device.

[0059] In this embodiment, the insulating region 501 is disposed below the main working unit, the PMOS region, and the carrier distribution region; the substrate region 511 is disposed below the insulating region 501. Through the above design, the present invention isolates the substrate from the main working area of the device and enhances the anti-latch-up ability of the device.

[0060] In this embodiment, the first electrode 101, the second electrode 111, the third electrode 121, the fourth electrode 131, the first insulating material 201, and the second insulating material 211 are all cuboids. The first electrode 101 and the second electrode 111 have the same height. The first insulating material 201 and the second insulating material 211 have the same height. The third electrode 121 and the fourth electrode 131 have the same height;

[0061] The height of the first electrode 101 and the second electrode 111 is greater than the height of the first insulating material 201, the second insulating material 211, the third electrode 121, and the fourth electrode 131;

[0062] The first electrode 101 and the second electrode 111 have the same width. The first insulating material 201 and the third electrode 121 have the same width. The second insulating material 211 and the fourth electrode 131 have the same width. The width of the first electrode 101 and the second electrode 111 is greater than the width of the third electrode 121 and the fourth electrode 131. The width of the third electrode 121 is greater than the width of the fourth electrode 131. The first insulating material 201 and the third electrode 121 have the same length. The second insulating material 211 and the fourth electrode 131 have the same length.

[0063] In this embodiment, the first insulating material 201, the second insulating material 211, and the insulating region 501 are all silicon dioxide; the second electrode heavily doped ohmic contact region 301, the third electrode base region 311, the drift region 321, and the buffer region 331 are all N-type doped silicon; the second electrode base region 401, the first conductivity type semiconductor 411, the first electrode heavily doped ohmic contact region 421, and the substrate region 511 are all P-type doped silicon.

[0064] In this embodiment, the length of the insulation region 501 is the same as that of the substrate region 511; the width of the insulation region 501 is the same as that of the substrate region 511; the thicknesses of the second electrode base region 401, the third electrode base region 311, the first conductivity type semiconductor 411, the second conductivity type semiconductor 431, the fourth electrode base region 451, the drift region 321, and the buffer region 331 are the same;

[0065] In this embodiment, the cross-sectional area of the first insulating material 201 is larger, and it is in contact with the second electrode base region 401 and the first conductivity type semiconductor 411, which enables two NMOS transistor structures to be formed under the first insulating material 201. During the conduction process, electron carriers can be quickly injected, accelerating the turn-on speed of the structure of the present invention.

[0066] In this embodiment, the first insulating material 201 and the second insulating material 211 in the present invention are doped with silicon dioxide to form an oxide layer structure, which isolates the metal electrode above the insulating material from the doped region; the second electrode heavily doped ohmic contact region 301 and the third electrode base region 311 are both N-type doped and can inject electrons during conduction; the second electrode base region 401 and the first conductivity type semiconductor 411 are P-type doped silicon. On the one hand, an inversion layer channel is formed during the conduction process, and on the other hand, hole carriers can flow into this region when conducting;

[0067] In this embodiment, the fourth electrode heavily doped ohmic contact region 441, the fourth electrode base region 451, and the second conductivity type semiconductor 431 are P-type doped silicon, forming a depletion-type PMOS structure. During conduction, a part of the hole carriers flow through here, reducing the conductance modulation effect. When turned off, all the excess carriers flow through this region, accelerating the turn-off speed and reducing the tail current and turn-off loss.

[0068] In this embodiment, based on a conventional lateral power semiconductor device, the present invention combines the principle of electron and hole carrier shunting and introduces P-type regions with different doping concentrations: the first conductivity type semiconductor 411 and the second conductivity type semiconductor 431. Due to the different doping concentrations of the two P-type regions, electrons tend to flow to the P-type region with a lower concentration, and hole carriers tend to flow to the P-type region with a higher concentration, enabling the structure of the present invention to successfully separate electrons and hole carriers. Additionally, in the right upper region of the structure of the present invention, a low-doped P-type region is introduced to form a PMOS structure (the second conductivity type semiconductor 431, the fourth electrode heavily doped ohmic contact region 441, and the fourth electrode base region 451 constitute the PMOS structure).

[0069] The present invention forms two different conduction channels in the structure, increasing the path for carriers to flow through the device. All electrodes are designed on the surface of the device, enabling direct and convenient connection of various regions inside the device through the electrodes. Meanwhile, compared with vertical devices, the lateral device of the present invention has better process compatibility, a simple process flow, and is easy to implement in terms of process.

[0070] When the present invention conducts, a conductance modulation effect can be formed in both two P-type regions with different doping concentrations and the drift region, effectively reducing the on-state voltage drop of the device and increasing the current density flowing through the device. During the turn-on transient, since two conduction channels are formed inside the device, the amount of charge accumulated near the gate electrode is reduced, making the transient current generated during the turn-on process smaller, effectively protecting the device and preventing the device from being damaged due to excessive transient current.

[0071] The electromagnetic interference resistance of the device becomes stronger, effectively protecting the device structure and enabling the device to operate safely. Meanwhile, during turn-off, the PMOS structure introduced by the present invention forms a channel, which can quickly extract the excess carriers inside the device, reducing the turn-off loss of the device, effectively solving the contradictory relationship between the on-state voltage drop and the turn-off loss, and improving the performance of the device during turn-on and turn-off.

[0072] Embodiment 2

[0073] As Figure 8 shown, the difference between this embodiment and Embodiment 1 is that the volume of the second-conductivity-type semiconductor 431 is increased, so that the isolation region contacts more with the second-conductivity-type semiconductor 431. The effect of increasing the volume of the second-conductivity-type semiconductor 431 is as follows: better maintaining the doping concentration difference relationship between the first and second-conductivity-type semiconductors, and utilizing the concentration difference formed between the two-conductivity-type semiconductors to achieve the formation of two internal conduction channels during the turn-on transient, reducing the amount of charge accumulated near the gate electrode, making the overshoot current generated during the turn-on transient smaller, the electromagnetic interference resistance stronger, effectively protecting the device structure, and enabling the device to operate safely. Meanwhile, during turn-off, the PMOS structure introduced by the present invention can quickly extract the excess carriers inside the device, reducing the turn-off loss.

[0074] Embodiment 3

[0075] As Figure 9As shown, the difference between this embodiment and Embodiment 1 lies in increasing the area of the fourth electrode 131. The fourth electrode 131 is disposed above the fourth electrode base region 451 and the second-conductivity-type semiconductor 341, such that the fourth electrode 131 simultaneously covers the fourth electrode base region 451 and the second-conductivity-type semiconductor 431. The effect of increasing the area of the fourth electrode 131 is that after applying an appropriate voltage to the fourth electrode 131, a conductive channel can be formed in the region under the electrode, and the formed channel area is larger. Electrons injected from the cathode can flow through the device faster, enabling the device to turn on faster.

[0076] Embodiment 4

[0077] As Figure 10 shown, the difference between this embodiment and Embodiment 1 lies in increasing the area of the third electrode 121, such that the third electrode 121 and the fourth electrode 131 form one electrode. The effect of increasing the area of the third electrode 121 is that after applying an appropriate voltage, a conductive channel can be formed in the region under the electrode, and the formed channel area is larger. Therefore, electrons injected from the cathode can flow through the device faster, enabling the device to turn on faster.

[0078] Embodiment 5

[0079] As Figure 11 shown, the difference between this embodiment and Embodiment 1 lies in reducing the size of the second-conductivity-type semiconductor 431, such that a gap is formed between the second-conductivity-type semiconductor 431 and the drift region 321. The width of the second-conductivity-type semiconductor 431 is the same as that of the fourth electrode 131. The effect of this embodiment is that when conducting, carriers all flow into the first-conductivity-type semiconductor 411 through the drift region 321, effectively reducing the on-state voltage drop of the device and increasing the current density. By utilizing the change in the concentration difference at the contact part between the first-conductivity-type semiconductor 411 and the second-conductivity-type semiconductor 431, the formation of two internal conductive channels during the turn-on transient is promoted, the extraction of excess carriers inside the device is accelerated, the amount of charge accumulated near the gate electrode is reduced, the overshoot current generated during the turn-on transient is decreased, and the electromagnetic interference resistance is enhanced, effectively protecting the device structure. At the same time, when turning off, the PMOS structure introduced in the present invention can quickly extract the excess carriers in the device, effectively improving the contradictory relationship between the on-state voltage drop and the turn-off loss.

[0080] Embodiment 6

[0081] As Figure 12As shown, the difference between this embodiment and Embodiment 1 lies in that the width dimensions of the second-conductivity-type semiconductor 431 and the isolation region 221 are increased, so that the isolation region 221 and the second-conductivity-type semiconductor 431 extend below the third electrode 121, and the size of the first-conductivity-type semiconductor 411 is reduced, so that a gap is formed between the first-conductivity-type semiconductor 411 and the drift region 321. Its advantages are as follows: When conducting, carriers all flow into the second-conductivity-type semiconductor 431 through the drift region 321, which plays a role in controlling the hole carriers in the device, reduces the conductance modulation effect of the present invention in the main working region and the PMOS region, effectively reduces the saturation current of the present invention, and improves the safe operating area. Utilizing the change in the concentration difference at the contact part between the first-conductivity-type semiconductor 411 and the second-conductivity-type semiconductor 431 promotes the formation of two internal conduction channels during the turn-on transient, accelerates the extraction of excess carriers inside the device, reduces the amount of charge accumulated near the gate electrode, reduces the overshoot current generated during the turn-on transient, enhances the anti-electromagnetic interference ability, and effectively protects the device structure. At the same time, when turning off, the PMOS structure introduced by the present invention can quickly extract the excess carriers in the device, effectively improving the contradictory relationship between the on-state voltage drop and the turn-off loss.

[0082] Embodiment 7

[0083] As Figure 13 shown, the difference between this embodiment and Embodiment 1 lies in that fourth electrodes 131 are provided on both sides of the third electrode 121 in the width direction, fourth electrode base regions 451 are provided below both sides of the fourth electrodes 131, and the third electrode base region 311 is clamped between the two fourth electrode base regions 451. Its advantages are as follows: Two PMOS structures are formed, and more current channels are formed during conduction, accelerating the extraction of excess carriers inside the device, reducing the amount of charge accumulated near the gate electrode, reducing the overshoot current generated during the turn-on transient, enhancing the anti-electromagnetic interference ability, and effectively protecting the device structure. At the same time, when turning off, the excess carriers in the device can be extracted more quickly, effectively improving the contradictory relationship between the on-state voltage drop and the turn-off loss.

[0084] Embodiment 8

[0085] As Figure 14 shown, the difference between this embodiment and Embodiment 7 lies in that the size of the fourth electrode 131 is increased, the fourth electrode 131 covers the fourth electrode base region 451 and the second-conductivity-type semiconductor 431, and the fourth electrode 131 reaches the leftmost side of the drift region 321 in the length direction. Its advantages are as follows: After applying an appropriate voltage, conductive channels can be formed in the regions below the electrodes, and the formed channel area is larger. Therefore, electrons injected from the cathode can flow through the device faster, making the device turn on faster.

[0086] Embodiment 9

[0087] As Figure 15 shown, the difference between this embodiment and Embodiment 8 is that the fourth electrode 131 in Embodiment 7 is replaced with the third electrode 121, and the third electrode 121 in Embodiment 6 is replaced with the fourth electrode 131, so that the fourth electrode 131 is disposed between two third electrodes 121, the isolation region 211 is disposed between two third electrode base regions 311, the second conductivity type semiconductor 431 is disposed between the first conductivity type semiconductors 411, the first conductivity type semiconductors 411 and the second conductivity type semiconductor 431 are both connected to the drift region 321, and the fourth electrode 131 is disposed above the isolation region 211. Its advantages are as follows: The main working regions are separately arranged on both sides, reducing the interference of other factors on the main working regions during the conduction process. More current channels are formed during conduction, accelerating the extraction of excess carriers inside the device, reducing the amount of charge accumulated near the gate electrode, reducing the overshoot current generated during the turn-on transient, enhancing the electromagnetic interference resistance, and effectively protecting the device structure. At the same time, during turn-off, the excess carriers in the device can be more quickly extracted, effectively improving the contradictory relationship between the on-state voltage drop and the turn-off loss.

Claims

1. A lateral hybrid carrier control device, characterized in that It includes a main working unit, a PMOS region, a carrier distribution region, an insulating region, and a substrate region; the insulating region is disposed above the substrate region, and the main working unit includes a second electrode, a third electrode, a first insulating material, a second electrode heavily doped ohmic contact region, a second electrode base region, a third electrode base region, a first conductivity type semiconductor, and an isolation region; The PMOS region includes a second electrode, a fourth electrode, a second insulating material, a second conductivity type semiconductor, a fourth electrode heavily doped ohmic contact region, and a fourth electrode base region; The carrier distribution region includes a drift region, a buffer region, a first electrode heavily doped ohmic contact region, and a first electrode; The second electrode base region, the third electrode base region, the drift region, and the buffer region are disposed on the insulating region and are horizontally arranged in sequence along the length direction on the insulating region; The second electrode is disposed above the second electrode base region; the second electrode heavily doped ohmic contact region is disposed in the second electrode base region, and the second electrode heavily doped ohmic contact region contacts the second electrode; The isolation region is connected beside the second electrode base region and the third electrode base region, and the isolation region is distributed along the width direction of the insulating region. A first conductivity type semiconductor is disposed between the third electrode base region and the drift region, and the first conductivity type semiconductor connects the third electrode base region and the isolation region; The second electrode penetrates and connects the second electrode heavily doped ohmic contact region, the second electrode base region, and the isolation region; the third electrode is disposed above the third electrode base region, and a first insulating material is disposed between the third electrode and the third electrode base region, and the first insulating material contacts the second electrode heavily doped ohmic contact region; a fourth electrode is disposed above the insulating region, and a second insulating material is disposed between the fourth electrode and the insulating region; The first electrode heavily doped ohmic contact region and the first electrode are sequentially stacked above the buffer region. The fourth electrode heavily doped ohmic contact region is disposed in the fourth electrode base region, and the upper end of the fourth electrode heavily doped ohmic contact region contacts the second electrode and the second insulating material. The second conductivity type semiconductor is connected beside the fourth electrode base region, and the fourth electrode base region and the second conductivity type semiconductor are arranged along the length direction of the insulating region. The first conductivity type semiconductor and the second conductivity type semiconductor are arranged along the width direction of the insulating region.

2. The lateral hybrid carrier control device according to claim 1, wherein The cross section of the first electrode heavily doped ohmic contact region is a quarter-circular structure, the cross section of the buffer region is a quarter-circular ring structure, and the first electrode is disposed on the upper surface of the first electrode heavily doped ohmic contact region.

3. The lateral hybrid carrier control device according to claim 1, characterized in that, The first electrode, the second electrode, the third electrode, the fourth electrode, the first insulating material, and the second insulating material are all in a cuboid structure, and the heights of the first electrode and the second electrode, the third electrode and the fourth electrode, and the first insulating material and the second insulating material are the same; The heights of the first electrode and the second electrode are greater than the heights of the first insulating material, the second insulating material, the third electrode, and the fourth electrode; The widths of the first electrode and the second electrode, the first insulating material and the third electrode, and the second insulating material and the fourth electrode are the same; The widths of the first electrode and the second electrode are greater than those of the third electrode and the fourth electrode, the width of the third electrode is greater than that of the fourth electrode, and the lengths of the first insulating material and the third electrode and the second insulating material and the fourth electrode are the same.

4. The lateral hybrid carrier control device according to claim 1, wherein, The first insulating material, the second insulating material, and the insulating region are all silicon dioxide; the second electrode heavily doped ohmic contact region, the third electrode base region, the drift region, and the buffer region are all N-type doped silicon; The second electrode base region, the first conductive type semiconductor, the first electrode heavily doped ohmic contact region, the substrate region, the fourth electrode heavily doped ohmic contact region, the fourth electrode base region, and the second conductive type semiconductor are all P-type doped silicon.

5. The lateral hybrid carrier control device according to claim 4, wherein The doped silicon dioxides of the first insulating material and the second insulating material form an oxide layer structure to isolate the third electrode and the fourth electrode above the first insulating material and the second insulating material from the doped regions.

6. The lateral hybrid carrier control device according to claim 1, wherein, The length of the insulating region is the same as that of the substrate region, and the width of the insulating region is the same as that of the substrate region; the thicknesses of the second electrode base region, the third electrode base region, the first conductive type semiconductor, the second conductive type semiconductor, the fourth electrode base region, the drift region, and the buffer region are the same.

7. The lateral hybrid carrier control device according to claim 1, wherein The fourth electrode is disposed above the fourth electrode base region and the second conductive type semiconductor, so that the fourth electrode covers the fourth electrode base region and the second conductive type semiconductor.

8. The lateral hybrid carrier control device according to claim 1, wherein The third electrode and the fourth electrode form a single electrode.

9. The lateral hybrid carrier control device according to claim 1, wherein The widths of the second conductive type semiconductor and the isolation region are increased, so that the isolation region and the second conductive type semiconductor extend below the third electrode, and the size of the first conductive type semiconductor is reduced, resulting in a gap being formed between the first conductive type semiconductor and the drift region.

10. The lateral hybrid carrier control device according to claim 1, characterized in that, The fourth electrodes are disposed on both sides of the third electrode in the width direction, the fourth electrode base regions are disposed below both of the fourth electrodes on both sides, and the third electrode base region is clamped between the two fourth electrode base regions.

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