A ring gate transistor and a method of manufacturing the same

Abstract

The application discloses a ring gate transistor and a manufacturing method thereof, and relates to the technical field of semiconductors, so that the ring gate transistor has asymmetric switching current and meets the working requirements of corresponding application scenarios. The ring gate transistor comprises a first active region, a second active region, a channel and a gate stack structure. The channel is located between the first active region and the second active region and contacts the first active region and the second active region respectively. The gate stack structure surrounds the outer periphery of the channel. The channel comprises at least one first nanostructure. In the direction from the first active region to the second active region, each first nanostructure has a first region and a second region which are covered by the gate stack structure. In the same first nanostructure, the width and the thickness of the first region are smaller than the width and the thickness of the second region respectively.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gate-ring transistor and its manufacturing method. Background Technology

[0002] Gate-around transistors (GMT-A) have advantages over planar transistors and fin field-effect transistors, such as higher gate control capability, which can improve the operating performance of semiconductor devices including GMT-A.A. transistors.

[0003] However, in some special applications, gate-around transistors (GMT-A) require asymmetrical switching currents (e.g., access transistors included in magnetic random access memory). Existing GMT-A, manufactured using conventional GMT-A processes, typically have symmetrical switching currents, making them unsuitable for these applications. Summary of the Invention

[0004] The purpose of this invention is to provide a gate-ring transistor and its manufacturing method, so that the gate-ring transistor has an asymmetrical switching current to meet the working requirements of the corresponding application scenarios.

[0005] To achieve the above objectives, the present invention provides a gate-ring transistor, comprising: a first active region, a second active region, a channel, and a gate stack structure. The channel is located between and contacts the first and second active regions, respectively. The gate stack structure surrounds the outer periphery of the channel. The channel includes at least one first nanostructure. Along the direction from the first active region to the second active region, the portion of each first nanostructure covered by the gate stack structure has a first region and a second region. Within the same first nanostructure, the width and thickness of the first region are smaller than the width and thickness of the second region, respectively.

[0006] Compared with the prior art, the ring-gate transistor provided by the present invention includes a channel located between a first active region and a second active region, comprising at least one first nanostructure. Along the direction from the first active region to the second active region, each first nanostructure covered by the gate stack structure has a first region and a second region. Within the same first nanostructure, the width and thickness of the first region are smaller than the width and thickness of the second region, respectively. In this case, the cross-sectional area of ​​the first region within the same first nanostructure is smaller than the cross-sectional area of ​​the second region. Based on this, since resistance is inversely proportional to cross-sectional area, the resistance of the portion of each first nanostructure located in the first region is greater than the resistance of its portion located in the second region. Furthermore, when the cross-sectional area of ​​the first region is smaller than the cross-sectional area of ​​the second region, the control capability of the gate stack structure over the portion of each first nanostructure located in the first region is greater than its control capability over the portion of each first nanostructure located in the second region. In this situation, where the resistance of each first nanostructure located in the first region and the second region are different, and the control capability of the gate stack structure over each first nanostructure located in the first region and the second region is different, the ring-gate transistor exhibits an asymmetrical switching current after being turned on, thereby meeting the operational requirements of the corresponding application scenario.

[0007] The present invention also provides a method for manufacturing a gate-around transistor, the method comprising:

[0008] Provide a semiconductor substrate.

[0009] A first active region, a second active region, and a channel are formed on a semiconductor substrate. The channel is located between the first active region and the second active region, and is in contact with both the first active region and the second active region.

[0010] A gate stack structure is formed around the outer periphery of the channel. The channel includes at least one first nanostructure. Along the direction from the first active region to the second active region, the portion of each first nanostructure covered by the gate stack structure has a first region and a second region. Within the same first nanostructure, the width and thickness of the first region are smaller than the width and thickness of the second region, respectively.

[0011] Compared with the prior art, the beneficial effects of the manufacturing method of the ring gate transistor provided by the present invention can be referred to the analysis of the beneficial effects of the ring gate transistor described above, and will not be repeated here. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0013] Figure 1 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 1 ;

[0014] Figure 2 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 2 ;

[0015] Figure 3 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 3 ;

[0016] Figure 4 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 4 ;

[0017] Figure 5 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 5 ;

[0018] Figure 6 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 6 ;

[0019] Figure 7 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 7 ;

[0020] Figure 8 Parts (1), (2), and (3) in the figure are schematic diagrams of the ring gate transistor provided in the embodiments of the present invention during the manufacturing process. Figure 8 , Nine and ten;

[0021] Figure 9 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 one;

[0022] Figure 10 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 two;

[0023] Figure 11 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 three;

[0024] Figure 12 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 Four;

[0025] Figure 13 Parts (1), (2), and (3) in the figure are schematic diagrams of the ring gate transistor provided in the embodiments of the present invention during the manufacturing process. Figure 15 , sixteen and seventeen;

[0026] Figure 14 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 eight;

[0027] Figure 15 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 10 Nine;

[0028] Figure 16 Parts (1) and (2) in the figure are schematic diagrams of the ring gate transistor provided in the embodiments of the present invention during the manufacturing process. Figure 2 Ten and twenty-one;

[0029] Figure 17 A schematic diagram of the structure of the gate-ring transistor provided in the embodiment of the present invention during the manufacturing process. Figure 2 twelve;

[0030] Figure 18 This is a flowchart illustrating a method for manufacturing a gate-ring transistor according to an embodiment of the present invention.

[0031] Reference numerals: 11 is a semiconductor substrate, 12 is a shallow trench isolation structure, 13 is a fin structure, 131 is a stack, 1311 is a sacrificial layer, 1312 is a semiconductor layer, 14 is a source / drain formation region, 15 is a channel formation region, 16 is a sacrificial gate, 17 is a gate sidewall, 18 is a first active region, 19 is a second active region, 20 is a dielectric layer, 21 is a channel pre-formation structure, 211 is a first channel portion, 2111 is a first nanostructure, 212 is a second nanostructure, 22 is a mask layer, 23 is a first region, 24 is a second region, 25 is an oxide layer, 26 is a channel, and 27 is a gate stack structure. Detailed Implementation

[0032] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0033] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0034] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0036] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] A gate-around transistor includes a channel comprising at least one layer of nanowires or sheets. Each nanowire or sheet layer has a gap with the semiconductor substrate. Furthermore, when a gate-around transistor includes at least two nanowires or sheets, gaps also exist between adjacent nanowires or sheets. Based on this, the gate stack structure of the gate-around transistor can surround the corresponding portion of each nanowire or sheet layer through the aforementioned gaps. In other words, the gate stack structure of the gate-around transistor can be formed not only on the top of each nanowire or sheet layer and on the sidewalls along the width direction, but also on the bottom of each nanowire or sheet layer. Therefore, gate-around transistors have advantages such as higher gate control capability compared to planar transistors and fin field-effect transistors, which can improve the operating performance of semiconductor devices including such gate-around transistors.

[0038] In some special applications, gate-to-ring transistors (GMT-Js) require asymmetric switching currents. For example, a magnetic random access memory (MRRAM) with a core structure consisting of a magnetic tunnel junction (MTJ) and an access transistor. The MTJ structure comprises a magnetically fixed layer, a free layer, and a tunneling layer between the fixed and free layers. The magnetization direction of the fixed layer is constant, while the magnetization direction of the free layer can be changed. When the magnetization directions of the fixed and free layers are aligned, it is called a "parallel state," and the tunnel magnetoresistance of the MTJ structure is low. Conversely, when the magnetization directions are not aligned, it is called an "anti-parallel state," and the tunnel magnetoresistance of the MTJ structure is high. In actual operation, data writing is achieved by switching the magnetization direction of the free layer, while reading is achieved by measuring the magnetoresistance by allowing current to flow through the junction. The gate of the access transistor is connected to the word line, forming a "1T1M" structure to select the memory cell. Due to the asymmetry of the MTJ structure's switching current, the write drive current of the access transistor also needs to be asymmetric.

[0039] However, gate-ring transistors manufactured using conventional gate-ring transistor processes typically have symmetrical switching currents, which makes it difficult to meet the above application requirements.

[0040] To address the aforementioned technical problems, embodiments of the present invention provide a gate-ring transistor and a method for manufacturing the same. In the gate-ring transistor provided by the embodiments of the present invention, the channel includes at least one first nanostructure. Along the direction from the first active region to the second active region, the portion of each first nanostructure covered by the gate stack structure has a first region and a second region. Within the same first nanostructure, the width and thickness of the first region are smaller than the width and thickness of the second region, respectively, so that the gate-ring transistor has an asymmetric switching current after being turned on, to meet the operating requirements of the corresponding application scenario.

[0041] like Figures 14 to 17 As shown, the ring-gate transistor provided in this embodiment of the invention includes: a first active region 18, a second active region 19, a channel 26, and a gate stack structure 27. The channel 26 is located between the first active region 18 and the second active region 19, and is in contact with both the first active region 18 and the second active region 19. The gate stack structure 27 surrounds the outer periphery of the channel 26. The channel 26 includes at least one first nanostructure 2111. Along the direction from the first active region 18 to the second active region 19, the portion of each first nanostructure 2111 covered by the gate stack structure 27 has a first region 23 and a second region 24. In the same first nanostructure 2111, the width and thickness of the first region 23 are smaller than the width and thickness of the second region 24, respectively.

[0042] Specifically, in terms of quantity, the channel may include one or more first nanostructures. When the channel includes multiple first nanostructures, the arrangement of the different first nanostructures can be set according to the actual application scenario, and no specific limitation is made here.

[0043] For example, when the channel includes multiple first nanostructures, the multiple first nanostructures can be distributed in the same layer or in different layers. Among them, different first nanostructures located in different layers can be spaced apart along the height direction of the channel; different first nanostructures located in the same layer can be spaced apart along the width direction of the gate stack structure.

[0044] For example, when the channel includes multiple first nanostructures, the multiple first nanostructures can also be spaced apart only along their own thickness direction.

[0045] From a materials perspective, each first nanostructure can be made of semiconductor materials such as silicon, silicon germanium, germanium, or group III-V compounds. When the channel comprises multiple first nanostructures, the materials of the different first nanostructures can be the same or different. The specific material of each first nanostructure can be set according to actual needs, as long as it can be applied to the gate-ring transistor provided in the embodiments of this invention.

[0046] The specific dimensions of the first and second regions of each first nanostructure can be set according to the actual application scenario, and are not specifically limited here.

[0047] In this embodiment, the lengths of the first region and the second region of each first nanostructure can be the same or different. When the channel includes multiple first nanostructures, the lengths of the first regions of different first nanostructures can be the same or different. When the lengths of the first regions of different first nanostructures are the same, the first regions of different first nanostructures are aligned end-to-end along the length direction of the first nanostructure. In this case, during the fabrication of the ring-gate transistor provided in this embodiment, the first channel portions of all fabricated first nanostructures can be simultaneously thinned under the masking action of the same mask layer. Specifically, as shown... Figures 8 to 12As shown, conventional gate-around transistor (GOT) manufacturing processes can be used to form the channel preform structure 21. After filling the mask material in the gate formation region, photolithography can be performed using a photomask corresponding to the sacrificial gate. By controlling the offset of the photomask, a negative resist photoresist mask is formed at the corresponding position of the mask material. The mask material is patterned using this photoresist mask to form a mask layer 22 covering the portion of the channel preform structure 21 corresponding to the second region 24. Then, the portion of each first channel portion 211 corresponding to the first region 23 is thinned to obtain the first nanostructure 2111. Therefore, in manufacturing the GOT transistor provided in this embodiment of the invention, a GOT transistor with asymmetric switching current can be obtained without manufacturing a new photomask, thereby reducing the manufacturing cost of the GOT transistor and facilitating the mass production of semiconductor devices including the GOT transistor.

[0048] It should be noted that when the channel includes a first nanostructure, the first nanostructure can also be formed using a photomask for fabricating a sacrificial gate, thereby reducing the manufacturing cost of the gate-around transistor.

[0049] Furthermore, the width of the first region of different first nanostructures can be the same or different. The thickness of the first region of different first nanostructures can also be the same or different. In practical applications, all other things being equal, if the materials of the different first nanostructures are different, then after thinning the first channel portion, the width and thickness of the first region of the different first nanostructures may differ. If the materials of the different first nanostructures are the same, then after thinning the first channel portion, the width and thickness of the first region of the different first nanostructures will be the same. Based on this, the material of the different first nanostructures can be determined according to the size requirements of the first region of the different first nanostructures in the actual application scenario.

[0050] Secondly, it is understandable that when the width and thickness of the first region in the same first nanostructure are smaller than the width and thickness of the second region, the cross-sectional area of ​​the first region in the same first nanostructure is smaller than the cross-sectional area of ​​the second region. Based on this, since resistance is inversely proportional to cross-sectional area, the resistance of the portion of each first nanostructure located in the first region is greater than the resistance of its portion located in the second region. Furthermore, when the cross-sectional area of ​​the first region is smaller than the cross-sectional area of ​​the second region, the gate stack structure's control over the portion of each first nanostructure located in the first region is greater than its control over the portion located in the second region. In this case, with different resistances in the first and second regions for each first nanostructure and different control capabilities of the gate stack structure for each first nanostructure located in the first and second regions, the gate-ring transistor exhibits an asymmetrical switching current after being turned on, to meet the operational requirements of the corresponding application scenarios. Based on this, the specific relationship between the width and thickness of the first and second regions can be determined according to the required magnitude of the asymmetrical switching current of the gate-ring transistor in different application scenarios.

[0051] For example, the ratio of the width of the first region to the width of the second region of each first nanostructure can range from 1:2 to 4:5.

[0052] For example, the thickness of the first region of each first nanostructure can be 1 nm to 6 nm smaller than the thickness of the second region it has.

[0053] From a structural perspective, such as Figures 14 to 17 As shown, the channel 26 may further include at least one second nanostructure 212. The at least one second nanostructure 212 is spaced apart from at least one first nanostructure 2111. The material of the at least one second nanostructure 212 is different from the material of the at least one first nanostructure 2111. Along the length direction of the gate stack structure 27, the width and thickness of each region of each second nanostructure 212 are the same.

[0054] Specifically, the number of second nanostructures included in the channel can be set according to the actual application scenario, and is not specifically limited here. The positional relationship between each second nanostructure and the first nanostructure, as well as the positional relationship between different second nanostructures when the channel includes multiple second nanostructures, can be determined with reference to the positions between different first nanostructures described above. For example: Figure 17 As shown, the second nanostructure 212 can be spaced apart from the first nanostructure 2111 along the height direction of the channel 26. Alternatively, the second nanostructure can be spaced apart from the first nanostructure along the width direction of the gate stack structure.

[0055] Furthermore, the material of the second nanostructure can be any semiconductor material different from that of the first nanostructure, as long as it remains unaffected during the thinning process of the first channel. For example, if the material of the first nanostructure is silicon, the material of the second nanostructure can be germanium.

[0056] As for the first active region and the second active region of the gate-ring transistor, one of the first active region and the other is the source region and the other is the drain region. Because the width and thickness of the first region are smaller than those of the second region, the gate-ring transistor will have an asymmetrical switching current after being turned on. Furthermore, the portion of the channel corresponding to the first region is close to the first active region. Therefore, based on the actual application scenario, the specific location of the first active region and the second active region can be determined as the source region and the drain region, depending on the conductivity type of the gate-ring transistor and the different switching current requirements between forward and reverse directions.

[0057] For example, when the gate ring transistor is an N-type gate ring transistor, if the forward switching current of the gate ring transistor is required to be greater than the reverse switching current, the first active region is the source region and the second active region is the drain region.

[0058] The materials for the first and second active regions can be any semiconductor material such as silicon, silicon germanium, or germanium. The materials of the first and second active regions can be the same as or different from the channel material. Furthermore, the type and concentration of impurity doping in the first and second active regions can be the same.

[0059] For the aforementioned gate stack structure, the gate stack structure may include at least a gate dielectric layer surrounding the outer periphery of the channel, and a gate electrode located on the gate dielectric layer. The gate dielectric layer may be made of insulating materials such as HfO2, ZrO2, TiO2, or Al2O3. The gate electrode may be made of conductive materials such as TiN, TaN, or TiSiN.

[0060] In some cases, such as Figures 14 to 17As shown, the aforementioned gate-around transistor may further include a semiconductor substrate 11, a shallow trench isolation structure 12, a gate sidewall 17, and a dielectric layer 20. The first active region 18, the second active region 19, the channel 26, and the gate stack structure 27 are formed on the semiconductor substrate 11. The specific structure of the semiconductor substrate 11 can be set according to the actual application scenario. For example, the semiconductor substrate can be a silicon substrate, a germanium-silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrates on which no other structures are formed. For another example, if the gate-around transistor provided in this embodiment is applied to a second or higher layer gate-around transistor in an integrated circuit, the semiconductor substrate may at least include a semiconductor substrate, a first layer device structure formed on the semiconductor substrate, and a dielectric layer covering the first layer device structure. In this case, the materials of each part of the semiconductor substrate can be set according to actual needs, as long as they can be applied to the gate-around transistor provided in this embodiment.

[0061] like Figure 16 As shown in parts (1) and (2) above, the shallow trench isolation structure 12 is formed on the semiconductor substrate 11 to isolate different active regions of the semiconductor substrate 11 and prevent leakage current. The thickness of the shallow trench isolation structure 12 can be set according to the actual situation. The material of the shallow trench isolation structure 12 can be insulating materials such as SiN, Si3N4, SiO2 or SiCO.

[0062] like Figure 14 , Figure 15 and Figure 17 As shown, the gate sidewall 17 is formed at least on the side of the gate stack structure 27 near the first active region 18 and on the side of the gate stack structure 27 near the second active region 19, to isolate the gate stack structure 27 from other conductive structures and improve the electrical characteristics of the gate-to-ring transistor. The thickness of the portions of the gate sidewall 17 located on both sides of the gate stack structure 27 along its length can be the same. The material of the gate sidewall 17 can be an insulating material such as silicon oxide or silicon nitride.

[0063] like Figure 14 , Figure 15 and Figure 17 As shown, the dielectric layer 20 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 27. In actual manufacturing, the presence of this dielectric layer 20 protects the first active region 18 and the second active region 19 from subsequent operations such as removing the sacrificial gate and sacrificial layer, thus improving the yield of the gate-around transistor. The dielectric layer 20 can be made of insulating materials such as silicon oxide or silicon nitride.

[0064] It is worth noting that the gate-ring transistor with asymmetric switching current provided in the embodiments of the present invention can have the same doping conditions for the first active region and the second active region, and the thickness of the portions of the gate sidewalls located on both sides of the gate stack structure along the length direction can also be the same. This can improve the compatibility of the embodiments of the present invention with conventional gate-ring transistor manufacturing processes, and further solve the problem in the prior art that achieving asymmetric switching current in a gate-ring transistor by setting asymmetric sidewalls or different doping of the source and drain regions leads to additional mask manufacturing processes required to form asymmetric sidewalls, or additional mask manufacturing processes required to form source and drain regions with different doping. This reduces the high manufacturing cost of gate-ring transistors and facilitates the mass production of semiconductor devices including such gate-ring transistors.

[0065] In one example, such as Figures 14 to 16 As shown in sections (1) and (2), the aforementioned ring gate transistor further includes an oxide layer 25 formed between the gate stack structure 27 and the first region 23 of each first nanostructure 2111.

[0066] Specifically, in the actual manufacturing process, such as Figure 10 As shown, after thinning the portion of the first channel corresponding to the first region 23 of the first nanostructure 2111 using an oxidation process, a corresponding oxide layer 25 is also formed on the portion of the first nanostructure 2111 corresponding to the first region 23. Therefore, the material of this oxide layer 25 is an oxide of the semiconductor material of the first nanostructure 2111. For example, if the material of the first nanostructure 2111 is silicon, the material of the oxide layer 25 is silicon dioxide.

[0067] The thickness of the oxide layer can be determined based on the differences between the width and thickness of the first region and the width and thickness of the second region, as well as the specific manufacturing process.

[0068] like Figure 10 As shown, if the oxide layer 25 is not etched back after the thinning process, the outer surface of the oxide layer 25 will protrude from the outer surface of the second region 24 of the corresponding first nanostructure 2111.

[0069] In addition, such as Figure 11 As shown, if the oxide layer 25 is etched back after the thinning process, the outer surface of the oxide layer 25 is flush with the outer surface of the second region 24 of the corresponding first nanostructure 2111. Alternatively, the outer surface of the oxide layer may be recessed inward relative to the outer surface of the second region of the corresponding first nanostructure.

[0070] like Figure 18 As shown, embodiments of the present invention also provide a method for manufacturing a gate-ring transistor. The following will describe a method based on... Figures 1 to 17 The illustrated perspective or cross-sectional view describes the manufacturing process. Specifically, the manufacturing method of this gate-ring transistor includes the following steps:

[0071] First, a semiconductor substrate is provided. The specific structure and materials of this semiconductor substrate can be referred to in the previous text, and will not be repeated here.

[0072] In one example, when forming the gate stack structure of the ring-gate transistor using an alternative gate process, the method for manufacturing the ring-gate transistor further includes the following steps after providing a semiconductor substrate and before performing subsequent operations:

[0073] like Figure 1 As shown, a fin structure 13 is formed on a semiconductor substrate 11. The fin structure 13 includes at least one stack 131, each stack 131 including a sacrificial layer 1311 and a semiconductor layer 1312 located on the sacrificial layer 1311. Along the length direction of the fin structure 13, the fin structure 13 includes source / drain formation regions 14 and channel formation regions 15 located between the source / drain formation regions 14.

[0074] Specifically, when the channel of the aforementioned gate-ring transistor includes only a first nanostructure, each of the aforementioned semiconductor layers is a film layer used to fabricate the corresponding first nanostructure. When the aforementioned channel includes both a first nanostructure and a second nanostructure, each semiconductor layer is a film layer used to fabricate either the corresponding first nanostructure or the corresponding second nanostructure. Therefore, the number of layers in the stacked fin structure, the material of each semiconductor layer, and the size of each semiconductor layer can be determined based on the number, material, and size of the first and second nanostructures included in the channel.

[0075] For example, when the channel includes multiple first nanostructures and the multiple first nanostructures are spaced apart along the thickness direction of the channel, the number of layers in the fin structure is equal to the number of first nanostructures included in the channel.

[0076] For example, when the channel includes multiple first nanostructures and the multiple nanostructures are spaced apart along the width direction of the gate stack structure, the fin structure includes a stack.

[0077] Furthermore, the ring-gate transistor manufactured by the manufacturing method provided in this embodiment of the invention includes a gate stack structure that surrounds the outer periphery of a first nanostructure through gaps. Alternatively, the gate stack structure surrounds the outer periphery of both the first and second nanostructures through gaps. Based on this, the sacrificial layer is used to form a film layer that at least partially covers the aforementioned gaps, and therefore the size of the sacrificial layer can be set with reference to the size of the gate stack structure. The material of each sacrificial layer is a semiconductor material different from all the semiconductor layers. For example, in a fin structure including at least one semiconductor layer made of Si, and at least one semiconductor layer made of Si...0.6 Ge 0.4 In the case of a semiconductor layer, the material of the sacrificial layer can be Si. 0.2 Ge 0.8 .

[0078] In practical applications, at least one layer of stacked material can be formed using processes such as epitaxial growth. Then, processes such as photolithography and etching are used to pattern the at least one layer of stacked material and a portion of the semiconductor substrate, forming fins on the semiconductor substrate. Finally, as... Figure 1 As shown, shallow trench isolation structures 12 are formed on the portion of the semiconductor substrate 11 exposed outside the fins using processes such as deposition and etching. The portion of each fin exposed before the shallow trench isolation structure 12 is a fin structure 13.

[0079] Next, as Figure 2 As shown, a sacrificial gate 16 is formed across the portion of the channel formation region corresponding to the fin structure 13 using processes such as deposition and etching. The material of the sacrificial gate 16 can be polysilicon or other easily removable materials.

[0080] like Figure 3 and Figure 4 As shown, if the manufactured ring gate transistor also includes gate sidewalls 17, after the sacrificial gate 16 is formed, processes such as deposition and etching can be used to form at least two gate sidewalls 17 located on both sides of the sacrificial gate 16 along the length direction.

[0081] like Figure 5 and Figure 6 As shown, the portion of the fin-shaped structure corresponding to the source / drain formation region is processed to form the first active region 18 and the second active region 19.

[0082] In practical applications, at least under the masking effect of the sacrificial gate, processes such as ion implantation can be used to directly form the portion of the fin structure corresponding to the source / drain formation region, thereby forming the aforementioned first and second active regions. Alternatively, as... Figure 5 As shown, at least under the masking effect of the sacrificial gate 16, dry etching or wet etching processes can be used to remove the portion of the source / drain formation region corresponding to the fin structure. Then, as... Figure 6 As shown, epitaxial growth and other processes can be used to form a first active region 18 and a second active region 19 on both sides of the channel formation region 15 corresponding to the fin structure.

[0083] like Figure 7As shown, in the case where the manufactured gate-ring transistor also includes a dielectric layer 20, the dielectric layer 20 can be formed on the semiconductor substrate 11 by processes such as deposition and chemical mechanical polishing after the formation of the first active region 18 and the second active region 19. The top of the dielectric layer 20 is flush with the top of the sacrificial gate 16. The material of the dielectric layer 20 can be referred to above.

[0084] like Figure 8 As shown in parts (1), (2) and (3), processes such as wet etching or dry etching can be used to remove the sacrificial gate and the portion of the channel formation region corresponding to the sacrificial layer, so as to expose the portion of the channel formation region corresponding to each semiconductor layer.

[0085] Next, as Figure 13 As shown in sections (1), (2), and (3), a first active region 18, a second active region 19, and a channel 26 are formed on the semiconductor substrate 11. The channel 26 is located between the first active region 18 and the second active region 19, and is in contact with both the first active region 18 and the second active region 19. Finally, as... Figures 14 to 17 As shown, a gate stack structure 27 is formed around the outer periphery of the channel 26. The channel 26 includes at least one first nanostructure 2111. Along the direction from the first active region 18 to the second active region 19, the portion of each first nanostructure 2111 covered by the gate stack structure 27 has a first region 23 and a second region 24. In the same first nanostructure 2111, the width and thickness of the first region 23 are smaller than the width and thickness of the second region 24, respectively.

[0086] Specifically, information on the types and doping conditions of the first and second active regions, as well as the specific structures and materials of the channel and gate stack structures, can be found in the previous text and will not be repeated here.

[0087] In one example, forming a channel on a semiconductor substrate may include the steps of:

[0088] like Figure 8 As shown in portions (1), (2), and (3) of the diagram, a channel preform structure 21 is formed on the semiconductor substrate 11. The channel preform structure 21 includes at least one first channel portion 211. Each first channel portion 211 has a gap with the semiconductor substrate 11.

[0089] Specifically, the aforementioned first channel portion is used to manufacture the first nanostructure. Therefore, information such as the number of first channel portions included in the channel preform structure and the arrangement of different first channel portions can be set with reference to information such as the number of first nanostructures included in the channel and the arrangement of different first nanostructures.

[0090] For example, when the channel includes multiple first nanostructures and the semiconductor substrates of different first nanostructures are spaced apart in the thickness direction, the preformed channel structure includes multiple first channel portions and the multiple first channel portions are spaced apart along the thickness direction of the semiconductor substrate.

[0091] Furthermore, the aforementioned pre-formed channel structure is used to fabricate the channel included in the gate-around transistor. Therefore, in cases where the channel also includes at least one second nanostructure, such as Figure 8 As shown in sections (2) and (3) above, the channel preform structure 21 further includes at least one second nanostructure 212. The at least one second nanostructure 212 is spaced apart from at least one first channel portion 211, and each second nanostructure 212 is spaced apart from the semiconductor substrate 11. The material of the at least one second nanostructure 212 is different from the material of the at least one first channel portion 211. Along the length direction of the gate stack structure 27, the width and thickness of each region of each second nanostructure 212 are the same. The number of second nanostructures 212 included in the channel preform structure 21, and the arrangement of each second nanostructure 212 with the remaining second nanostructures 212 or the first channel portion 211, can be determined with reference to the arrangement of the number of second nanostructures 212 included in the channel and the arrangement of each second nanostructure 212 with the remaining second nanostructures 212 or the first nanostructure 2111 described above.

[0092] In practical applications, such as Figure 8 As shown in sections (1), (2), and (3), after removing the sacrificial gate and the portion of the channel formation region corresponding to the sacrificial layer, the portion of each semiconductor layer located within the channel formation region is exposed, forming the aforementioned channel pre-formed structure 21. Specifically, when the channel only includes the first nanostructure, the portion of each semiconductor layer located within the channel formation region forms a corresponding first channel portion 211, and the channel pre-formed structure 21 only includes the first channel portion 211. However, when the channel includes both the first nanostructure and the second nanostructure 212, the portion of each semiconductor layer located within the channel formation region forms either a corresponding first channel portion 211 or a corresponding second nanostructure 212. In this case, the channel pre-formed structure 21 includes both the first channel portion 211 and the second nanostructure 212.

[0093] Next, as Figure 10 or Figure 12 As shown, under the masking effect of the mask layer 22, only the portion of each first channel corresponding to the first region 23 is thinned, so that each first channel forms a corresponding first nanostructure 2111. The mask layer 22 covers the portion of the channel pre-formed structure 21 corresponding to the second region 24. Figure 13 As shown, the mask layer is removed.

[0094] In practical applications, processes such as chemical vapor deposition can be used to form a mask material covering the pre-formed structure. Then, a photoresist mask covering the mask material can be formed using a photomask for fabricating a sacrificial gate. Specifically, this photoresist mask is a negative resist, and the offset of the photomask can be determined based on the lengths of the first and second regions to control the length of the exposed channel pre-formed structure. Next, under the masking effect of this photoresist mask, the mask material is patterned to obtain a mask layer. Then, as... Figure 9 As shown, by removing the photoresist layer, mask layer 22 is formed by fabricating a sacrificial gate photomask. This improves the compatibility of the manufacturing method provided in this embodiment with conventional gate-around transistor manufacturing processes, while also saving the cost of manufacturing new photomasks. Finally, as Figure 10 or Figure 12 As shown, under the masking effect of the mask layer 22, only the portion of the first region 23 corresponding to each first channel is thinned, so that each first channel forms a corresponding first nanostructure 2111. And as... Figure 13 As shown, the mask layer is removed using processes such as dry etching or wet etching.

[0095] Specifically, such as Figure 10 As shown, under the masking effect of the mask layer 22, an oxidation process can be used to thin the portion of the first channel corresponding to the first region 23. After the thinning process, as shown... Figure 10 As shown, not only can at least one first nanostructure 2111 be formed, but also an oxide layer 25 can be formed around the outer periphery of the first region 23 of each first nanostructure 2111.

[0096] Or, such as Figure 12 As shown, under the masking effect of the mask layer 22, the portion of the first region 23 corresponding to each first channel can be thinned by atomic layer etching process to form at least one first nanostructure 2111.

[0097] It should be noted that after thinning the portion of the first channel corresponding to the first region using an oxidation process, the thickness of the resulting oxide layer is usually greater than the thickness reduced in the first channel. Therefore, when the portion of the first channel corresponding to the first region is thinned using an oxidation process, and the outer surface of the oxide layer in the manufactured ring-gate transistor is flush with the outer surface of the second region of the corresponding first nanostructure, the manufacturing method of the ring-gate transistor after thinning the first region of the first channel and before forming the gate stack structure further includes: Figure 11As shown, the oxide layer 25 is thinned by using dry etching or wet etching processes so that the outer surface of the oxide layer 25 is flush with the outer surface of the second region 24 of the corresponding first nanostructure 2111.

[0098] Alternatively, when the portion of the first channel corresponding to the first region is thinned using an oxidation process, and the outer surface of the oxide layer in the manufactured ring-gate transistor is recessed inward relative to the outer surface of the second region of the corresponding first nanostructure, the manufacturing method of the ring-gate transistor further includes, after thinning the first region of the first channel and before forming the gate stack structure, using a process such as dry etching or wet etching to thin the oxide layer 25 so that the outer surface of the oxide layer is recessed inward relative to the outer surface of the second region of the corresponding first nanostructure by a target thickness.

[0099] Alternatively, in a method for manufacturing a ring-gate transistor where the portion corresponding to the first region of the first channel is thinned using an oxidation process, and the manufactured ring-gate transistor does not include an oxide layer, the manufacturing method further includes, after thinning the first region of the first channel and before forming the gate stack structure: Figure 12 As shown, the oxide layer is removed using processes such as dry etching or wet etching.

[0100] Finally, as Figures 14 to 17 As shown, a gate stack structure 27 surrounding the channel 26 can be formed using processes such as atomic layer deposition. The specific structure and materials of the gate stack structure 27 can be found in the preceding text.

[0101] Compared with the prior art, the beneficial effects of the manufacturing method of the gate ring transistor provided in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the gate ring transistor described above, and will not be repeated here.

[0102] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0103] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A gate-ring transistor, characterized in that, include: The system comprises a first active region, a second active region, a channel, and a gate stack structure; the channel is located between the first active region and the second active region, and contacts both the first active region and the second active region; the gate stack structure surrounds the outer periphery of the channel; wherein, The channel includes at least one first nanostructure; along the direction from the first active region to the second active region, each portion of the first nanostructure covered by the gate stack structure has a first region and a second region; in the same first nanostructure, the width and thickness of the first region are smaller than the width and thickness of the second region, respectively; the first nanostructure is integrally continuous along the length direction of the gate stack structure. The channel further includes at least one second nanostructure; the at least one second nanostructure is spaced apart from the at least one first nanostructure; the material of the at least one second nanostructure is different from the material of the at least one first nanostructure. Along the length of the gate stack structure, each region of the second nanostructure has the same width and the same thickness.

2. The gate-ring transistor according to claim 1, characterized in that, The ratio of the width of the first region to the width of the second region of each of the first nanostructures ranges from 1:2 to 4:5; and / or, Each of the first nanostructures has a first region that is 1 nm to 6 nm thinner than the second region it has.

3. The gate-ring transistor according to claim 1, characterized in that, The ring gate transistor further includes an oxide layer formed between the gate stack structure and a first region of each of the first nanostructures.

4. The gate-ring transistor according to claim 3, characterized in that, The outer surface of the oxide layer is flush with the outer surface of the second region of the corresponding first nanostructure.

5. The gate-to-ring transistor according to claim 1, characterized in that, The channel includes a plurality of first nanostructures; the plurality of first nanostructures are spaced apart along their own thickness direction.

6. The gate-to-ring transistor according to claim 5, characterized in that, Along the length of the first nanostructure, the first regions of different first nanostructures are aligned end to end; and / or, The widths of the first regions of the different first nanostructures are the same; and / or, The first region of the different nanostructures has the same thickness.

7. A method for manufacturing a gate-to-ring transistor, characterized in that, include: Provide a semiconductor substrate; A first active region, a second active region, and a channel are formed on the semiconductor substrate; The channel is located between the first active region and the second active region, and is in contact with the first active region and the second active region respectively; A gate stack structure is formed around the outer periphery of the channel; wherein the channel includes at least one first nanostructure; along the direction from the first active region to the second active region, the portion of each first nanostructure covered by the gate stack structure has a first region and a second region; in the same first nanostructure, the width and thickness of the first region are smaller than the width and thickness of the second region, respectively; the first nanostructure is integrally continuous along the length direction of the gate stack structure; the channel also includes at least one second nanostructure; the at least one second nanostructure is spaced apart from the at least one first nanostructure; the material of the at least one second nanostructure is different from the material of the at least one first nanostructure; Along the length of the gate stack structure, each region of the second nanostructure has the same width and the same thickness.

8. The method for manufacturing a gate-to-ring transistor according to claim 7, characterized in that, Forming the channel on the semiconductor substrate includes: A pre-formed channel structure is formed on the semiconductor substrate; the pre-formed channel structure includes at least one first channel portion; each first channel portion has a gap with the semiconductor substrate; the pre-formed channel structure further includes at least one second nanostructure; the at least one second nanostructure is spaced apart from the at least one first channel portion, and each second nanostructure is spaced apart from the semiconductor substrate; the material of the at least one second nanostructure is different from the material of the at least one first channel portion. Under the masking effect of the mask layer, only the portion of each first channel corresponding to the first region is thinned, so that each first channel forms a corresponding first nanostructure; the mask layer covers the portion of the channel preform structure corresponding to the second region; Remove the mask layer.

9. The method for manufacturing a gate-to-ring transistor according to claim 8, characterized in that, The preformed channel structure includes a plurality of first channel portions, which are spaced apart along the thickness direction of the semiconductor substrate.

10. The method for manufacturing a gate-ring transistor according to claim 8, characterized in that, The process of thinning the portion of each first channel corresponding to the first region under the masking effect of the mask layer includes: Under the masking effect of the mask layer, an oxidation process is used to thin the portion of each first channel corresponding to the first region to form the at least one first nanostructure and to form an oxide layer surrounding the outer periphery of the first region of each first nanostructure.

11. The method for manufacturing a gate-to-ring transistor according to claim 10, characterized in that, Before forming the gate stack structure surrounding the outer periphery of the channel, after thinning the portion of each first channel corresponding to the first region by an oxidation process under the masking effect of the mask layer, the manufacturing method of the ring gate transistor further includes: The oxide layer is thinned so that the outer surface of the oxide layer is flush with the outer surface of the second region of the corresponding first nanostructure.

12. The method for manufacturing a gate-ring transistor according to claim 8, characterized in that, Under the masking effect of the mask layer, the portion of each first channel corresponding to the first region is thinned using an atomic layer etching process to form the at least one first nanostructure.

13. The method for manufacturing a gate-ring transistor according to claim 8, characterized in that, After providing a semiconductor substrate, and before forming a channel pre-formation structure on the semiconductor substrate, the method for manufacturing the gate-around transistor further includes: A fin-like structure is formed on the semiconductor substrate; the fin-like structure includes at least one stack, each of the stacks including a sacrificial layer and a semiconductor layer located on the sacrificial layer; along the length direction of the fin-like structure, the fin-like structure includes source / drain formation regions and channel formation regions located between the source / drain formation regions; A sacrificial gate is formed across the portion of the fin-like structure corresponding to the channel formation region; The portion of the fin structure corresponding to the source / drain formation region is processed to form the first active region and the second active region; Remove the sacrificial gate and the portion of the sacrificial layer corresponding to the channel formation region.

14. The method for manufacturing a gate-ring transistor according to claim 13, characterized in that, The mask layer is formed using a photolithographic mask for manufacturing the sacrificial gate.

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