Level conversion circuit and drive circuit

Abstract

This application discloses a level conversion circuit and a driving circuit. The level conversion circuit includes a pulse generator, a switch unit, a conduction identification unit, a common-mode processing unit, and a trigger unit. The common-mode processing unit is used to process the common-mode interference signals of the first identification signal and the second identification signal output by the conduction identification unit; wherein, the common-mode processing unit includes a first latch and a second latch. The input end of the first latch is connected to the first identification signal terminal of the conduction identification unit, the enable end of the first latch is connected to the second identification signal terminal of the common-mode processing unit, the output end of the first latch is connected to the trigger unit, the input end of the second latch is connected to the second identification signal terminal of the conduction identification unit, the enable end of the second latch is connected to the first identification signal terminal of the conduction identification unit, and the output end of the second latch is connected to the trigger unit. By adding a common-mode processing unit, this application enables the common-mode interference signal not to be transmitted to the next stage, suppressing the influence of common-mode interference.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and particularly to a level conversion circuit and a driving circuit. Background Art

[0002] With the popularization of electric power, the application scenarios of power transistors are increasing. As the application scenarios of power supplies increase, the control requirements for power transistors are also increasing day by day. In order to enable power transistors to have better performance (switching speed, reliability, etc.), the gate driver chips used to drive power transistors are becoming increasingly important. The gate driver chip converts a low-voltage logic signal into a logic signal with a floating voltage up to a high voltage to control the on and off of the peripheral high-voltage power transistors.

[0003] Due to the parasitic capacitance between the drain terminal of the conduction recognition unit in the traditional level conversion circuit and the ground, the device connected to the drain terminal of the conduction recognition unit needs to charge the drain terminal of the conduction recognition unit. When the charging speed cannot compensate for the rising speed of the power supply of the floating well, an abnormally low level phenomenon will occur at the drain terminal of the conduction recognition unit, that is, a common-mode interference phenomenon will occur, thereby affecting the level conversion efficiency of the level conversion circuit. How to solve the influence of common-mode interference in the level conversion circuit on the circuit is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] In view of this, the present invention aims to solve at least one of the problems in the related technologies to some extent. For this purpose, the objective of this application is to provide a level conversion circuit and a driving circuit.

[0005] The level conversion circuit according to the embodiments of the present application. The level conversion circuit includes a pulse generator, a switch unit, a conduction identification unit, a common-mode processing unit, and a trigger unit. The pulse generator is configured to perform on-off control under the action of generating a first pulse signal and a second pulse signal according to the level of a control signal; the switch unit is connected to the pulse generator, and the switch unit is configured to conduct and cut off in response to the first pulse signal and the second pulse signal; the conduction identification unit is connected to the switch unit, and the conduction identification unit is configured to output a first identification signal and a second identification signal according to the conduction state of the switch unit; the common-mode processing unit is connected to the conduction identification unit, and the common-mode processing unit is configured to process the common-mode interference signals of the first identification signal and the second identification signal; the trigger unit is connected to the common-mode processing unit, and the trigger unit generates an output signal according to the first identification signal and the second identification signal processed by the common-mode processing unit; wherein, the common-mode processing unit includes a latch sub-unit, the latch sub-unit includes a first latch and a second latch, an input end of the first latch is connected to a first identification signal terminal of the conduction identification unit, an enable end of the first latch is connected to a second identification signal terminal of the conduction identification unit, an output end of the first latch is connected to the trigger unit, an input end of the second latch is connected to the second identification signal terminal of the conduction identification unit, an enable end of the second latch is connected to the first identification signal terminal of the conduction identification unit, and an output end of the second latch is connected to the trigger unit.

[0006] In some embodiments, the switch unit includes a first load, a first switching transistor, a second load, and a second switching transistor; wherein, a gate of the first switching transistor is connected to a first pulse signal terminal of the pulse generator, a first pole of the first switching transistor is connected to a first end of the first load, a second pole of the first switching transistor is connected to a second power supply, a gate of the second switching transistor is connected to a second pulse signal terminal of the pulse generator, a first pole of the second switching transistor is connected to a first end of the second load, a second pole of the second switching transistor is connected to the second power supply; a second end of the first load is connected to a first power supply, and a second end of the second load is connected to the first power supply.

[0007] In some embodiments, the conduction identification unit includes a first identification sub-unit and a second identification sub-unit, the first identification sub-unit is connected to the first pole of the first switching transistor and the first end of the first load, and the first identification sub-unit is configured to output the first identification signal according to the conduction state of the first switching transistor, the second identification sub-unit is connected to the first pole of the second switching transistor and the first end of the second load, and the second identification sub-unit outputs the second identification signal according to the conduction state of the second switching transistor.

[0008] In some embodiments, the first identification subunit includes a first P-type transistor and a first N-type transistor. The gates of the first P-type transistor and the first N-type transistor are connected to the first pole of the first switching transistor and the first end of the first load. The first pole of the first P-type transistor is connected to a third power supply. The second pole of the first P-type transistor is connected to the first identification signal terminal of the conduction identification unit. The first pole of the first N-type transistor is connected to the first identification signal terminal of the conduction identification unit. The second pole of the first N-type transistor is connected to a fourth power supply.

[0009] In some embodiments, the second identification subunit includes a second P-type transistor and a second N-type transistor. The gates of the second P-type transistor and the second N-type transistor are connected to the first pole of the second switching transistor and the first end of the second load. The first pole of the second P-type transistor is connected to a third power supply. The second pole of the second P-type transistor is connected to the second identification signal terminal of the conduction identification unit. The first pole of the second N-type transistor is connected to the second identification signal terminal of the conduction identification unit. The second pole of the second N-type transistor is connected to a fourth power supply.

[0010] In some embodiments, the trigger unit includes an RS flip-flop. The reset terminal of the RS flip-flop is used to receive the first identification signal. The set terminal of the RS flip-flop is used to receive the second identification signal. The output terminal of the RS flip-flop generates the output signal.

[0011] In some embodiments, the level conversion circuit includes a filtering subunit. The filtering subunit is connected to the common-mode processing unit and the trigger unit. The filtering subunit is used to perform filtering processing on the first identification signal and the second identification signal.

[0012] In some embodiments, the filtering subunit includes a first filtering subunit and a second filtering subunit. The output terminal of the first latch is connected to the reset terminal of the RS flip-flop through the first filtering subunit. The output terminal of the second latch is connected to the set terminal of the RS flip-flop through the second filtering subunit.

[0013] In some embodiments, the first filtering subunit includes a first resistor and a first capacitor. The first resistor is connected to the output terminal of the first latch and the reset terminal of the RS flip-flop. The first capacitor is connected to the reset terminal of the RS flip-flop and the ground. The second filtering subunit includes a second resistor and a second capacitor. The second resistor is connected to the output terminal of the second latch and the set terminal of the RS flip-flop. The second capacitor is connected to the set terminal of the RS flip-flop and the ground.

[0014] The embodiment of the present application also provides a driving circuit. The driving circuit includes a power transistor and the level conversion circuit described in any of the above embodiments; the gate of the power transistor is connected to the output signal terminal of the triggering unit.

[0015] By adding a common-mode processing unit to the level conversion circuit and the driving circuit of the present application, the common-mode interference signal will not be transmitted to the next stage, effectively suppressing the influence of common-mode interference on the circuit.

[0016] Some additional aspects and advantages of the present application will be given in the following description, some will become apparent from the following description, or will be understood through the practice of the present application. Description of the Drawings

[0017] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0018] Figure 1 is a schematic diagram of a conventional topology for driving high-voltage devices using a floating well;

[0019] Figure 2 is a signal schematic diagram of current common-mode interference generation;

[0020] Figure 3 is a schematic diagram of a driving waveform generated by currently driving high-voltage devices using a floating well;

[0021] Figure 4 is a schematic diagram of the level conversion circuit of some embodiments of the present application;

[0022] Figure 5 is a schematic diagram of the structure of the first identification subunit or the second identification subunit in the conduction identification unit of the level conversion circuit of some embodiments of the present application;

[0023] Figure 6 is a schematic diagram of the driving circuit of some embodiments of the present application. Detailed Embodiments

[0024] The following describes in detail the embodiments of the present application. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0025] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0026] In the description of the present application, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, an electrical connection, or a connection that allows mutual communication; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0027] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0028] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0029] The working principle of the gate-level drive chip is to convert a low-voltage logic control signal into a high-voltage logic control signal to control the power transistor. During the conversion from a low-voltage logic signal to a high-voltage logic signal, it is required that its power be as low as possible. On the one hand, low power represents high conversion efficiency. On the other hand, this high-voltage conversion is generally a conversion between a low voltage and a floating well, and the power supply of the floating well generally adopts a bootstrap generation method. Bootstrap means generating the power supply by itself without an external power supply. This bootstrap generation method solves the problem of continuously refreshing and storing limited charges.

[0030] The traditional topology for driving high-voltage devices using the floating well method is as Figure 1As shown. The circuit within the dashed box is the floating well circuit. VB is the power supply of the floating well, and VS is the ground of the floating well. GND is the ground of the low-voltage part. The overall circuit includes: a pulse generator for generating pulses at the rising and falling edges of the input signal HIN, which emits SET and RST signals, as Figure 2 shown. The SET port drives a high-voltage device HVMOS for the low-voltage region and the floating well to conduct. This signal passes through a resistor connected to the high-voltage well power supply (of course, it can also be other loads, such as a current source, etc.). The HVMOS conduction recognition unit determines whether the HVMOS is conducting by the difference in the voltage or current at its access terminal caused by the conduction or non-conduction of the HVMOS, and filters this signal and transmits it to the RS flip-flop. When the HVMOS at the SET end conducts, the set terminal of the RS flip-flop is valid, and the RS flip-flop outputs a valid potential, causing the HO port to output a valid potential; when the HVMOS at the RST end conducts, the reset terminal of the RS flip-flop is valid, and the RS flip-flop turns off the valid potential, causing the HO port to output off. In this way, through the short-term conduction of the HVMOS, the input signal of HIN can be accurately transmitted to the high-voltage output HO. The advantage of this approach is power consumption savings. Waveform examples are as Figure 3 shown.

[0031] When the HO port outputs a high level and turns on the peripheral power transistor, the VS voltage will be raised to several hundred volts (such as 400V). At this time, VB will also be raised to a relatively high voltage (such as 415V) due to the capacitance between VB and VS. At this time, the drain terminals of the two HVMOSs are raised to a relatively high voltage. The drain terminals of the HVMOSs are raised from the initial relatively low voltage (3V or 15V) to a relatively high voltage (such as 403V or 415V). At this time, because there is a parasitic capacitance Cds between the drain terminal of the HVMOS and the ground, the device connected to the drain terminal of the HVMOS needs to charge the drain terminal of the HVMOS. When the charging speed cannot make up for the rising speed of VB, an abnormally low level will appear at the drain terminal of the HVMOS corresponding to RST, which is called common-mode interference. As Figure 2 shown. Among them, the SET_HVD to VS signal is the voltage of the drain terminal of the HVMOS corresponding to SET minus the ground signal VS within the floating well. Similarly, RST_HVDto VS is the waveform corresponding to RST.

[0032] In view of this, please refer to Figure 4 , this application provides a level conversion circuit 100. The level conversion circuit 100 includes a pulse generator 110, a switch unit 120, a conduction recognition unit 130, a common-mode processing unit 140, and a trigger unit 150.

[0033] The pulse generator 110 is used to generate a first pulse signal and a second pulse signal according to the level of a control signal. The control signal is a low-voltage logic control signal. This control signal is the low-voltage logic control signal HIN, the first pulse signal is the SET signal, and the second pulse signal is the RST signal.

[0034] The switch unit 120 is connected to the pulse generator 110. The switch unit 120 is used to implement on-off control under the action of the first pulse signal and the second pulse signal. Among them, the switch unit 120 includes a first switch transistor SET and a second switch transistor RST.

[0035] The conduction recognition unit 130 is connected to the switch unit 120. The conduction recognition unit 130 is used to output a first recognition signal A1 and a second recognition signal A2 according to the conduction state of the switch unit 120. The conduction recognition unit 130 can be, for example, an HVMOS conduction recognition unit.

[0036] The common-mode processing unit 140 is connected to the conduction recognition unit 130. The common-mode processing unit 140 is used to process the common-mode interference signals of the first recognition signal A1 and the second recognition signal A2.

[0037] The common-mode processing unit 140 includes a latch sub-unit 141. The latch sub-unit 141 includes a first latch 1411 and a second latch 1412. The input end of the first latch 1411 is connected to the first recognition signal terminal 131 of the conduction recognition unit 130. The enable end of the first latch 1411 is connected to the second recognition signal terminal 132 of the conduction recognition unit 130. The output end of the first latch 1411 is connected to the trigger unit 150. The input end of the second latch 1412 is connected to the second recognition signal terminal 132 of the conduction recognition unit 130. The enable end of the second latch 1412 is connected to the first recognition signal terminal 131 of the conduction recognition unit 130. The output end of the second latch 1412 is connected to the trigger unit 150.

[0038] The trigger unit 150 is connected to the common-mode processing unit 140. The trigger unit 150 generates an output signal according to the first recognition signal A1 and the second recognition signal A2 processed by the common-mode processing unit 140.

[0039] It can be understood that the working principle of the common-mode processing unit 140 of the level conversion circuit 100 in this application is that when the effective signal of the first switch transistor SET is transmitted, the signal on the RST transmission line is latched by means of a latch; when the effective signal of the second switch transistor RST is transmitted, the signal on the SET transmission line is latched by means of a latch. In this way, even if common-mode interference occurs, the common-mode interference signal will not be transmitted to the next stage. Among them, latching means temporarily storing the signal to maintain a certain level state.

[0040] Among them, the latch of the present application has the following characteristics: The A1 signal of the SET transmission line is the input A1 of the latch of the SET transmission line, and at the same time is the latch enable signal CLK2 of the latch of the RST transmission line; The A2 signal of the RST transmission line is the input A2 of the latch of the RST transmission line, and at the same time is the latch enable signal CLK1 of the latch of the SET transmission line. Assuming that A1 representing SET validity is at a high level, then the CLK of the second latch 1412 is also at a high level, and at this time the output Y of the second latch 2 is maintained; When A1 is at a low level, the CLK of the second latch 1412 is also at a low level, and at this time the output Y2 of the latch 1412 = A2.

[0041] Thus, the level conversion circuit 100 of the present application adds a common mode processing unit 140. Through the function of the latch in the common mode processing unit 140, the common mode interference signal can be prevented from being transmitted to the next stage, effectively suppressing the influence of the common mode interference on the level conversion circuit.

[0042] More specifically, please refer to Figure 4 , the switching unit 120 includes a first load R1, a first switching transistor SET, a second load R2, and a second switching transistor RST. Among them, the gate of the first switching transistor SET is connected to the first pulse signal terminal 111 of the pulse generator 110, the first pole of the first switching transistor SET is connected to the first end of the first load R1, the second pole of the first switching transistor SET is connected to the second power supply GND, the gate of the second switching transistor RST is connected to the second pulse signal terminal of the pulse generator 110, the first pole of the second switching transistor RST is connected to the first end of the second load R2, and the second pole of the second switching transistor RST is connected to the second power supply GND. The second end of the first load R1 is connected to the first power supply VB, and the second end of the second load is connected to the first power supply VB.

[0043] The conduction identification unit 130 includes a first identification subunit 1311 and a second identification subunit 1312. The first identification subunit 1311 is connected to the first pole of the first switching transistor SET and the first pole of the first load R1. The first identification subunit 1311 is used to output a first identification signal A1 according to the conduction state of the first switching transistor SET. The second identification subunit 1312 is connected to the first pole of the second switching transistor RST and the first pole of the second load R2, and the second identification subunit 1312 outputs a second identification signal A2 according to the conduction state of the second switching transistor RST.

[0044] Please combine with Figure 5, the first identification subunit 1311 includes a first P-type transistor MP1 and a first N-type transistor MN1. The gates of the first P-type transistor and the first N-type transistor are connected to the first pole of the first switching transistor SET and the first pole of the first load R1. The first pole of the first P-type transistor MP1 is connected to the third power supply VB1, the second pole of the first P-type transistor MP1 is connected to the first identification signal terminal 131 of the conduction identification unit 130, the first pole of the first N-type transistor MN1 is connected to the first identification signal terminal 131 of the conduction identification unit 130, and the second pole of the first N-type transistor MN1 is connected to the fourth power supply VB2.

[0045] Similarly, the second identification subunit 1312 also includes a second P-type transistor MP2 and a second N-type transistor MN2. The gates of the second P-type transistor MP2 and the second N-type transistor MN2 are connected to the first pole of the second switching transistor RST and the first pole of the second load R2. The first pole of the second P-type transistor MP2 is connected to the third power supply VB1, the second pole of the second P-type transistor MN2 is connected to the second identification signal terminal 132 of the conduction identification unit 130, the first pole of the second N-type transistor MN2 is connected to the second identification signal terminal 132 of the conduction identification unit 130, and the second pole of the second N-type transistor MN2 is connected to the fourth power supply VB2.

[0046] The trigger unit 150 includes an RS flip-flop. The reset terminal of the RS flip-flop is used to receive the first identification signal A1, the set terminal of the RS flip-flop is used to receive the second identification signal A2, and the output terminal of the RS flip-flop generates an output signal. It can be understood that when common-mode interference occurs, the incorrect valid signal that appears on the RST transmission line enters the RS flip-flop, and this common-mode interference transmission can be weakened through RC filtering.

[0047] In addition, please refer to again Figure 4 , the common-mode processing unit 140 further includes a filtering subunit 142. The filtering subunit 142 is connected to the latch subunit 141 and the trigger unit 150. The filtering subunit 142 is used to perform filtering processing on the first identification signal A1 and the second identification signal A2. It can be understood that the first identification signal A1 and the second identification signal A2 processed by the filtering subunit 142 at this time are identification signals without common-mode interference signals after being processed by the latch for common-mode.

[0048] The filtering subunit 142 includes a first filtering subunit 1421 and a second filtering subunit 1422. The output terminal of the first latch 1411 is connected to the reset terminal of the RS flip-flop through the first filtering subunit, and the output terminal of the second latch 1412 is connected to the set terminal of the RS flip-flop through the second filtering subunit 1422. It can be understood that when common-mode interference occurs, an incorrect valid signal will appear on the RST transmission line and enter the RS flip-flop, and this common-mode interference transmission can be weakened through RC filtering.

[0049] More specifically, the first filtering subunit 1421 includes a first resistor R3 and a first capacitor C1. The first resistor R3 is connected to the output terminal of the first latch 1411 and the reset terminal of the RS flip-flop, and the first capacitor C1 is connected to the reset terminal of the RS flip-flop and the ground.

[0050] The second filtering subunit 1422 includes a second resistor R4 and a second capacitor C2. The second resistor R4 is connected to the output terminal of the second latch 1412 and the set terminal of the RS flip-flop, and the second capacitor C2 is connected to the set terminal of the RS flip-flop and the ground.

[0051] Please refer to Figure 6 , this application also provides a driving circuit 1000. The driving circuit 1000 includes the level conversion circuit 100 and the power transistor 200 described in the above embodiments. The gate PMG of the power transistor 200 is connected to the output signal terminal of the trigger unit 150. Among them, the structure of the level conversion circuit 100 is as described above and will not be elaborated here.

[0052] The structure of the power transistor 200 is as Figure 6 shown. The voltages at the PMD terminal and the PMS terminal may be below 0V or may reach the breakdown voltage of the high-power transistor, such as 600V or 1200V. The switching function of the power transistor 200 is achieved by controlling the voltage difference between its gate PMG and source PMS. Among them, as Figure 6 shown, the voltage VPMG output by the level conversion circuit 100 controls the voltage of the gate PMG, and the voltage VPMS output by the level conversion circuit 100 controls the voltage of the source PMS. When the voltage VPMG - VPMS output by the level conversion circuit 100 is equal to 0V, the power transistor is turned off; when the voltage VPMG - VPMS output by the level conversion circuit 100 is equal to 15V, the power transistor 200 is turned on.

[0053] The driving circuit 1000 has the following characteristics: The VS voltage can float within a relatively large range, such as 0 - 600V, where VS is the source voltage, but the VGS voltage is within a relatively small range, such as 0 - 20V, and VGS is the voltage of the gate relative to the source. The driving circuit 1000 converts a low-voltage logic signal into a logic signal with a floating voltage up to a high voltage to control the on and off of the peripheral high-voltage power transistor.

[0054] The level conversion circuit 100 in the driving circuit 1000 of this application newly adds a common-mode processing unit 140. Through the function of the latch in the common-mode processing unit 140, the common-mode interference signal can be prevented from being transmitted to the next stage, effectively suppressing the influence of common-mode interference on the driving circuit.

[0055] The above embodiments only illustrate several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A level conversion circuit, characterized in that, comprising: a pulse generator for generating a first pulse signal and a second pulse signal according to the level of a control signal; a switch unit, the switch unit being connected to the pulse generator, the switch unit being used for on-off control under the action of the first pulse signal and the second pulse signal; a conduction identification unit, the conduction identification unit being connected to the switch unit, the conduction identification unit being used for outputting a first identification signal and a second identification signal according to the conduction state of the switch unit; a common-mode processing unit, the common-mode processing unit being connected to the conduction identification unit, the common-mode processing unit being used for processing the common-mode interference signals of the first identification signal and the second identification signal; a trigger unit, the trigger unit being connected to the common-mode processing unit, the trigger unit generating an output signal according to the first identification signal and the second identification signal processed by the common-mode processing unit; wherein, the common-mode processing unit includes a latch sub-unit, the latch sub-unit includes a first latch and a second latch, the input end of the first latch is connected to the first identification signal end of the conduction identification unit, the enable end of the first latch is connected to the second identification signal end of the conduction identification unit, the output end of the first latch is connected to the trigger unit, the input end of the second latch is connected to the second identification signal end of the conduction identification unit, the enable end of the second latch is connected to the first identification signal end of the conduction identification unit, and the output end of the second latch is connected to the trigger unit; the first latch is used for latching the signal at the first identification signal end according to the second identification signal and transmitting it to the trigger unit; the second latch is used for latching the signal at the second identification signal end according to the first identification signal and transmitting it to the trigger unit.

2. The level conversion circuit according to claim 1, characterized in that, the switch unit includes a first load, a first switching transistor, a second load and a second switching transistor; wherein, the gate of the first switching transistor is connected to the first pulse signal end of the pulse generator, the first pole of the first switching transistor is connected to the first end of the first load, the second pole of the first switching transistor is connected to a second power supply, the gate of the second switching transistor is connected to the second pulse signal end of the pulse generator, the first pole of the second switching transistor is connected to the first end of the second load, and the second pole of the second switching transistor is connected to the second power supply; the second end of the first load is connected to a first power supply, and the second end of the second load is connected to the first power supply.

3. The level conversion circuit according to claim 2, characterized in that, The conduction recognition unit includes a first recognition subunit and a second recognition subunit. The first recognition subunit is connected to the first pole of the first switching transistor and the first end of the first load. The first recognition subunit is configured to output the first recognition signal according to the conduction state of the first switching transistor. The second recognition subunit is connected to the first pole of the second switching transistor and the first end of the second load. The second recognition subunit outputs the second recognition signal according to the conduction state of the second switching transistor.

4. The level conversion circuit according to claim 3, wherein, the first recognition subunit includes a first P-type transistor and a first N-type transistor. The gates of the first P-type transistor and the first N-type transistor are connected to the first pole of the first switching transistor and the first end of the first load. The first pole of the first P-type transistor is connected to a third power supply. The second pole of the first P-type transistor is connected to the first recognition signal terminal of the conduction recognition unit. The first pole of the first N-type transistor is connected to the first recognition signal terminal of the conduction recognition unit. The second pole of the first N-type transistor is connected to a fourth power supply.

5. The level conversion circuit according to claim 3, wherein, the second recognition subunit includes a second P-type transistor and a second N-type transistor. The gates of the second P-type transistor and the second N-type transistor are connected to the first pole of the second switching transistor and the first end of the second load. The first pole of the second P-type transistor is connected to a third power supply. The second pole of the second P-type transistor is connected to the second recognition signal terminal of the conduction recognition unit. The first pole of the second N-type transistor is connected to the second recognition signal terminal of the conduction recognition unit. The second pole of the second N-type transistor is connected to a fourth power supply.

6. The level conversion circuit according to claim 1, wherein, the trigger unit includes an RS flip-flop. The reset terminal of the RS flip-flop is configured to receive the first recognition signal. The set terminal of the RS flip-flop is configured to receive the second recognition signal. The output terminal of the RS flip-flop generates the output signal.

7. The level conversion circuit according to claim 6, wherein, the common-mode processing unit includes a filtering subunit. The filtering subunit is connected to the latch subunit and the trigger unit. The filtering subunit is configured to perform filtering processing on the first recognition signal and the second recognition signal.

8. The level conversion circuit according to claim 7, wherein, the filtering subunit includes a first filtering subunit and a second filtering subunit. The output terminal of the first latch is connected to the reset terminal of the RS flip-flop through the first filtering subunit. The output terminal of the second latch is connected to the set terminal of the RS flip-flop through the second filtering subunit.

9. The level conversion circuit according to claim 8, wherein, The first filtering subunit includes a first resistor and a first capacitor. The first resistor is connected to the output terminal of the first latch and the reset terminal of the RS flip-flop, and the first capacitor is connected to the reset terminal of the RS flip-flop and the ground; The second filtering subunit includes a second resistor and a second capacitor. The second resistor is connected to the output terminal of the second latch and the set terminal of the RS flip-flop, and the second capacitor is connected to the set terminal of the RS flip-flop and the ground.

10. A driving circuit, characterized in that, it includes: the level conversion circuit according to any one of claims 1-9; a power transistor, the gate of the power transistor is connected to the output signal terminal of the trigger unit.

Images