Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and formation method, comprising: providing a substrate; forming a vertical transistor on the substrate; forming a first sacrificial layer and a first supporting layer on the vertical transistor; forming a first pillar layer and a first electrode layer located on a surface of the first pillar layer within the first sacrificial layer and the first supporting layer, wherein the first electrode layer is electrically connected to the vertical transistor; removing a portion of the first supporting layer; forming a second sacrificial layer and a second supporting layer on the first pillar layer and the first sacrificial layer; forming a second pillar layer and a second electrode layer located on a surface of the second pillar layer within the second sacrificial layer and the second supporting layer, wherein the second electrode layer is electrically connected to the first electrode layer; removing a portion of the second supporting layer; forming an opening between the first pillar layer, the second pillar layer, the first supporting layer, and the second supporting layer, exposing the surfaces of the first and second electrode layers; forming a dielectric layer on the surfaces of the first and second electrode layers; and forming a third electrode layer on the surface of the dielectric layer. The method has low process difficulty.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the rapid development of technology today, semiconductor memories are widely used in electronic devices.

[0003] Dynamic random access memory (DRAM) is a type of volatile memory and is the most commonly used solution for storing large amounts of data. Typically, DRAM consists of multiple memory cells, each of which is primarily composed of a transistor and a capacitor controlled by the transistor. Each cell is electrically connected to the other via word lines and bit lines.

[0004] However, there are still many problems in the existing dynamic random access memory formation process. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the formation process of dynamic random access memory.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a vertical transistor on the substrate; forming a first sacrificial layer and a first supporting layer located on the first sacrificial layer on the vertical transistor; forming a first pillar layer and a first electrode layer located on the surface of the first pillar layer within the first sacrificial layer and the first supporting layer, wherein the first electrode layer is electrically connected to the vertical transistor; after forming the first pillar layer and the first electrode layer, removing a portion of the first supporting layer; after removing a portion of the first supporting layer, forming a second sacrificial layer and a second supporting layer located on the second sacrificial layer on the first pillar layer and the first sacrificial layer; A second pillar layer and a second electrode layer located on the surface of the second pillar layer are formed in the second sacrificial layer and the second supporting layer, and the second electrode layer is electrically connected to the first electrode layer; after the second pillar layer and the second electrode layer are formed, part of the second supporting layer is removed; after removing part of the second supporting layer, the first sacrificial layer and the second sacrificial layer are removed, and openings are formed between the first pillar layer, the second pillar layer, the first supporting layer and the second supporting layer, and the openings expose the surfaces of the first electrode layer and the second electrode layer; a dielectric layer is formed on the surfaces of the first electrode layer, the second electrode layer, the first supporting layer and the second supporting layer; and a third electrode layer is formed on the surface of the dielectric layer.

[0007] Optionally, the vertical transistor includes: a channel column; a gate structure located on the sidewall surface of one side of the channel column; a first source and drain doping region located in the channel column, and the surface of one end of the channel column exposes the surface of the first source and drain doping region; a second source and drain doping region located in the channel column, and the surface of the other end of the channel column exposes the surface of the second source and drain doping region.

[0008] Optionally, it also includes: forming an isolation structure on the side wall of the channel column, wherein the channel column and the gate structure are located within the isolation structure; before forming a first sacrificial layer and a first supporting layer located on the first sacrificial layer on the vertical transistor, it also includes: forming an insulating layer on the isolation structure, wherein the first sacrificial layer is located on the insulating layer; forming a second highly doped layer located within the insulating layer, wherein the second highly doped layer is in contact with the second source and drain doping region.

[0009] Optionally, the method for forming the second highly doped layer includes: forming a third groove in the first sacrificial layer and the first supporting layer; forming a fifth groove in the insulating layer at the bottom of the third groove, the fifth groove exposing the surface of the second source and drain doping region; forming an initial second highly doped layer in the fifth groove and the third groove; etching back the initial second highly doped layer to form a second highly doped layer in the fifth groove.

[0010] Optionally, the method for forming the first pillar layer and the first electrode layer includes: forming an initial first electrode layer on the side wall surface of the third groove, the surface of the second highly doped layer and the surface of the first support layer; forming an initial first pillar layer on the surface of the initial first electrode layer, and the initial first pillar layer fills the third groove; removing the initial first pillar layer and the initial first electrode layer on the surface of the first support layer until the surface of the first support layer is exposed, forming the first pillar layer and the first electrode layer located on the surface of the first pillar layer, and the first electrode layer is electrically connected to the second highly doped layer.

[0011] Optionally, the method further includes: forming a metal silicide layer between the second highly doped layer and the first electrode layer.

[0012] Optionally, the method for forming the metal silicide layer includes: forming a metal layer on the surface of the second highly doped layer; annealing the metal layer to form a metal silicide layer on the surface of the second highly doped layer; and after forming the metal silicide layer, removing the remaining metal layer.

[0013] Optionally, a top surface of the second highly doped layer is lower than a surface of the insulating layer, and the first electrode layer is further located in the fifth groove.

[0014] Optionally, the method further includes: forming a first highly doped layer located on a surface of one end of the channel pillar, wherein the first highly doped layer is in contact with the first source and drain doped region.

[0015] Optionally, the method for forming the second pillar layer and the second electrode layer includes: forming a fourth groove in the second supporting layer and the second sacrificial layer, the fourth groove exposing the surface of the first electrode layer; forming a second electrode layer on the side wall surface and the bottom surface of the fourth groove, the second electrode layer is electrically connected to the first electrode layer; forming a second pillar layer in the fourth groove, the second pillar layer is located on the surface of the second electrode layer.

[0016] Optionally, the material of the first sacrificial layer includes silicon oxide, phosphorus- and boron-doped silicon oxide, or phosphorus-doped silicon oxide; the material of the second sacrificial layer includes silicon oxide, phosphorus- and boron-doped silicon oxide, or phosphorus-doped silicon oxide.

[0017] Optionally, the process of removing the first sacrificial layer and the second sacrificial layer includes a wet etching process.

[0018] Optionally, the material of the first supporting layer is different from the material of the first sacrificial layer, and the material of the second supporting layer is different from the material of the second sacrificial layer; the material of the first supporting layer includes silicon nitride, carbon-doped silicon nitride or boron-doped silicon nitride; the material of the second supporting layer includes silicon nitride, carbon-doped silicon nitride or boron-doped silicon nitride.

[0019] Optionally, the process of removing a portion of the second supporting layer and removing a portion of the first supporting layer includes a dry etching process.

[0020] Optionally, the material of the first pillar layer includes polysilicon or metal, and the metal includes titanium nitride; the material of the second pillar layer includes polysilicon or metal, and the metal includes titanium nitride.

[0021] Optionally, it further includes: forming a third pillar layer on the surface of the third electrode layer, wherein the third pillar layer fills the opening; the material of the third pillar layer includes polysilicon or metal, and the metal includes titanium nitride.

[0022] Optionally, the projection range of the first groove on the substrate at least partially overlaps with the projection range of the second groove on the substrate, or the projection range of the first groove on the substrate does not overlap with the projection range of the second groove on the substrate.

[0023] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate; a vertical transistor located on the substrate; a first pillar layer located on the vertical transistor and a second pillar layer located on the first pillar layer; a first supporting layer located between the first pillar layers, the top surface of the first supporting layer being flush with the top surface of the first pillar layer; a first groove located within the first supporting layer; a second supporting layer located between the second pillar layers, the top surface of the second supporting layer being flush with the top surface of the second pillar layer; a second groove located within the second supporting layer; a first electrode layer located on the side wall surface and bottom surface of the first pillar layer; a second electrode layer located on the side wall surface and bottom surface of the second pillar layer; an opening located between the first pillar layer, the second pillar layer, the first supporting layer and the second supporting layer, the opening exposing the surfaces of the first electrode layer and the second electrode layer, the first groove and the second groove being connected with the opening; a dielectric layer located on the surface of the first electrode layer, the surface of the second electrode layer, the surface of the first supporting layer and the surface of the second supporting layer; a third electrode layer located on the surface of the dielectric layer.

[0024] Optionally, the vertical transistor includes: a channel column; a gate structure located on the sidewall surface of one side of the channel column; a first source and drain doping region located in the channel column, and the surface of one end of the channel column exposes the surface of the first source and drain doping region; a second source and drain doping region located in the channel column, and the surface of the other end of the channel column exposes the surface of the second source and drain doping region.

[0025] Optionally, it further includes: a first highly doped layer located on a surface of one end of the channel pillar, wherein the first highly doped layer is in contact with the first source and drain doped region.

[0026] Optionally, it also includes: an isolation structure located on the side wall of the channel column, the channel column and the gate structure are located within the isolation structure; an insulating layer located on the isolation structure; a second highly doped layer located within the insulating layer, the second highly doped layer is in contact with the second source and drain doping region; the first pillar layer is located on the second highly doped layer, and the first electrode layer is electrically connected to the second highly doped layer.

[0027] Optionally, the method further includes: a metal silicide layer located between the second highly doped layer and the first electrode layer.

[0028] Optionally, a top surface of the second highly doped layer is lower than a surface of the insulating layer.

[0029] Optionally, the material of the insulating layer includes silicon nitride or carbon-doped silicon nitride.

[0030] Optionally, the material of the first pillar layer includes polysilicon or metal, and the metal includes titanium nitride; the material of the second pillar layer includes polysilicon or metal, and the metal includes titanium nitride.

[0031] Optionally, it further includes: a third pillar layer located on the surface of the third electrode layer, the third pillar layer filling the opening; the material of the third pillar layer includes polysilicon or metal, and the metal includes titanium nitride.

[0032] Optionally, the dielectric layer material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0033] Optionally, the projection range of the first groove on the substrate at least partially overlaps with the projection range of the second groove on the substrate, or the projection range of the first groove on the substrate does not overlap with the projection range of the second groove on the substrate.

[0034] Optionally, the material of the first supporting layer includes silicon nitride, carbon-doped silicon nitride or boron-doped silicon nitride; the material of the second supporting layer includes silicon nitride, carbon-doped silicon nitride or boron-doped silicon nitride.

[0035] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0036] The formation method of the technical solution of the present invention first forms a first sacrificial layer and a first supporting layer, and a third groove located within the first sacrificial layer and the first supporting layer, then forms a first electrode layer within the third groove, then forms a second sacrificial layer and a second supporting layer, and a fourth groove located within the second sacrificial layer and the second supporting layer, and then forms a second electrode layer within the fourth groove. The third groove has a small depth-to-width ratio, and the fourth groove has a small depth-to-width ratio, which reduces the process difficulty of forming the third and fourth grooves and improves production efficiency.

[0037] Furthermore, the projection of the first groove on the substrate at least partially overlaps with the projection of the second groove on the substrate, or the projection of the first groove on the substrate does not overlap with the projection of the second groove on the substrate. Portions of the first supporting layer and the second supporting layer can be removed in different steps, and the portions of the first supporting layer and the second supporting layer to be removed can be arbitrarily selected, thereby increasing process flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figures 1 to 4 is a structural schematic diagram of a semiconductor structure forming process in one embodiment;

[0039] Figures 5 to 14 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] As described in the background art, the existing process of forming a dynamic random access memory still has many problems, which will now be analyzed and explained in conjunction with specific embodiments.

[0041] Figures 1 to 4 1 is a schematic structural diagram of a semiconductor structure forming process in one embodiment.

[0042] Please refer to Figure 1 , providing a substrate 100; forming a vertical transistor on the substrate 100, the vertical transistor comprising: a channel pillar 101; a gate structure 102 located on a sidewall surface of the channel pillar 101; a first source-drain doped region 121 located in the channel pillar 101, wherein one end surface of the channel pillar 101 exposes the surface of the first source-drain doped region 121; a second source-drain doped region 122 located in the channel pillar 101, wherein the other end surface of the channel pillar 101 exposes the surface of the second source-drain doped region 122; forming an isolation structure 120 on the sidewall of the channel pillar 101, The channel pillar 101 and the gate structure 102 are located in the isolation structure 120; an insulating layer 105 is formed on the isolation structure 120; a first sacrificial layer 106 and a first supporting layer 107 located on the first sacrificial layer 106 are formed on the insulating layer 105; a second sacrificial layer 108 and a second supporting layer 109 located on the second sacrificial layer 108 are formed on the first supporting layer 107; a first highly doped layer 103 is formed in the substrate 100, and the first highly doped layer 103 is located at one end of the channel pillar 101 and is in contact with the first source and drain doping region 121.

[0043] Please refer to Figure 2 A groove (not shown) is formed in the second supporting layer 109, the second sacrificial layer 108, the first supporting layer 107, the first sacrificial layer 106 and the insulating layer 105; a second highly doped layer 104 is formed in the groove, the second highly doped layer 104 is located in the insulating layer 105, and the second highly doped layer 104 is in contact with the second source-drain doping region 122; a metal silicide layer is formed on the surface of the second highly doped layer 104; a first electrode layer 111 is formed on the sidewall surface of the groove and the surface of the metal silicide layer; a first pillar layer 112 is formed in the groove, and the first pillar layer 112 is located in the groove.

[0044] Please refer to Figure 3 , remove part of the second supporting layer 109, and after removing part of the second supporting layer 109, wet-remove the second sacrificial layer 108, remove part of the first supporting layer 107, and after removing part of the first supporting layer 107, wet-remove the first sacrificial layer 106 to form an opening 113 between the second supporting layer 109 and the first supporting layer 107, and between the first electrode layer 111.

[0045] Please refer to Figure 4A dielectric layer 116 is formed on the surface of the second supporting layer 109 , the surface of the first supporting layer 107 and the surface of the first electrode layer 111 ; a second electrode layer 117 is formed on the surface of the dielectric layer 116 ; a second pillar layer 118 is formed on the surface of the second electrode layer 117 , and the second pillar layer 118 fills the opening 113 .

[0046] During the formation of the semiconductor structure, the first electrode layer 111, the dielectric layer 116, and the second electrode layer 117 constitute a capacitor structure, and the first support layer 107 and the second support layer 109 are used to support the capacitor structure. When forming the groove, it is necessary to etch the second support layer 109, the second sacrificial layer 108, the first support layer 107, the first sacrificial layer 106, and the insulating layer 105. This results in a larger depth-to-width ratio for the groove, a higher process difficulty during etching, and difficulty controlling the etching process, resulting in a poor groove morphology, which affects the performance of the semiconductor structure.

[0047] To address the above-mentioned issues, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure. The method comprises first forming a first sacrificial layer and a first supporting layer, and a third groove within the first sacrificial layer and the first supporting layer, forming a first electrode layer within the third groove, and then forming a second sacrificial layer and a second supporting layer, and a fourth groove within the second sacrificial layer and the second supporting layer, and forming a second electrode layer within the fourth groove. The third groove and the fourth groove have a small depth-to-width ratio, which reduces the process difficulty of forming the third and fourth grooves and improves production efficiency. Furthermore, portions of the first and second supporting layers can be removed at different steps, and the portions of the first and second supporting layers that are removed can be arbitrarily selected, providing greater process flexibility.

[0048] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] Figures 5 to 14 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0050] Please refer to Figure 5 , providing a substrate 200.

[0051] In this embodiment, the substrate 200 is made of silicon.

[0052] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0053] Please continue to refer to Figure 5 , a vertical transistor is formed on the substrate 200.

[0054] The vertical transistor includes: a channel column 201; a gate structure 202 located on the side wall surface of one side of the channel column 201; a first source-drain doped region 241 located in the channel column 201, and the surface of one end of the channel column 201 exposes the surface of the first source-drain doped region 241; a second source-drain doped region 242 located in the channel column 201, and the surface of the other end of the channel column 201 exposes the surface of the second source-drain doped region 242.

[0055] There are doping ions in the first source / drain doping region 241 and the second source / drain doping region 242 , and the doping ions include N-type ions or P-type ions.

[0056] Please continue to refer to Figure 5 An isolation structure 230 is formed on the sidewall of the channel pillar 201 , and the channel pillar 201 and the gate structure 202 are located in the isolation structure 230 ; an insulating layer 204 is formed on the isolation structure 230 .

[0057] In this embodiment, the material of the insulating layer 204 includes silicon nitride or carbon-doped silicon nitride.

[0058] Please continue to refer to Figure 5 , a first highly doped layer 203 is formed in the substrate 200 , wherein the first highly doped layer 203 is located at one end of the channel pillar 201 and contacts the first source-drain doped region 241 .

[0059] In this embodiment, the material of the first highly doped layer 203 includes polycrystalline silicon doped with ions. The concentration of the doped ions in the first highly doped layer 203 is greater than the concentration of the doped ions in the first source / drain doped region 241. Thus, the first highly doped layer 203 can improve the contact resistance between the first source / drain doped region 241 and the second electrode layer subsequently formed on the back side of the substrate 200 and the first source / drain doped region 241, thereby reducing the situation in which the direct contact between the second electrode layer and the first source / drain doped region 241 creates a large Schottky barrier and increases the contact resistance.

[0060] Please refer to Figure 6 , a first sacrificial layer 205 and a first supporting layer 206 located on the first sacrificial layer 205 are formed on the insulating layer 204 .

[0061] The material of the first sacrificial layer 205 is different from the material of the first supporting layer 206. In this embodiment, the material of the first sacrificial layer 205 includes silicon oxide, phosphorus- and boron-doped silicon oxide, or phosphorus-doped silicon oxide, and the material of the first supporting layer 206 includes silicon nitride, carbon-doped silicon nitride, or boron-doped silicon nitride.

[0062] Please continue to refer to Figure 6 , the first sacrificial layer 205, the first supporting layer 206 and the insulating layer 204 are etched to form a third groove 207 in the first sacrificial layer 205 and the first supporting layer 206, and a fifth groove 231 is formed in the insulating layer 204 at the bottom of the third groove 207. The fifth groove 231 is connected to the third groove 207, and the fifth groove 231 exposes the surface of the second source-drain doped region 242.

[0063] The process of etching the first sacrificial layer 205 , the first supporting layer 206 and the insulating layer 204 includes a dry etching process.

[0064] Please refer to Figure 7 , an initial second highly doped layer (not shown) is formed in the fifth groove 231 and the third groove 207 ; the initial second highly doped layer is etched back to form a second highly doped layer 208 in the fifth groove 231 , and the second highly doped layer 208 is in contact with the second source-drain doped region 242 .

[0065] In this embodiment, a top surface of the second highly doped layer 208 is lower than a surface of the insulating layer 204 .

[0066] In this embodiment, the material of the second highly doped layer 208 includes polycrystalline silicon doped with ions. The concentration of the doped ions in the second highly doped layer 208 is greater than the concentration of the doped ions in the second source / drain doped region 242. Thus, the second highly doped layer 208 can improve the contact resistance between the first electrode layer subsequently formed in the third recess and the second source / drain doped region 242, thereby reducing the situation in which direct contact between the first electrode layer and the second source / drain doped region 242 creates a large Schottky barrier and increases contact resistance.

[0067] Please continue to refer to Figure 7 , a metal silicide layer (not shown) is formed on the surface of the second highly doped layer 208 .

[0068] The method for forming the metal silicide layer includes: forming a metal layer (not shown) on the surface of the second highly doped layer 208; annealing the metal layer to form a metal silicide layer on the surface of the second highly doped layer 208; and removing the remaining metal layer after the metal silicide layer is formed.

[0069] In this embodiment, the material of the metal layer includes cobalt, and the metal silicide layer includes cobalt silicon.

[0070] Please refer to Figure 8 A first pillar layer 210 and a first electrode layer 209 located on the surface of the first pillar layer 210 are formed in the third groove 207. The first electrode layer 209 is electrically connected to the second highly doped layer 208. The first electrode layer 209 is located on the sidewall surface and bottom surface of the third groove 207.

[0071] The method for forming the first pillar layer 210 and the first electrode layer 209 includes: forming an initial first electrode layer (not shown) on the side wall surface of the third groove 207, the surface of the metal silicide layer and the surface of the first support layer 206; forming an initial first pillar layer (not shown) on the surface of the initial first electrode layer, and the initial first pillar layer fills the third groove 207; removing the initial first pillar layer and the initial first electrode layer on the surface of the first support layer 206 until the surface of the first support layer 206 is exposed, forming the first pillar layer 210 and the first electrode layer 209, and the first electrode layer 209 is electrically connected to the second highly doped layer 208.

[0072] In this embodiment, a top surface of the second highly doped layer 208 is lower than a surface of the insulating layer 204 , and the first electrode layer 209 is also located in the fifth groove 231 .

[0073] In this embodiment, the material of the first pillar layer 210 includes polysilicon or metal, and the metal includes titanium nitride. The material of the first pillar layer 210 needs to have a certain strength and stress to play a supporting role and not easily skew.

[0074] Please refer to Figure 9 , a portion of the first supporting layer 206 is removed, and a first groove 211 exposing the first sacrificial layer 205 is formed in the first supporting layer 206 .

[0075] A portion of the first supporting layer 206 is removed to leave an etching opening for a subsequent wet etching process for removing the first sacrificial layer 205 .

[0076] In this embodiment, the process of removing a portion of the first supporting layer 206 includes a dry etching process.

[0077] Please refer to Figure 10 A second sacrificial layer 212 and a second supporting layer 213 located on the second sacrificial layer 212 are formed on the first pillar layer 210 , the first supporting layer 206 and the first sacrificial layer 205 .

[0078] In one embodiment, the material of the first sacrificial layer is the same as the material of the second sacrificial layer.

[0079] In another embodiment, the material of the first sacrificial layer and the material of the second sacrificial layer may be different.

[0080] In this embodiment, the material of the second sacrificial layer 212 includes silicon oxide, silicon oxide doped with phosphorus and boron, or silicon oxide doped with phosphorus.

[0081] In this embodiment, the material of the second supporting layer 213 is different from the material of the second sacrificial layer 212 .

[0082] In one embodiment, the material of the first supporting layer is the same as the material of the second supporting layer.

[0083] In another embodiment, the material of the first supporting layer and the material of the second supporting layer may be different.

[0084] In this embodiment, the material of the second supporting layer 213 includes silicon nitride, carbon-doped silicon nitride, or boron-doped silicon nitride.

[0085] Please refer to Figure 11 A second pillar layer 215 and a second electrode layer 214 located on the surface of the second pillar layer 215 are formed in the second sacrificial layer 212 and the second supporting layer 213 . The second electrode layer 215 is electrically connected to the first electrode layer 209 .

[0086] The method for forming the second pillar layer 215 and the second electrode layer 214 includes: forming a fourth groove (not shown) in the second supporting layer 213 and the second sacrificial layer 212, the fourth groove exposing the top surface of the first electrode layer 209 and the top surface of the first pillar layer 210; forming the second electrode layer 214 on the side wall surface and the bottom surface of the fourth groove, the second electrode layer 214 is electrically connected to the first electrode layer 209; forming the second pillar layer 215 in the fourth groove, the second pillar layer 215 is located on the surface of the second electrode layer 214.

[0087] In one embodiment, the material of the first pillar layer is the same as the material of the second pillar layer.

[0088] In another embodiment, the material of the first pillar layer and the material of the second pillar layer may be different.

[0089] The material of the second pillar layer 215 includes polysilicon or metal, and the metal includes titanium nitride. The material of the second pillar layer 215 needs to have a certain strength and stress to play a supporting role and not be easily skewed.

[0090] Please refer to Figure 12 , a portion of the second supporting layer 213 is removed, and a second groove 217 exposing the second sacrificial layer 212 is formed in the second supporting layer 213 .

[0091] A portion of the second supporting layer 213 is removed to leave an etching opening for a subsequent wet etching process for removing the second sacrificial layer 212 .

[0092] In this embodiment, the process of removing a portion of the second supporting layer 213 includes a dry etching process.

[0093] The projection range of the first groove 211 on the substrate 200 at least partially overlaps with the projection range of the second groove 217 on the substrate 200, or the projection range of the first groove 211 on the substrate 200 does not overlap with the projection range of the second groove 217 on the substrate 200.

[0094] Please refer to Figure 13 , remove the first sacrificial layer 205 and the second sacrificial layer 212, and form an opening 218 between the first pillar layer 210, the second pillar layer 215, the first support layer 206 and the second support layer 213, and the opening 218 exposes the surface of the first electrode layer 209 and the second electrode layer 214, and the first groove 211 and the second groove 217 are connected to the opening 218.

[0095] In this embodiment, the process of removing the first sacrificial layer 205 and the second sacrificial layer 212 includes a wet etching process. The etching rate of the insulating layer 204, the first supporting layer 206, the second supporting layer 213, the first electrode layer 209, and the second electrode layer 214 during the process of removing the first sacrificial layer 205 and the second sacrificial layer 212 is lower than the etching rate of the first sacrificial layer 205 and the second sacrificial layer 212, so as to avoid damaging the insulating layer 204, the first supporting layer 206, the second supporting layer 213, the first electrode layer 209, and the second electrode layer 214.

[0096] Please refer to Figure 14 A dielectric layer 222 is formed on the surfaces of the first electrode layer 209 , the second electrode layer 214 , the first support layer 206 , and the second support layer 213 ; and a third electrode layer 223 is formed on the surface of the dielectric layer 222 .

[0097] The dielectric layer 222 includes a high dielectric constant material, such as hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0098] The materials of the third electrode layer 223, the second electrode layer 214 and the first electrode layer 209 include metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0099] In this embodiment, the dielectric layer 222 is also located on the top surface of the second pillar layer 215 .

[0100] Please continue to refer to Figure 14 A third pillar layer 224 is formed on the surface of the third electrode layer 223 , and the third pillar layer 224 fills the opening 218 .

[0101] In one embodiment, the material of the third pillar layer, the material of the first pillar layer, and the material of the second pillar layer are the same in pairs or all of them are the same.

[0102] In another embodiment, the material of the third pillar layer is different from the material of the first pillar layer and the material of the second pillar layer.

[0103] In this embodiment, the material of the third pillar layer 224 includes polysilicon or metal, and the metal includes titanium nitride.

[0104] The formation method comprises first forming a first sacrificial layer 205 and a first supporting layer 206, and a third groove within the first sacrificial layer 205 and the first supporting layer 206, forming a first electrode layer 209 within the third groove, then forming a second sacrificial layer 212 and a second supporting layer 213, and a fourth groove within the second sacrificial layer 212 and the second supporting layer 213, and forming a second electrode layer 214 within the fourth groove. The third groove and the fourth groove have a small depth-to-width ratio, which reduces the difficulty of forming the third and fourth grooves and improves production efficiency. Furthermore, portions of the first supporting layer 210 and the second supporting layer 213 are removed at different steps, so that the projection of the first groove 211 on the substrate 200 at least partially overlaps with the projection of the second groove 217 on the substrate 200, or the projection of the first groove 211 on the substrate 200 does not overlap with the projection of the second groove 217 on the substrate 200. The portions of the first supporting layer 210 and the second supporting layer 213 to be removed can be arbitrarily selected, providing greater process flexibility.

[0105] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 14 ,include:

[0106] substrate 200;

[0107] A vertical transistor located on a substrate 200;

[0108] a first pillar layer 210 located on the vertical transistor and a second pillar layer 215 located on the first pillar layer 210;

[0109] a first supporting layer 206 located between the first pillar layers 210 , wherein a top surface of the first supporting layer 206 is flush with a top surface of the first pillar layer 210 ;

[0110] a first groove located in the first supporting layer 206;

[0111] a second supporting layer 213 located between the second pillar layers 210 , wherein the top surface of the second supporting layer 213 is flush with the top surface of the second pillar layer 210 ;

[0112] a second groove located in the second supporting layer 213;

[0113] a first electrode layer 209 located on the sidewall surface and the bottom surface of the first pillar layer 210;

[0114] a second electrode layer 214 located on the sidewall surface and the bottom surface of the second pillar layer 215;

[0115] An opening located between the first pillar layer 210 , the second pillar layer 215 , the first supporting layer 206 and the second supporting layer 213 , wherein the opening exposes the surfaces of the first electrode layer 209 and the second electrode layer 214 , and the first groove and the second groove are connected to the opening;

[0116] a dielectric layer 222 located on the surface of the first electrode layer 209 , the surface of the second electrode layer 214 , the surface of the first support layer 206 , and the surface of the second support layer 213 ;

[0117] The third electrode layer 223 is located on the surface of the dielectric layer 222 .

[0118] In this embodiment, the vertical transistor includes: a channel column 201; a gate structure 202 located on the side wall surface of one side of the channel column 201; a first source-drain doped region 241 located in the channel column 201, and the surface of one end of the channel column 201 exposes the surface of the first source-drain doped region 241; a second source-drain doped region 242 located in the channel column 201, and the surface of the other end of the channel column 201 exposes the surface of the second source-drain doped region 242.

[0119] In this embodiment, the present invention further includes: a first highly doped layer 203 located on a surface of one end of the channel pillar 201 , wherein the first highly doped layer 203 is in contact with the first source-drain doped region 241 .

[0120] In this embodiment, it also includes: an isolation structure 230 located on the side wall of the channel column 201, and the channel column 201 and the gate structure 202 are located in the isolation structure 230; an insulating layer 204 located on the isolation structure 230; a second highly doped layer 208 located in the insulating layer 204, and the second highly doped layer 208 is in contact with the second source and drain doping region 242; the first pillar layer 210 is located on the second highly doped layer 208, and the first electrode layer 209 is electrically connected to the second highly doped layer 208.

[0121] In this embodiment, the semiconductor structure further includes a metal silicide layer located between the second highly doped layer 208 and the first electrode layer 209 .

[0122] In this embodiment, a top surface of the second highly doped layer 208 is lower than a surface of the insulating layer 204 .

[0123] In this embodiment, the material of the insulating layer 204 includes silicon nitride or carbon-doped silicon nitride.

[0124] In this embodiment, the material of the first pillar layer 210 includes polysilicon or metal, and the metal includes titanium nitride; the material of the second pillar layer 215 includes polysilicon or metal, and the metal includes titanium nitride.

[0125] In this embodiment, the semiconductor structure further includes: a third pillar layer 224 located on the surface of the third electrode layer 223, and the third pillar layer 224 fills the opening; the material of the third pillar layer 224 includes polysilicon or metal, and the metal includes titanium nitride.

[0126] In this embodiment, the dielectric layer 222 is made of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.

[0127] In this embodiment, the projection range of the first groove on the substrate at least partially overlaps with the projection range of the second groove on the substrate, or the projection range of the first groove on the substrate 200 does not overlap with the projection range of the second groove on the substrate 200.

[0128] In this embodiment, the material of the first supporting layer 206 includes silicon nitride, carbon-doped silicon nitride, or boron-doped silicon nitride; the material of the second supporting layer 213 includes silicon nitride, carbon-doped silicon nitride, or boron-doped silicon nitride.

[0129] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a vertical transistor on a substrate; forming a first sacrificial layer and a first supporting layer on the vertical transistor; forming a first pillar layer and a first electrode layer located on a surface of the first pillar layer in the first sacrificial layer and the first supporting layer, wherein the first electrode layer is electrically connected to the vertical transistor; After forming the first supporting layer and the first electrode layer, removing a portion of the first supporting layer to form a first groove in the first supporting layer to expose the first sacrificial layer; After removing part of the first supporting layer, forming a second sacrificial layer and a second supporting layer located on the second sacrificial layer on the first pillar layer, the first supporting layer, the first sacrificial layer and in the first groove; forming a second pillar layer and a second electrode layer located on a surface of the second pillar layer in the second sacrificial layer and the second supporting layer, wherein the second electrode layer is electrically connected to the first electrode layer; After forming the second supporting layer and the second electrode layer, removing a portion of the second supporting layer to form a second groove in the second supporting layer to expose the second sacrificial layer; After removing a portion of the second supporting layer, the first sacrificial layer and the second sacrificial layer are removed to form openings between the first pillar layer, the second pillar layer, the first supporting layer and the second supporting layer, wherein the openings expose surfaces of the first electrode layer and the second electrode layer, and the first groove and the second groove are connected to the openings; forming a dielectric layer on the surface of the first electrode layer, the surface of the second electrode layer, the surface of the first supporting layer, and the surface of the second supporting layer; A third electrode layer is formed on the surface of the dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The vertical transistor includes: a channel column; a gate structure located on the sidewall surface of one side of the channel column; a first source-drain doped region located in the channel column, and the surface of one end of the channel column exposes the surface of the first source-drain doped region; a second source-drain doped region located in the channel column, and the surface of the other end of the channel column exposes the surface of the second source-drain doped region.

3. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: forming an isolation structure on a sidewall of the channel pillar, wherein the channel pillar and the gate structure are located within the isolation structure; Before forming a first sacrificial layer and a first supporting layer on the first sacrificial layer on the vertical transistor, the method further includes: forming an insulating layer on the isolation structure, wherein the first sacrificial layer is located on the insulating layer; A second highly doped layer is formed in the insulating layer, wherein the second highly doped layer is in contact with the second source-drain doped region.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the second highly doped layer includes: forming a third groove in the first sacrificial layer and the first supporting layer; forming a fifth groove in the insulating layer at the bottom of the third groove, wherein the fifth groove exposes the surface of the second source and drain doping region; forming an initial second highly doped layer in the fifth groove and the third groove; etching back the initial second highly doped layer to form a second highly doped layer in the fifth groove.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the first pillar layer and the first electrode layer includes: forming an initial first electrode layer on the side wall surface of the third groove, the surface of the second highly doped layer and the surface of the first support layer; forming an initial first pillar layer on the surface of the initial first electrode layer, and the initial first pillar layer fills the third groove; removing the initial first pillar layer and the initial first electrode layer on the surface of the first support layer until the surface of the first support layer is exposed, forming the first pillar layer and the first electrode layer located on the surface of the first pillar layer, and the first electrode layer is electrically connected to the second highly doped layer.

6. The method for forming a semiconductor structure according to claim 5, wherein: Also includes: A metal silicide layer is formed between the second highly doped layer and the first electrode layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the metal silicide layer includes: forming a metal layer on the surface of the second highly doped layer; annealing the metal layer to form a metal silicide layer on the surface of the second highly doped layer; and removing the remaining metal layer after the metal silicide layer is formed.

8. The method for forming a semiconductor structure according to claim 5, wherein: A top surface of the second highly doped layer is lower than a surface of the insulating layer, and the first electrode layer is further located in the fifth groove.

9. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: A first highly doped layer is formed on a surface of one end of the channel pillar, wherein the first highly doped layer is in contact with the first source and drain doped regions.

10. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the second pillar layer and the second electrode layer includes: forming a fourth groove in the second supporting layer and the second sacrificial layer, the fourth groove exposing the top surface of the first electrode layer and the top surface of the first pillar layer; forming a second electrode layer on the side wall surface and bottom surface of the fourth groove, the second electrode layer is electrically connected to the first electrode layer; forming a second pillar layer in the fourth groove, the second pillar layer is located on the surface of the second electrode layer.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first sacrificial layer includes silicon oxide, silicon oxide doped with phosphorus and boron, or silicon oxide doped with phosphorus; the material of the second sacrificial layer includes silicon oxide, silicon oxide doped with phosphorus and boron, or silicon oxide doped with phosphorus.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of removing the first sacrificial layer and the second sacrificial layer includes a wet etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first supporting layer is different from the material of the first sacrificial layer, and the material of the second supporting layer is different from the material of the second sacrificial layer; the material of the first supporting layer includes silicon nitride, carbon-doped silicon nitride or boron-doped silicon nitride; the material of the second supporting layer includes silicon nitride, carbon-doped silicon nitride or boron-doped silicon nitride.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process of removing a portion of the second supporting layer and removing a portion of the first supporting layer includes a dry etching process.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first pillar layer includes polysilicon or metal, and the metal includes titanium nitride; the material of the second pillar layer includes polysilicon or metal, and the metal includes titanium nitride.

16. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming a third pillar layer on the surface of the third electrode layer, wherein the third pillar layer completely fills the opening; The material of the third pillar layer includes polysilicon or metal, and the metal includes titanium nitride.

17. The method for forming a semiconductor structure according to claim 1, wherein: The projection range of the first groove on the substrate at least partially overlaps with the projection range of the second groove on the substrate, or the projection range of the first groove on the substrate does not overlap with the projection range of the second groove on the substrate.

18. A semiconductor structure, characterized in that include: substrate; a vertical transistor located on a substrate; a first pillar layer located on the vertical transistor and a second pillar layer located on the first pillar layer; a first supporting layer positioned between the first pillar layers, wherein a top surface of the first supporting layer is flush with a top surface of the first pillar layer; a first groove located in the first supporting layer; a second supporting layer positioned between the second pillar layers, wherein a top surface of the second supporting layer is flush with a top surface of the second pillar layer; a second groove located in the second supporting layer; a first electrode layer located on the sidewall surface and the bottom surface of the first pillar layer; a second electrode layer located on the sidewall surface and the bottom surface of the second pillar layer; an opening located between the first pillar layer, the second pillar layer, the first supporting layer and the second supporting layer, wherein the opening exposes the surfaces of the first electrode layer and the second electrode layer, and the first groove and the second groove are connected to the opening; a dielectric layer located on the surface of the first electrode layer, the surface of the second electrode layer, the surface of the first supporting layer, and the surface of the second supporting layer; A third electrode layer is located on the surface of the dielectric layer.

19. The semiconductor structure according to claim 18, wherein: The vertical transistor includes: a channel column; a gate structure located on the sidewall surface of one side of the channel column; a first source-drain doped region located in the channel column, and the surface of one end of the channel column exposes the surface of the first source-drain doped region; a second source-drain doped region located in the channel column, and the surface of the other end of the channel column exposes the surface of the second source-drain doped region.

20. The semiconductor structure according to claim 19, wherein Also includes: A first highly doped layer is located on a surface of one end of the channel pillar, wherein the first highly doped layer is in contact with the first source and drain doped regions.

21. The semiconductor structure according to claim 19, wherein Also includes: an isolation structure located on a sidewall of the channel pillar, wherein the channel pillar and the gate structure are located within the isolation structure; an insulating layer located on an isolation structure; A second highly doped layer is located in the insulating layer, and the second highly doped layer is in contact with the second source and drain doping region; the first pillar layer is located on the second highly doped layer, and the first electrode layer is electrically connected to the second highly doped layer.

22. The semiconductor structure according to claim 21, wherein Also includes: A metal silicide layer is located between the second highly doped layer and the first electrode layer.

23. The semiconductor structure according to claim 21, wherein A top surface of the second highly doped layer is lower than a surface of the insulating layer.

24. The semiconductor structure according to claim 21, wherein The insulating layer is made of silicon nitride or carbon-doped silicon nitride.

25. The semiconductor structure according to claim 18, wherein The material of the first pillar layer includes polysilicon or metal, and the metal includes titanium nitride; the material of the second pillar layer includes polysilicon or metal, and the metal includes titanium nitride.

26. The semiconductor structure according to claim 18, wherein It also includes: a third pillar layer located on the surface of the third electrode layer, the third pillar layer fills the opening; the material of the third pillar layer includes polysilicon or metal, and the metal includes titanium nitride.

27. The semiconductor structure according to claim 18, wherein The material of the dielectric layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

28. The semiconductor structure according to claim 18, wherein The projection range of the first groove on the substrate at least partially overlaps with the projection range of the second groove on the substrate, or the projection range of the first groove on the substrate does not overlap with the projection range of the second groove on the substrate.

29. The semiconductor structure according to claim 18, wherein The material of the first supporting layer includes silicon nitride, carbon-doped silicon nitride or boron-doped silicon nitride; the material of the second supporting layer includes silicon nitride, carbon-doped silicon nitride or boron-doped silicon nitride.

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