Microprocessor storage instruction fusion

Abstract

A method for fusing stored instructions in a microprocessor is provided. The method includes identifying two instructions in the microprocessor's execution pipeline. The method further includes determining that the two instructions satisfy a fusion criterion. In response to determining that the two instructions satisfy the fusion criterion, the two instructions are re-encoded into a fused instruction. The fused instruction is then executed.

Description

Background Technology

[0001] This invention relates generally to the field of computing, and more specifically to the fusion of instructions in a microprocessor.

[0002] A microprocessor is a computer processor that combines the functionality of a central processing unit onto one or more integrated circuits (ICs). The processor executes instructions (e.g., store instructions) based on clock cycles. A clock cycle, or simply a "cycle," is a single electronic pulse from the processor. Typically, a processor is capable of executing a single instruction per cycle. Summary of the Invention

[0003] Embodiments of the present invention include a method, computer program product, and system for fusing stored instructions in a microprocessor. The method includes identifying two instructions in an execution pipeline of the microprocessor. The method further includes determining that the two instructions satisfy a fusion criterion. In response to determining that the two instructions satisfy the fusion criterion, the two instructions are re-encoded into a fused instruction. The fused instruction is then executed.

[0004] The embodiment also includes a microprocessor configured to fuse instructions. The microprocessor includes an instruction fetch unit, an instruction ordering unit, and a load-store unit. The instruction fetch unit is configured to determine that two store instructions fetched from memory are fused. The instruction fetch unit is further configured to re-encode the two store instructions into a fused store instruction. The instruction ordering unit is configured to receive the fused store instruction from the instruction fetch unit and store the fused instruction as an entry in a release queue. A first half of the fused store instruction is stored in a first half of the release queue, and a second half of the fused store instruction is stored in a second half of the release queue. The load-store unit is configured to receive the fused store instruction from the release queue, generate a memory address using the first half of the fused store instruction, store the memory address in a memory reordering queue, and store data from the second half of the fused store instruction in a memory data queue.

[0005] The above overview is not intended to describe every illustrated embodiment or implementation of the invention. Attached Figure Description

[0006] The accompanying drawings, which are incorporated in and form a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. The drawings are merely illustrative of exemplary embodiments and do not limit the scope of the invention.

[0007] Figure 1 A high-level block diagram of various components of an example processor microarchitecture according to an embodiment of the present invention is shown.

[0008] Figure 2 A block diagram of an example microarchitecture of a processor configured with fused instructions according to an embodiment of the present invention is shown.

[0009] Figure 3A An embodiment of the present invention is shown. Figure 2 Here is a block diagram of an example instruction acquisition unit (IFU).

[0010] Figure 3B An embodiment of the present invention is shown. Figure 2 A block diagram of an example instruction sorting unit (ISU).

[0011] Figure 3C Illustration of an embodiment of the present invention Figure 2 Block diagrams of example vector / scalar units (VSUs) and example load-store units (LSUs).

[0012] Figure 3D An embodiment of the present invention is shown. Figure 2 A flowchart of the completion and exception handling.

[0013] Figure 4 A flowchart illustrating an exemplary method for fusing instructions executed by a microprocessor according to an embodiment of the present invention is shown.

[0014] Figure 5 A high-level block diagram of an exemplary computer system, according to embodiments of the present invention, is shown that can be used to implement one or more of the methods, tools, modules, and any related functions described herein.

[0015] While the embodiments described herein are subject to various modifications and alternatives, their details have been illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that the specific embodiments described are not intended to be limiting. Rather, the invention is intended to cover all modifications, equivalents, and substitutions that fall within the scope of the invention. Detailed Implementation

[0016] The various aspects of this invention generally relate to the field of computing, and more particularly to the integration of memory instructions in microprocessors. While the invention is not necessarily limited to these applications, its various aspects can be understood through discussion of various instances within the context.

[0017] Currently, store instructions executed within a microprocessor core or thread are processed individually (i.e., one at a time). Consequently, a single load-store instruction can be issued every clock cycle, thus limiting the processor's execution bandwidth. Adding more cores or hardware threads can improve performance, but each core / hardware thread occupies a considerable amount of space on the processor die.

[0018] Embodiments of the present invention are designed to improve execution bandwidth and have a moderate impact on component size, thereby increasing microprocessor performance. Embodiments of the invention include examining the preceding execution flow (e.g., during instruction fetch) and identifying instructions that can be fused and executed together (e.g., store instructions). These instructions, referred to herein as “fusionable instructions,” are then re-encoded into new instructions with a new IOP (instruction opcode) referred to herein as “fused instructions.” The fused instructions appear as a single instruction for atomically performing two stores. The fused instructions can be buffered into the execution flow and executed as a single instruction, thus requiring only a single clock cycle to complete both instructions.

[0019] In some embodiments, when the Instruction Fetch Unit (IFU) fetches instructions from the L2 cache, it analyzes the instructions to see if they can be fused. The IFU uses a set of fusion criteria to determine whether instructions can be fused. For example, the IFU may look for two store instructions that access adjacent memory as they enter the core. This can be executed by hardware logic before the instructions are placed in the instruction cache (Icache). In some embodiments, when recoding / fusing instructions, the IFU may remove unnecessary bits (e.g., reduce a 32-bit instruction to 20 bits while preserving its type (load / store) and size).

[0020] In some embodiments, instructions may need to be consecutive for fusion. However, in other embodiments, fusion may involve one or more instructions in between, provided they are not intermediate branch instructions. Additionally, in some embodiments, fusion requires instructions to have the same base address register, the same size, and offsets of a specific size. For example, if store instructions are all 8-bit stores, the offsets must differ by 8 bits (assuming the instructions have the same base address register) to ensure they are written to contiguous memory locations.

[0021] Embodiments of the present invention support both rising and falling memory merging. For example, for 8-bit memory, instructions can be shifted x+0 from the base register and x+8 from the base register, or vice versa, x+8 and x+0. In other words, the order in which two instructions are fetched is irrelevant as long as they are to be written to adjacent memory regions (e.g., proven by the difference between their offsets equaling the memory size). If fetching an instruction results in the second instruction being written to the first memory location (i.e., the memory location directly preceding the first instruction), then the system can “flip” the order of the instructions after merging. In these embodiments, the publish queue (ISQ) is instructed to swap instructions before sending them to the load-memory unit (LSU). The determination of whether instructions need to be flipped and whether they are merging is part of the pre-decoding, and whether bit flags indicate whether an swap exists. Therefore, in some embodiments, there are two bits used as flags: the first bit indicates whether instructions will be merged, and the second bit indicates whether their order is swapped. These bits can override existing bits used for existing IOPS. In any case, instructions will still be loaded in the appropriate order for atomic execution.

[0022] Embodiments of the present invention may support the merging of various memory sizes depending solely on the processor architecture. For example, some embodiments may be configured to merge memories including single-bit, half-word, single-word (SW), double-word (DW), and four-word (QW) memories. Larger memories may require additional processing depending on the queue, bus, and memory size. For instance, if the memory queue is 16 bytes wide, it is possible to process the merging of two double-word to 16-byte memories using a single issue and a single STAG (as discussed herein). However, merging two four-word memories into 32-byte memory may require two instruction issues and two consecutive STAG writes.

[0023] Although embodiments of the invention are described herein using a 16-byte (128-bit) storage queue, it should be understood that this is for illustrative purposes. As those skilled in the art will recognize, the embodiments described herein can be applied to storage queues of other sizes, and the invention is not limited to 16-byte storage queues.

[0024] Now turn to the attached diagram. Figure 1 A high-level block diagram of various components of an exemplary microprocessor 100 according to an embodiment of the present invention is shown. The microprocessor 100 includes an instruction fetch unit (IFU) 102, an instruction sorting unit (ISU) 104, a load-store unit (LSU) 108, a vector / scalar unit (VSU) 106, and completion and exception handling logic 110.

[0025] The IFU 102 is the processing unit responsible for organizing program instructions, which are fetched from memory and executed in the appropriate order. The IFU 102 is often considered part of the control unit of the Central Processing Unit (CPU), such as the unit responsible for directing the processor's operations. About Figure 3A A more detailed example of IFU 102 is discussed.

[0026] The ISU 104 is the computation unit responsible for dispatching instructions to a release queue, renaming registers to support out-of-order execution, distributing instructions from the release queue to the execution pipeline, completing instruction execution, and handling exceptions. The ISU 104 includes a release queue that distributes all instructions once dependencies are resolved. For a more detailed example of the ISU 104, see [link to ISU 104 documentation]. Figure 3B discuss.

[0027] The VSU 106 is the computation unit that maintains ownership of the sliced ​​object file (STF). The STF holds the registers required for storing address operands and sends stored data to the LSU 108 for execution.

[0028] The LSU 108 is the execution unit responsible for executing all load and store instructions, managing the interface between the processor core and the rest of the system using a unified cache, and performing address translation. For example, the LSU 108 generates virtual addresses for load and store operations, and it loads data from memory (for load operations) or stores data from registers to memory (for store operations). The LSU 108 may include a queue for memory instructions, and the LSU 108 can operate independently of other units. About Figure 3C A more detailed example of LSU108 is discussed.

[0029] Completion and exception handling logic 110 (hereinafter "Completion Logic" 110) is responsible for simultaneously completing both parts of a merged memory instruction (e.g., two instructions). If the merged memory instruction causes an exception, Completion Logic 110 refreshes both parts of the merged instruction and signals the IFU to re-fetch the merged instruction as two separate instructions (i.e., no merging). Regarding Figure 3D A more detailed example of completing logic 110 is discussed.

[0030] It should be understood that Figure 1 Components 102-110 shown are provided for illustrative purposes and to explain the principles of embodiments of the invention. In some embodiments, some processor architectures may include more, fewer, or different components, and various functions of components 102-110 may be performed by different components. For example, exception and completion handling may be performed by ISU 104.

[0031] Additionally, the processor may include more than one of the components 102-110. For example, a multi-core processor may include one or more instruction fetch units (IFUs) 102 per core. Furthermore, although generally referring to The present invention has been described in the processor examples, but this is for illustrative purposes only. The invention can be implemented using other processor architectures and is not limited to the POWER processor.

[0032] For reference Figure 2 The diagram illustrates an exemplary microprocessor 200 configured to fuse instructions according to an embodiment of the present invention. The microprocessor 200 includes an IFU 102, an ISU 104, a VSU 106, and an LSU 108. The IFU, ISU, VSU, and LSU can be substantially similar to those described above. Figure 1 The IFU 102, ISU 104, VSU 106 and LSU 108 are discussed.

[0033] Figure 2 This shows how IFU 102, ISU 104, VSU 106, and LSU 108 are connected to each other, and their various sub-components. Figures 3A-3D This will be discussed in more detail. For example, as... Figure 2 As shown, IFU 102 includes fusion detection logic 202, Icache 204, decoding logic 206, and instruction buffer (IBUF) 208. A pair of channels connect IFU 102 (specifically via IBUF 208) to ISU 104 (specifically to dispatch channels 210A and 210B, collectively referred to as dispatch 210).

[0034] ISU 104 includes dispatch 210, completion logic 212, mapper 214, release queue (ISQ) 216, a pair of release multiplexers (muxes) 218A and 218B, and a STAG free list 220. Dispatch 210 includes two dispatch channels 210A and 210B. Similarly, ISQ 216 includes even half 216A and odd half 216B. Each of the release multiplexers 218A and 218B is connected to one half of ISQ 216. For example, the first release multiplexer 218A is connected to the ISQ even half 216A, and the second release multiplexer 218B is connected to the ISQ odd half 216B. The output from the two multiplexers 218A and 218B is sent to VSU 106 (specifically, to slice target file (STF) 230).

[0035] VSU 106 includes STF 230, which is a register file that holds the memory address operands and the memory data sent to LSU 108 for execution. VSU 106 receives data from multiplexers 218A and 218B of ISU 104 and outputs data to LSU 108.

[0036] LSU 108 includes a set of operation latches 232A1, 232A2, 232B, an address generator (AGEN) 234, a storage reordering queue (SRQ) 236, and a storage data queue (SDQ) 238. LSU 108 is connected to ISU 104 via completion and exception logic 212.

[0037] Now for reference Figure 3A It illustrates an embodiment of the present invention. Figure 2 The example instruction for obtaining the unit (IFU) is shown in the block diagram above. Figure 2 The IFU 102 discussed includes multiple sub-components. Specifically, the example IFU 102 includes pre-decoding and fusion detection logic 202, instruction cache (Icache) 204, decoder logic 206, and instruction buffer (IBUF) 208.

[0038] In embodiments of the invention, pre-decoding and fusion detection logic 202 determines whether two (or more) instructions are fusionable (e.g., satisfying the fusion criteria of microprocessor 100). This can be done when IFU 102 fetches instructions from a cache (e.g., L2 cache). Pre-decoding and fusion detection logic 202 examines the fetched instructions and uses a set of fusion criteria to determine whether two (or more) instructions are fusionable.

[0039] In some embodiments, the set of fusion criteria considers one or more of the following: whether the instructions are close to each other in the fetch queue (e.g., consecutive instructions, only one instruction between them, etc.), whether the instructions have the same base address register, the offset of the instructions, and the type of the instructions (e.g., D-type storage and X-type storage). For example, in some implementations, the pre-decoding and fusion detection logic 202 may be configured to determine that a pair of instructions is fusionable if (1) the instructions are both D-type storage instructions, (2) the instructions are consecutive instructions, (3) the instructions have the same length (e.g., byte, half-word, single-word, double-word, quad-word), and (4) the instructions are contiguous in memory (e.g., based on the contiguousness of their adjacent fields). The type and length of the instructions can be determined based on the RA field of the instructions. Instructions that do not meet all four criteria may be non-fusionable in these implementations.

[0040] In other implementations, the set of fusion criteria may require stricter or less strict conditions to be fusionable. For example, some implementations may allow fusion of X-shaped memory instructions by analyzing the registers of each instruction. Similarly, some embodiments may allow fusion of discontinuous instructions (i.e., at least one instruction between them), such as if the instructions are within two instructions of each other. For example, IFU 102 may include logic that compares each instruction with the instructions following (and / or preceding) it and the instructions following the next (or preceding the next). In some embodiments, consecutive but out-of-order instructions may be fused.

[0041] There are two main types of memory instructions: D-type memory and X-type memory. For D-type memory, the memory address is determined by adding a 16-bit immediate offset from the instruction itself to the base register. For X-type memory, the memory address is formed by reading two registers and adding them together. Because D-type memory only requires knowing the base register and the offset, determining whether an instruction is writing to a contiguous region of memory is relatively straightforward. However, for X-type memory, it can be difficult to detect whether memory is fused from the instruction itself. For example, the processor might notice that one of the registers is identical, but the others might not be. Accordingly, in some embodiments, only D-type memory is supported, while in others, fused X-type memory may be supported.

[0042] After determining that an instruction is fusion-compatible, the pre-decoding and fusion detection logic 202 re-encodes the fusion-compatible instruction into a new instruction (referred to herein as a fusion-compatible instruction), marks the fusion-compatible instruction, and writes the fusion-compatible instruction into the instruction cache (Icache) 204. The pre-decoding and fusion detection logic 202 identifies whether the instruction being written to Icache 204 is a fusion-compatible instruction by setting a flag. For example, the pre-decoding and fusion detection logic 202 can set a specified bit to 1 when the instruction is a fusion-compatible instruction and set the specified bit to 0 when the instruction is not a fusion-compatible instruction.

[0043] After the pre-decoding and fusion detection logic 202 writes the fused instructions to Icache 204, the decoding logic 206 can retrieve the fused instructions, decode them, and store them in IBUF 208. IFU 102 can then use a channel pair to transmit the fused instructions from IBUF 208 to ISU 104. The first half (Store0) of the fused instructions can be transmitted to ISU 104 via the first channel (i.e., forwarded to...). Figure 3B In A1), and the second half of the fused instruction (Store1) can be sent to ISU 104 via the second channel (i.e., to... Figure 3B (A2 in the document). In addition, an instruction that Store0 and Store1 are half of the merged storage instructions is sent to ISU 104.

[0044] In embodiments that enable out-of-order instruction fusion, the pre-decoding and fusion detection logic 202 may further configure a second bit of the instruction used for fusion. The second bit indicates that the two halves of the fused instruction are reversed (i.e., the second half modifies the first memory location, and the first half modifies the subsequent memory location). In other words, some embodiments support both rising and falling memory fusion.

[0045] Now refer to Figure 3B This illustrates an embodiment of the invention. Figure 2 A block diagram of an example instruction sorting unit (ISU) 104 is provided. In an embodiment of the invention, ISU 104 includes a dispatch 210. The dispatch is configured to transmit merged instructions (e.g., merged storage) to a mapper 214, a release queue 216, and completion logic 212 on a paired channel. The merged instructions will be used in two dispatch slots 210A and 210B.

[0046] Mapper 214 stores register tags (e.g., STF tags) of the fused instructions received from dispatch 210. The STF tag identifies the register identified by the instruction constituting the fused instruction. The mapper may also store instruction tags (ITAGs) for the instructions.

[0047] Dispatch 210 is also configured to assign STAGs to merged instructions. STAGs are fields that indicate the physical location in the storage queue entry to which the instruction is written, and they are assigned from the ISU 104 dispatcher using the STAG free list 220. The STAG free list 220 includes a list of available STAGs that dispatch 210 can assign to instructions. If the merged instruction includes two single-word (SW) or double-word (DW) instructions, then dispatch assigns only one STAG to the merged instruction. If the merged instruction includes two quad-word (QW) instructions, then both STAGs are assigned to the merged instruction.

[0048] Completion logic 212 is configured to write the instruction tags (ITAGs) of the two instructions that make up the merged instruction into the completion table. Completion logic 212 also marks these two instructions as atomic, meaning that they must both be completed together. The completion logic also automatically completes the second half of the merged store instruction.

[0049] The fused instructions are then written to ISQ 216. In some embodiments, dispatch 210 sends the base address register index (RA), immediate offset (1mm field), and STAG(s) for both halves of the fused instructions (Store0 and Store1) to ISQ 216. Dispatch 210 may also send an indication that Store0 and Store1 are half of the fused stored instructions and whether ISQ needs to reverse the storage order (e.g., if they are consecutive but in reverse order). Additionally, mapper 214 sends the RS and RA STF tag information for Store0 and Store1 to ISQ 216.

[0050] Typically, stored instructions are written to a single half of ISQ 216. For example, an unfused instruction will be written as an entry in either ISQ even half 216A or ISQ odd half 216B, but not both. However, fused instructions are stored as a complete ISQ entry (e.g., an entry spanning both ISQ even half 216A and odd half 216B). Accordingly, information about the first half (Store0) of the fused instruction is sent to even channel 216A of ISQ 216, while information about Store1 is sent to odd channel 216B of ISQ 216.

[0051] The data portion of the merge instruction will wait in ISQ 216 until both storage data are available before being published. For merge instructions with storage DW or fewer, ISQ 216 will perform a single publication for both sources of storage data. For merge instructions with storage QW, ISQ 216 will publish the storage data twice: once for each of the two STF tags that are sources of the merged storage data.

[0052] In other words, because the merged memory requires reading two memory data entries from two different registers to be merged in the SDQ 238, the ISQ 216 waits for both to be ready before attempting to publish the memory data. For example, if the two memory data operands originate from two previous loads, the ISQ 216 waits until both loads are written back to the STF 230 before publishing the memory data(s). As an example, if the total merge width is 16 bytes or less, this will occur with the publication of one memory data entry on the 16-byte memory data bus. If the total merge width is 32 bytes, there will be two publications on the 16-byte memory data bus, which will write two consecutive STAG entries, each 16 bytes wide in the SDQ 238.

[0053] When both storage data are available, the data from ISQ 216 will be multiplexed by publish multiplexers 218A and 218B, and the output will be sent to VSU 106. VSU 106 will process the data and send the information to LSU 108 for execution. Figures 3A to 3D In the embodiment shown, storage address generation (AGEN) will be published from even channel 216A, and storage data will be published from odd channel 216B.

[0054] See now Figure 3C The illustration shows an embodiment of the present invention. Figure 2 The block diagrams are of an example vector / scalar unit (VSU) 106 and an example load-store unit (LSU) 108. The VSU 106 includes a slice object file (STF) 230, and the LSU 108 includes a set of operation latches 232A1, 232A2, 232B, an address generator (AGEN) 234, a storage reordering queue (SRQ) 236, and a storage data queue (SDQ) 238.

[0055] STF 230 is a register file for structured registers. While the main structured registers are general-purpose registers (GPR), vector / scalar registers (VSR), and floating-point registers (FPR), all structured registers can be included in STF 230. Arithmetic operations read from STF 230, are performed internally in VSU 106 using the data read from STF 230, and then written back to VSU 106. For LSU 108 memory operations, STF 230 is read from LSU 108, and address and data operands are sent to LSU 108 for execution.

[0056] STF 230 receives the RS-STF tags for Store0 and Store1, along with the storage RA, 1mm offset, and STAG from ISU 104. VSU 106 sends two address operands to two operand latches 232A1 and 232A2 in LSU 108. For storage convergence cases limited to D-shaped storage, the first operand (OpA) is the base address register read from STF 230, and the second operand (OpB) is the immediate offset. Figure 3C As shown, the first operand can be sent to the first operand latch 232A1 of LSU 108, while the second operand can be sent to the second operand latch 232A2 of LSU 108.

[0057] Using the received information (e.g., the base address register and immediate offset), the LSU 108 uses the AGN 234 to generate the appropriate memory address. Then, using the STAG as the write address, the memory address generated by the AGN 234 is sent to the SRQ 236. Assuming a 128-bit width, for a memory DW or smaller, the merged memory consumes a single SRQ entry. Similarly, for a memory QW, the merged memory consumes two SRQ entries.

[0058] The stored data will have two sources (SRCs), meaning two STF 230 register entries read from which the overall merged stored data to be published is obtained. The merged stored data is sent with one SRC on the first half of the available bits and a second SRC on the second half. For example, again assuming a 128-bit bandwidth bus and DW or less storage, the first SRC is sent at bits [0:63] and the second SRC at bits [64:127]. The two halves of the stored data bus are independently formatted to form a contiguous block of data. In this example, all stored data is sent on the data bus in the same cycle. For QW storage, data is sent in two cycles. Stored data is written to SDQ 238 using STAG as the address pointer. For DW or less storage, the merged stored data will consume one SDQ 238 entry. For QW storage, the merged stored data will consume two SDQ 238 entries.

[0059] The SDQ 238 moves to either L1 or L2 cache. However, data must be shifted in a unique way before it can be stored, depending on the size of the memory queue and the instruction size. This is because data may not be back-to-back on the bus due to how it is read from registers and / or due to padding. Reading data from separate registers: one instruction uses the bottom half of the bus, while another uses the top half. For SW to memory DW, the system wants to store 8 bytes across two memory locations. However, because the bus is 16 bytes wide, and each instruction uses half of its allocated space (e.g., four out of its 8 bytes), the processor must first shift the first four bytes to be adjacent to the last four bytes before entering the memory data queue.

[0060] Similarly, it differs slightly when you converge quad-word storage compared to a double-word storage with a 16-byte storage data bus. When it's smaller than a QW converged storage, there's only one storage data post, with one instruction sent on bits 0-63 and another on bits 64-127. In the case of a DW converged storage, bits 0-63 are used for both instructions (0-31 for the first instruction and 32-63 for the second). For a SW converged storage, only bits 0-31 are used (0-15 for the first instruction and 16-31 for the second).

[0061] For cache-prohibited storage (or for LSU 108 exceptions), LSU 108 will signal IFU 102 (via ISU 104) to perform a single refresh to split the merged storage instruction into two separate storage instructions. These two separate instructions will then be processed like normal instructions.

[0062] See now Figure 3D The illustration shows an embodiment of the present invention. Figure 2 A block diagram of the completion and exception handling logic. The completion and handling logic may be part of the completion and exception logic 212 of ISU 104.

[0063] If LSU 108 detects an anomaly, it will signal ISU 104 completion and anomaly logic 212 to notify that an anomaly has been detected. ISU 104 completion and anomaly logic 212 then signals IFU 102 to notify that the merged memory should be refreshed and separated. IFU 102 then handles the broadcast of the refresh to the core and tracks the original memory instructions that should not be merged.

[0064] Completion logic 240 will complete both halves of the merged memory instruction simultaneously, provided no identified exception is found. If the merged memory instruction causes an exception, completion logic 240 will refresh both halves of the merged memory instruction 242. It will then signal IFU 102 to re-fetch the merged memory instruction as two separate memory instructions (i.e., without merging them). The memory instruction will resume execution from the first half of the original merged memory instruction. An exception will be taken for the appropriate half of the original merged memory instruction.

[0065] For example, if two stores that are merged span a translation page (e.g., the first store is in the first page and the second store is in the second page), the anomaly detection logic can indicate the presence of an anomaly. The system may receive a release where one store does not want to log the anomaly, while the other does (e.g., because it crosses a page boundary). In these cases, the system needs to log the anomaly at the correct store / address. This will cause both instructions to be re-fetched and processed as non-mergeable instructions.

[0066] Merging can also be disabled after a non-branch refresh. Depending on the implementation, merging can be disabled for the first pair of commands fetched, for more than two commands, or for the entire first fetch.

[0067] It should be understood that Figure 2-3D The components and sub-components 102-242 shown are provided for illustrative purposes and to explain the principles of embodiments of the invention. In some embodiments, some processor architectures may include more, fewer, or different components, including more, fewer, or different sub-components, and various functions of components and sub-components 102-242 may be performed by different components. Additionally, a processor may include more than one of components 102-242, and these components may be arranged in different orders. For example, a multi-core processor may include one or more instruction fetch units (IFUs) 102 per core. Furthermore, although generally referred to... The present invention has been described in the processor examples, but this is for illustrative purposes only. The invention can be implemented using other processor architectures and is not limited to the POWER processor.

[0068] Now for reference Figure 4 The illustration shows a flowchart of an exemplary method 400 for fusing storage instructions in a microprocessor according to an embodiment of the present invention. Method 400 may be performed by hardware, firmware, software executing on the processor, or any combination thereof. Method 400 may begin at operation 402, wherein two or more instructions are detected.

[0069] When two or more instructions are fetched from memory (e.g., from the L2 cache) for execution, they can be detected by the IFU. After detecting two or more instructions, the IFU can determine at decision box 404 whether the instructions satisfy a set of fusion criteria. As discussed herein, the fusion criterion set is a set of rules for determining whether instructions can be fused. The fusion criterion set can be based on the processor architecture (e.g., how hardware units are configured). The fusion criterion set can include whether the instructions are close to each other in the fetch queue (e.g., consecutive instructions, only one instruction between them, etc.), whether the instructions have the same base address register, the instruction offset, and the instruction type (e.g., D-type memory and X-type memory).

[0070] If the instructions do not satisfy the set of fusion criteria, the instructions can be executed individually at operation 414, and method 400 can terminate. However, if the instructions do satisfy the set of fusion criteria, the instructions can be fused at operation 406. Additionally, the instructions can be marked (e.g., by IFU) to indicate whether they are fused, and whether the instructions are in sequence or need to be flipped.

[0071] At operation 408, the processor attempts to execute the fused instructions as a single instruction, as described herein. If no exception is found at decision box 410, the stored instructions complete and the fused instructions are executed. However, if an exception is detected at decision box 410, the fused instructions are refreshed, and the fused instructions are re-fetched. The re-fetched instructions are then executed individually (e.g., normally), and method 400 terminates.

[0072] Now for reference Figure 5 This illustration shows a high-level block diagram of an exemplary computer system 501, according to embodiments of the present invention, which can be used to implement one or more of the methods, tools, and modules described herein and any related functions (e.g., using one or more processor circuits of a computer or a computer processor). In some embodiments, the main components of the computer system 501 may include one or more CPUs 502, a memory subsystem 504, a terminal interface 512, a storage interface 516, an I / O (input / output) device interface 514, and a network interface 518, all of which may be directly or indirectly communicatively coupled for inter-component communication via a memory bus 503, an I / O bus 508, and an I / O bus interface unit 510.

[0073] Computer system 501 may include one or more general-purpose programmable central processing units (CPUs) 502A, 502B, 502C, and 502D, collectively referred to herein as CPU 502. In some embodiments, computer system 501 may include a typical multiple processors of a relatively large system; however, in other embodiments, computer system 501 may alternatively be a single CPU system. Each CPU 502 may execute instructions stored in memory subsystem 504 and may include one or more onboard caches.

[0074] System memory 504 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 522 or cache memory 524. Computer system 501 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 526 may be configured to read from and write to non-removable, non-volatile magnetic media (such as a "hard disk drive"). Although not shown, a disk drive may be provided for reading from or writing to a removable non-volatile disk (e.g., a "floppy disk"), or an optical disk drive may be provided for reading from or writing to a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM, or other optical media). Furthermore, memory 504 may include flash memory, such as a flash stick drive or a flash drive. Memory devices may be connected to memory bus 503 via one or more data media interfaces. Memory 504 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of different embodiments.

[0075] One or more programs / utilities 528, each having at least one set of program modules 530, may be stored in memory 504. Programs / utilities 528 may include a hypervisor (also called a virtual machine monitor), one or more operating systems, one or more applications, other program modules, and program data. Each or some combination of the operating system, one or more applications, other program modules, and program data may include an implementation of a network environment. Program modules 530 typically perform functions or methods of different embodiments.

[0076] Although the memory bus 503 is Figure 5 The diagram illustrates a single bus structure providing a direct communication path between CPU 502, memory subsystem 504, and I / O bus interface 510. However, in some embodiments, memory bus 503 may include multiple different buses or communication paths, which may be arranged in any of a variety of forms, such as point-to-point links in hierarchical, star, or network configurations, multiple hierarchical buses, parallel and redundant paths, or any other suitable type of configuration. Furthermore, although I / O bus interface 510 and I / O bus 508 are shown as a single corresponding unit, in some embodiments, computer system 501 may include multiple I / O bus interface units 510, multiple I / O buses 508, or both. Further, while multiple I / O interface units are shown separating I / O bus 508 from different communication paths running to different I / O devices, in other embodiments, some or all of the I / O devices may be directly connected to one or more system I / O buses.

[0077] In some embodiments, computer system 501 may be a multi-user mainframe computer system, a single-user system, a server computer, or a similar device that has little or no direct user interface but receives requests from other computer systems (clients). Further, in some embodiments, computer system 501 may be implemented as a desktop computer, portable computer, laptop or notebook computer, tablet computer, pocket computer, telephone, smartphone, network switch or router, or any other suitable type of electronic device.

[0078] It is important to note that Figure 5 This description aims to depict representative major components of an exemplary computer system 501. However, in some embodiments, a single component may have more than Figure 5 The greater or lesser complexity represented therein can exist differently from... Figure 5 The components shown or excluding Figure 5 Components other than those shown are included, and the number, type, and configuration of such components may vary. Furthermore, modules are listed and described illustratively according to embodiments and do not imply the necessity of a particular module or the exclusivity of other potential modules (or functions / purposes applied to a particular module).

[0079] This invention can be a system, method, and / or computer program product with any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (one or more media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention.

[0080] Computer-readable storage media can be a tangible means for retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0081] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0082] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing state information from the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this invention.

[0083] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0084] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0085] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0086] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the figures. For example, two blocks shown consecutively may actually be completed as a single step, executed simultaneously, substantially simultaneously, or with partial or complete temporal overlap, or the blocks may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0087] It should be understood that the above advantages are exemplary and should not be construed as limiting. Embodiments of the present invention may include all, some, or not include the above advantages while remaining within the scope of the invention.

[0088] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the various embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It should also be understood that when the terms “comprising” and / or “including” are used in this specification, they specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. In the preceding detailed description of exemplary embodiments of the various embodiments, reference has been made to the accompanying drawings (in which like numerals denote like elements), which form a part of the description and illustrate specific exemplary embodiments in which the various embodiments may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, but other embodiments may be used and logical, mechanical, electrical, and other changes may be made without departing from the scope of the different embodiments. In the preceding description, numerous specific details have been set forth to provide a thorough understanding of the various embodiments. However, the various embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the embodiments.

[0089] As used in this article, when referring to a project as “multiple,” it means one or more projects. For example, “multiple different types of networks” means one or more different types of networks.

[0090] When different reference numbers include common numbers followed by different letters (e.g., 100a, 100b, 100c) or punctuation followed by different numbers (e.g., 100-1, 100-2, or 100.1, 100.2), the reference character without letters or following numbers (e.g., 100) may refer to the group of elements as a whole, any subset of that group, or an example sample of that group.

[0091] Furthermore, when used with a series of items, the phrase "at least one" indicates that different combinations of one or more of the listed items can be used, and only one item from each of the listed items may be required. In other words, "at least one" means that any combination of items and multiple items from the list can be used, but not all items from the list. Items can be specific objects, things, or categories.

[0092] For example, but not limited to, "at least one of Item A, Item B, or Item C" can include Item A, Item A and Item B, or Item B. The example could also include Item A, Item B, and Item C, or Item B and Item C. Of course, any combination of these items can exist. In some illustrative examples, "at least one" can be, for example, but not limited to, two Item A; one Item B; and ten Item C; four Item B and seven Item C; or other suitable combinations.

[0093] In the foregoing, reference has been made to various embodiments. However, it should be understood that the invention is not limited to the specifically described embodiments. Rather, any combination of the features and elements is contemplated for implementation and practice, regardless of whether they are associated with different embodiments. Many modifications, alterations, and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. Furthermore, while embodiments of the invention may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit the invention. Therefore, the described aspects, features, embodiments, and advantages are merely illustrative and are not to be considered elements or limitations of the appended claims unless expressly stated in the claims. Moreover, the following claims are intended to be construed as covering all such changes and modifications falling within the scope of the invention.

[0094] In a preferred embodiment of the invention described herein, a processor is provided, comprising: an instruction fetch unit configured to: determine that two memory instructions fetched from memory are fusionable; and re-encode the two memory instructions into a fusion memory instruction; an instruction sorting unit configured to: receive the fusion memory instruction from the instruction fetch unit; and store the fusion memory instruction as an entry in a release queue, wherein a first half of the fusion memory instruction is stored in the first half of the release queue, and a second half of the fusion memory instruction is stored in the second half of the release queue; and a load memory unit configured to: receive the fusion memory instruction from the release queue; generate a memory address using the first half of the fusion memory instruction; store the memory address in a memory reordering queue; and store data from the second half of the fusion memory instruction in a memory data queue. The load-memory unit is preferably further configured to: identify an anomaly during execution of the fusion memory instruction; refresh the fusion memory instruction; and the instruction fetch unit re-fetch the two memory instructions. The processor is preferably further configured to: after re-fetching the two memory instructions, execute the two memory instructions as separate instructions. The two storage instructions preferably include a first storage instruction and a second storage instruction, and determining that the two storage instructions are merging preferably includes: determining that the first and second storage instructions have the same instruction type, the same instruction length, and that they will be stored in contiguous memory locations. The two storage instructions preferably include a first storage instruction fetched prior to the second storage instruction, and wherein the instruction fetching unit is further configured to: determine that the second storage instruction will be stored in a memory region directly preceding the first storage instruction; and mark the merged instruction as reversed. The instruction sorting unit is preferably further configured to: reverse the storage order of the merged instructions in response to recognizing the merged instruction as reversed.

Claims

1. A method for fusing instructions comprising: identifying two instructions in an execution pipeline of a microprocessor, wherein the two instructions comprise a first instruction and a second instruction, the two instructions are non-consecutive instructions in the execution pipeline; determining that the two instructions satisfy a fusion criteria, wherein the determining comprises determining that the first instruction and second instruction have a same instruction form, a number of instructions between the first instruction and second instruction in a fetch queue is below a threshold number, and the first instruction and second instruction store data in consecutive memory locations, wherein an instruction form of a given instruction is one of a D-form and an X-form that define a format used to encode the given instruction; in response to determining that the two instructions satisfy the fusion criteria, re-encoding the two instructions as a fused instruction; writing the fused instruction to a single entry of an issue queue via a pair of lanes, the issue queue comprising a first half issue queue and a second half issue queue, the issue queue configured to store unfused instructions in one half issue queue, the single entry spanning both the first half issue queue and the second half issue queue, wherein information for the first instruction is written to the first half issue queue via a first lane of the pair of lanes and information for the second instruction is written to the second half issue queue via a second lane of the pair of lanes; and executing the fused instruction. the first instruction and the second instruction are D-form store instructions, and wherein determining that the two instructions satisfy the fusion criteria comprises:

2. The method of claim 1, wherein, determining that the first instruction and the second instruction have a same D-form instruction form and store data in consecutive memory locations; and determining that the first instruction and the second instruction are store instructions and have a same instruction length. the method further comprising:

3. The method of claim 1, wherein, identifying an exception while executing the fused instruction; flushing the fused instruction; and re-fetching the two instructions. the method further comprising:

4. The method of claim 3, wherein, after re-fetching the two instructions, executing the two instructions separately.

5. The method of claim 3, the method further comprising: determining that the exception is related to a first instruction of the two instructions; and recording the exception against the first instruction. the first instruction is fetched before the second instruction, the method further comprising: determining that the first instruction is to store data to a first region of a memory; 6. The method of claim 1, wherein, determining that the second instruction is to store data to a second region of the memory immediately preceding the first region of the memory; labeling the fused instruction as reversed; and reversing an order of the first instruction and the second instruction in the fused instruction. the first instruction and the second instruction are D-form store instructions, and wherein determining that the two instructions satisfy the fusion criteria comprises: determining that the first instruction and the second instruction have a same D-form instruction form and store data in consecutive memory locations; 7. The method of claim 1, wherein, determining that the first instruction and the second instruction have a same base register; determining a store length of the first instruction and the second instruction, wherein the store length is the same for both the first instruction and the second instruction; and ​ ​ determining that a difference between a first offset of the first instruction and a second offset of the second instruction is equal to the store length.

8. A system comprising: a processor configured to perform the method for fusing instructions of any of the above claims.

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