Deposition method and apparatus for piezoelectric applications

Abstract

Methods and apparatus for depositing uniform layers for piezoelectric applications on a substrate (201) are disclosed. An ultrathin seed layer (308) having a uniform thickness from its center to its edge is deposited on the substrate (201). A template layer (310) closely matching the crystal structure of a subsequently formed piezoelectric material layer (312) is deposited on the substrate (201). The uniform thickness and orientation of the seed layer (308) and the template layer (310) in turn facilitate the growth of a piezoelectric material having improved crystallinity and piezoelectric properties.

Description

Technical Field

[0001] The embodiments disclosed herein generally relate to piezoelectric devices. More specifically, the embodiments disclosed herein relate to piezoelectric devices and methods for depositing films for piezoelectric devices. Background Technology

[0002] In semiconductor processing, physical vapor deposition (PVD) (e.g., sputtering) is used for atomic-level material transfer to deposit thin films or coatings on a substrate. During PVD, a target carrying source material is bombarded with ions generated from plasma within a processing chamber. The bombardment of the target causes the source material to be sputtered (e.g., jetted) from the substrate being processed. In some instances, the sputtered source material can be accelerated toward the substrate by applying a bias voltage. Upon reaching the substrate surface, the source material can react with another material on the substrate to form a thin film or coating thereon.

[0003] PVD (Polymerase Conversion) processes can be used to form thin-film piezoelectric materials that accumulate charge when mechanical stress is applied. Piezoelectric materials are commonly used in sensors and transducers in devices such as gyroscope sensors, inkjet printheads, and other microelectromechanical system (MEMS) devices, including acoustic resonators in mobile phones and other wireless electronic devices. Relaxor ferroelectrics, and especially relaxor PT (perovskite terephthalic acid) materials, are piezoelectric materials that exhibit extremely high piezoelectricity due to their unique free energy profile. To achieve these special piezoelectric properties, relaxor PT films must be grown with a uniform perovskite phase structure and... <001> Crystal orientation (e.g., (001) or (002) orientation). However, due to... <001> The orientation-dependent narrow growth window, and the fact that the material undergoes various phase transitions even with the slightest stoichiometric and / or temperature changes, make the growth of this type of relaxor PT material using conventional PVD processes extremely complex.

[0004] Therefore, what is needed in the art is an improved piezoelectric device stack and a method for forming a piezoelectric device stack by PVD. Summary of the Invention

[0005] This disclosure generally relates to piezoelectric devices. More specifically, the embodiments disclosed herein relate to piezoelectric devices and methods for depositing films for piezoelectric devices. Attached Figure Description

[0006] To gain a detailed understanding of the features described above, a more specific description of the disclosure can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and should not be considered as limiting the scope of this application, and other equally effective embodiments are permissible.

[0007] Figure 1 This is a plan view of a clustering tool according to an embodiment described herein, which is adapted to deposit a thin film layer on a substrate using one or more processing chambers.

[0008] Figure 2 The implementation method described in this case is as follows. Figure 1 The diagram shows a side cross-sectional view of a processing chamber in a clustering tool, which is adapted to deposit a thin film layer on a substrate.

[0009] Figure 3A It is based on the implementation method described in this case. Figure 1 A side view of an exemplary membrane stack produced within the clustering tool shown.

[0010] Figure 3B It is based on the implementation method described in this case. Figure 1 A side view of an exemplary membrane stack produced within the clustering tool shown.

[0011] Figure 4 This is a diagram illustrating production according to the embodiments described herein. Figure 3A and 3B A flowchart illustrating an exemplary method for membrane stacking.

[0012] Figure 5 This is a plan view of a controller according to the embodiment described in this case, which can... Figure 1 -3 illustrates that any of the processing chambers provides commands.

[0013] Figure 6A According to the implementation method described in this case, by Figure 4 X-ray diffraction (XRD) data of the piezoelectric film formed by the method described in the figure.

[0014] Figure 6B According to the implementation method described herein, by Figure 4 X-ray diffraction (XRD) data of the piezoelectric film formed by the method shown.

[0015] For ease of understanding, the same reference numerals are used as much as possible to denote the same elements commonly used in the figures. It is conceivable that elements and features of one embodiment can be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0016] This disclosure generally relates to piezoelectric devices. More specifically, the embodiments disclosed herein relate to piezoelectric devices and methods for depositing films for piezoelectric devices.

[0017] Large-scale deposition of metal films is typically challenging due to the inhomogeneity of the film from its center to its edges. During deposition processes involving sputtering (e.g., physical vapor deposition or "PVD"), differences in the atomic arrangement of the film layers on the substrate can lead to the formation of conical defects, stacking defects, and other surface defects in subsequently deposited layers. For piezoelectric device stacks, such defects can result in weakened piezoelectric coupling and suboptimal piezoelectric properties of the resulting devices.

[0018] The method disclosed in this paper enables the improvement of deposited film properties in various types of films, such as piezoelectric materials. The method achieves the deposition of seed and template layers with improved thickness and crystal orientation uniformity, which can be studied using X-ray diffraction (XRD). In some examples, an ultrathin seed layer with a uniform thickness from its center to its edge is deposited on a substrate. In other examples, a template layer with a crystal structure closely matched to the subsequently formed piezoelectric material layer is deposited on the substrate. The improved uniformity of orientation and thickness of these layers, in turn, promotes improved crystallinity in the growth of the piezoelectric material on these layers, resulting in superior piezoelectric properties.

[0019] Figure 1 This is a schematic floor plan of the Clustering Tool 100. An example of the Clustering Tool 100 is from Applied Materials, Inc., Santa Clara, California. System. It should be understood that the clustering tool 100 described below is an exemplary clustering tool, and other clustering tools, including clustering tools from other manufacturers, may be used with or modified to form the piezoelectric device stack described herein.

[0020] Cluster tool 100 includes a factory interface 104, a loading platform 140, a first transfer chamber 124, and a second transfer chamber 128. Multiple cassettes 112 or front-opening unified pods (FOUPs) are disposed on the factory interface 104 and configured to receive multiple substrates (in...) Figure 2 The substrate 201 (displayed as 201) is used for processing. The substrate 201 may have a diameter ranging from about 100 mm to about 750 mm and may be formed from a variety of materials, including silicon (Si), silicon carbide (SiC), or graphite coated with silicon carbide. In one example, the substrate 201 comprises a silicon material and has a diameter of about 1,000 cm². 2 Or a larger surface area. In another example, the surface area of ​​substrate 201 can be approximately 2,000 cm². 2 Or larger, and approximately 4,000 cm 2Or larger. Prior to processing, substrate 201 is removed from cassette 112 by factory interface robot 120 and transferred to loading platform 140 (i.e., loading locking mechanism). Once substrate processing is completed in cluster tool 100, the processed substrate 201 can be returned to its corresponding cassette 112.

[0021] The first transfer chamber 124 is part of the main frame 172 and houses the first transfer robot 132 centrally located. The first transfer robot 132 is configured to operate on the loading platform 140 alongside a plurality of first processing chambers 160. Figure 1 The diagram shows a movable substrate 201 between 160a-d) and / or through chamber 162. By using a slit valve (not shown) disposed between each of the first processing chamber 160 and through chamber 162 and the first transfer chamber 124, the first transfer chamber 124 can be selectively isolated from each of the first processing chamber 160 and through chamber 162.

[0022] Each loading platform 140 is selectively isolated from the first transfer chamber 124 via a slit valve and from the interior region 116 of the factory interface 104 via a vacuum door (not shown). In this configuration, a factory interface robot 120 in the factory interface 104 is configured to move a substrate 201 from a cassette 112 to a loading platform 140, which can be sealed and evacuated to a desired pressure for transferring the substrate 201 to the first transfer chamber 124. Once the desired pressure is reached, a first transfer robot 132 can then pick up the substrate 201 through a slit valve opening (not shown) formed between the first transfer chamber 124 and the loading platform 140.

[0023] The first processing chamber 160 may include any suitable type of processing chamber for forming a thin film stack on the substrate 201. In some embodiments, one or more of the first processing chambers 160 include orientation chambers disposed near the loading platform 140 and for aligning the substrate 201 with a desired rotational orientation within the clustering tool 100. In some embodiments, the orientation chambers may include a heat source, such as a lamp or a radiation heater that generates infrared radiation, adapted to heat the substrate 201 to a desired temperature. The orientation chambers may be further pressurized under vacuum conditions to ensure that any unwanted water or other contaminants are removed from the surface of the substrate 201 prior to processing in other downstream chambers.

[0024] In some embodiments, the first processing chamber 160 further includes one or more pre-cleaning chambers adapted to clean the surface of the substrate 201. The pre-cleaning chambers can clean the surface of the substrate 201 using a cleaning process that includes exposing the surface of the substrate 201 to radio frequency (RF) generated plasma and / or one or more pre-cleaning gas compositions, including carrier gases (e.g., argon, helium, krypton) and / or reactive gases (e.g., hydrogen). In some embodiments, the pre-cleaning chambers are adapted to perform processes that may include non-selective sputtering etching.

[0025] In some embodiments, one or more of the first processing chambers 160 are configured to process the substrate 201 in the first processing chamber by cooling the substrate 201, heating the substrate 201, etching the substrate 201, and / or depositing one or more layers on the surface of the substrate 201. In some embodiments, the deposition process may include a sputtering deposition process (i.e., a PVD deposition process). In some configurations, one or more processing chambers 160 are further configured to anneal the substrate 201.

[0026] The first transfer chamber 124 and the second transfer chamber 128 are coupled to each other via a through chamber 162. In some configurations, the first transfer chamber 124 can be evacuated to a moderately low pressure, for example, below about 1 millitor (mTorr). The second transfer chamber 128 can be evacuated to an even lower pressure, for example, 1 microtor or lower. Thus, the first and second transfer chambers 124, 128 are maintained at least at a moderate vacuum level to prevent contaminants from being transferred between the transfer chambers 124, 128 and other modules of the cluster tool 100.

[0027] Similar to the first transfer chamber 124, the second transfer chamber 128 is part of the main frame 172 and houses a centrally located second transfer robot 136. The second transfer robot 136 is configured to move the substrate 201 between each of the plurality of second processing chambers 170 and / or through chambers 162. By using slit valves (not shown) disposed between each of the second processing chambers 170 and through chambers 162 and the second transfer chamber 128, the second transfer chamber 128 can be selectively isolated from each of the second processing chambers 170 and through chambers 162.

[0028] In some embodiments, one or more of the second processing chambers 170 are configured to process the substrate 201 in the second processing chamber by cooling the substrate 201, heating the substrate 201, etching the substrate 201, and / or depositing one or more layers on the surface of the substrate 201. In some embodiments, the deposition process may include a sputtering deposition process (i.e., a PVD deposition process). In some configurations, one or more of the second processing chambers 170 are further configured to anneal the substrate 201.

[0029] Figure 2 This is a plan view of a processing chamber 200 that can be used as a first and / or second processing chamber 160, 170. The processing chamber 200 is adapted to... Figure 1 The cluster tool shown is a PVD chamber for depositing a thin film layer on substrate 201. It should be understood that the processing chamber 200 described herein is an exemplary chamber, and other PVD chambers, including PVD chambers from other manufacturers, may be used in conjunction with or modified to implement aspects of this disclosure.

[0030] like Figure 2 As shown, the processing chamber 200 includes a processing volume 202 defined by a chamber body 205. The processing volume 202 has a target 210 and a base 204 operable to support a substrate 201. The base 204 is coupled to the processing volume 202 via a rod 206 connected to a lifting system (not shown) that moves the base 204 between a raised processing position and a lowered position, which facilitates the transfer of the substrate 201 through an opening 208 in the chamber body 205 into and out of the processing chamber 200.

[0031] Target 210 is connected to power supply 212, such as a DC power supply, RF power supply, AC power supply, pulsed DC power supply, or pulsed RF power supply, via target switch 226. During the deposition process, target 210 can be negatively biased via a pulsed DC power supply providing pulsed DC power. Sputter gas flow controller 218, such as a mass flow control (MFC) device, is disposed between sputter gas source 214 and processing volume 202 to control the flow rate of sputter gas from sputter gas source 214 to processing volume 202. Reaction gas flow controller 220, such as an MFC device, is disposed between reaction gas source 216 and processing volume 202 to control the flow rate of reaction gas from reaction gas source 216 to processing volume 202.

[0032] The base 204 is connected to the base switch 230, which, when engaged, connects the base 204 to a power supply 234, such as a DC power supply, an RF power supply, an AC power supply, a pulsed DC power supply, or a pulsed RF power supply. During the deposition process, the base 204 can be negatively biased via the power supply 234, which provides RF power. In some embodiments, the processing chamber 200 is operable to independently bias the target 210 and the base 204. A controller 207 is coupled to the processing chamber 200 and configured to control various aspects of the processing chamber 200 during processing, such as connecting the target switch 226 and the base switch 230.

[0033] Figure 3A Is Figure 1The image shows a side view of an exemplary film stack 300 produced within a clustering tool. The film stack 300 includes a substrate 201, a first crystalline layer 304, a bottom electrode layer 306, a second crystalline layer 308, a piezoelectric material layer 312, and a top electrode layer 314. Typically, the layer thicknesses of the film stack 300 are highly uniform. For example, the thickness of each layer has an increment (delta) of about + / - 10% over the entire lateral length of the layer (e.g., thickness non-uniformity), such as an increment of about + / - 5%.

[0034] In some instances, substrate 201 is having <001> A 200 mm silicon (Si) substrate with crystal orientation (e.g., (001) or (002)). The substrate 201 may be formed of other metals having a suitable lattice structure, including but not limited to polycrystalline molybdenum (Mo), strontium ruthenium oxide (SrRuO3, SRO), lanthanum nickel oxide (LaNiO3, LNO), lanthanum strontium manganate (LaSrMnO3, LSMO), and calcium ruthenate (CaRuO3). In some embodiments, a thermal oxide layer 302 is grown on the surface of the substrate 201, such as a silicon or silicon oxide (SiOx) layer. For example, the thermal oxide layer 302 may be formed of silicon dioxide (SiO2). The thermal oxide layer 302 may have a thickness between about 10 nm and about 1000 nm, such as between about 15 nm and about 750 nm, for example between about 20 nm and about 500 nm. In some embodiments, the thickness of the thermal oxide layer 302 is between about 25 nm and about 200 nm, such as between about 50 nm and about 150 nm. For example, the thickness of the thermal oxide layer 302 may be between about 75 nm and about 125 nm, such as about 100 nm.

[0035] The first crystalline layer 304 can be formed directly on the surface of the substrate 201 or on the surface of the thermal oxide layer 302. The first crystalline layer 304 supports the growth of the bottom electrode layer 306, which is deposited on the surface of the first crystalline layer 304 and can serve as the bottom electrode of the device. Examples of suitable materials for the bottom electrode layer 306 include platinum (Pt), SrRuO3, LaNiO3, CaRuO3, LaSrMnO3, etc. In some embodiments, the first crystalline layer 304 is composed of materials having… <001> The bottom electrode layer 306 is formed of titanium oxide (TiOx) with an orientation (e.g., (001) or (002)), such as titanium dioxide (TiO2), and the bottom electrode layer 306 is made of titanium oxide (TiOx) with an orientation (e.g., (001) or (002)). <111> Oriented Pt formation. Highly oriented Pt. <111> The first crystalline layer 304, which forms a uniform second crystalline layer 308, is crucial for the formation of this layer, which in turn supports the formation of a piezoelectric material layer 312 with highly oriented control. Therefore, the formation of the first crystalline layer 304 of TiO2 can support the formation of only a piezoelectric material layer 312 with high orientation control. <111> Growth of oriented Pt bottom electrode layer 306.

[0036] Please note that the orientation of the bottom electrode layer 306 and the seed layers 304 and 308 can be detected and confirmed by X-ray diffraction (XRD) analysis (such as 2θ-ω scanning) and high-resolution transmission electron microscopy (HRTEM) of the cross-section. The inventors of this disclosure have discovered that, by utilizing the method described herein, only the orientation corresponding to the bottom electrode layer 306 can be detected. <111> Orientation peaks were detected using 2θ-ω scanning, and these peaks exhibited high intensities exceeding 10,000 counts per second (cps). The results indicate that the bottom electrode layer 306 and the first crystalline layer 304 are highly oriented.

[0037] In some embodiments, the thickness of the first crystalline layer 304 is between about 10 nm and about 50 nm, such as between about 20 nm and about 30 nm, or about 25 nm. In some embodiments, the thickness of the bottom electrode layer 306 is between about 50 nm and about 200 nm, such as between about 75 nm and about 175 nm, or between about 100 nm and about 150 nm, for example about 125 nm.

[0038] The second seed layer 308 is deposited on the bottom electrode layer 306 and can be formed of any suitable ultrathin metal film. In some embodiments, the second seed layer 308 is formed of Pt or titanium (Ti). In some embodiments, the second seed layer 308 is formed of the same or different material as the first seed layer 304. The second seed layer 308 has a uniform thickness between about 0.5 nm and about 5 nm, such as between about 1 nm and about 3 nm, which is confirmed by cross-sectional HRTEM. For example, the second seed layer 308 has a uniform thickness between about 1.5 nm and about 2.5 nm, such as about 2 nm. As described above, the highly uniform thin seed layer achieves uniformity of subsequent device layers and allows for improved process integration.

[0039] The piezoelectric material layer 312 is deposited on the second crystalline layer 308 and is formed of any suitable piezoelectric material. In some embodiments, the piezoelectric material layer 312 is formed of one or more layers comprising aluminum nitride or scandium-doped aluminum nitride (ScAlN). In some embodiments, the piezoelectric material layer 312 is formed of titanium nitride (TiN), hafnium nitride (HfN), or silicon nitride (Si). x N yThe piezoelectric material layer 312 is formed from one or more layers of any one or a combination thereof. In some instances, the piezoelectric material layer 312 is formed from a relaxor lead titanate (PT) type material, such as lead magnesium niobate-lead titanate (PMN-PT) and lead indium niobate-lead magnesium niobate-lead titanate (PIN-PMN-PT). The thickness of the piezoelectric material layer 312 can be between about 500 nm and about 2000 nm, such as between about 750 nm and about 1500 nm, such as about 1000 nm.

[0040] The top electrode layer 314 is deposited on the piezoelectric material layer 312 and can serve as the top electrode of the finished device. In some instances, the top electrode layer 314 is formed of the same or different material as the bottom electrode layer 306. For example, the top electrode layer 314 may be made of a material having <111> Oriented Pt formation. In some instances, the thickness of the top electrode layer 314 is between about 30 nm and about 200 nm, such as between about 50 nm and about 150 nm, for example about 100 nm.

[0041] Figure 3B Is Figure 1 A side view of another exemplary membrane stack 301 produced within the clustering tool disclosed herein. As described in reference membrane stack 300, the layers of membrane stack 301 are highly uniform in thickness. For example, the thickness of each layer has an increment of approximately + / - 10% (e.g., variance) over the entire lateral length of the layer, such as an increment of approximately + / - 5%. Membrane stack 301 includes the layers described above. Figure 3A The described layer further includes a template layer 310. The template layer 310 may be deposited directly on the surface of the bottom electrode layer 306 or the second crystal layer 308, and below the piezoelectric material layer 312.

[0042] When the piezoelectric material layer 312 is formed of a relaxor PT-type piezoelectric material, the formation of the template layer 310 is beneficial. Relaxor PT-type piezoelectric materials are a type of composite oxide material that exhibits exceptionally high piezoelectricity due to its unique free energy profile. When the relaxor PT-type material is... <001> These piezoelectric properties are enhanced during orientation formation. Therefore, in the example where the piezoelectric material layer 312 is formed of a relaxor PT-type piezoelectric material (such as PMN-PT), the template layer 310 can be formed by an orientation of... <001> The perovskite PZT film is formed. PZT has a crystal structure that closely matches the crystal structure of relaxor PT-type piezoelectric materials, and therefore, the PZT template layer 310 can reduce the growth of perovskite PZT films on it. <001> The nucleation energy of the oriented, relaxable PT-type piezoelectric material layer 312 leads to the growth of a cubic-to-cubic crystal through heteroepitaxial growth. This type of growth provides improved crystallinity, as seen in XRD analysis, such as 2θ-ω scans. <001> The peak intensity increased fivefold (e.g., 5x). Higher XRD intensity is crucial for obtaining significantly improved piezoelectric properties. Furthermore, since PZT itself is a piezoelectric material, increasing the thickness of the PZT template layer 310 does not adversely affect the electromechanical properties or response of the relaxor PT-type piezoelectric material layer 312. In some instances, the thickness of the template layer 310 is between approximately 10 nm and approximately 200 nm, such as between approximately 25 nm and approximately 175 nm, between approximately 50 nm and approximately 150 nm, between approximately 75 nm and approximately 125 nm, such as approximately 100 nm.

[0043] Figure 4 This is a flowchart illustrating method 400 for producing membrane stacks 300 and 301. For clarity, please refer to... Figure 1 Cluster tool 100 to describe Figure 4 However, it should be noted that, in addition to Figure 1 Cluster tools other than cluster tool 100 can be used in conjunction with method 400.

[0044] In block 402, substrate 201 is loaded into clustering tool 100 and pre-treated. Substrate 201 may or may not have a thermal oxide layer, such as thermal oxide layer 302, which is formed on substrate 201 before loading into clustering tool 100. In some embodiments, the substrate is loaded into loading platform 140 by one of factory interface robots 120 and subsequently transported by a first transfer robot 132 through a first transfer chamber 124 to a orientation chamber, a pre-cleaning chamber, and / or other first processing chambers 160. As described above, the pressure (P) in the first transfer chamber 124 may be approximately 1 microtor. Therefore, the pressure in clustering tool 100 is maintained under vacuum.

[0045] During pretreatment, substrate 201 may be exposed to a degassing process performed in one of the first processing chambers 160. Depending on the situation, the surface of substrate 201 may be exposed to plasma to pre-clean the surface of substrate 201; this step may be performed before or after the degassing process. For example, the surface of substrate 201 may be pre-cleaned in a pre-cleaning chamber (e.g., bombarded with reactive gas (e.g., H2) or non-reactive gas (e.g., argon, neon, helium) ions and / or gas free radicals (e.g., etching) before being transferred to another first or second processing chamber 160, 170 to deposit the first crystal layer 304). Pre-cleaning the surface of substrate 201 before depositing the first crystal layer 304 can reduce surface defects in the first crystal layer 304 when it is deposited on substrate 201. Other processes that may be performed during block 402 may also include heating, maintaining the transfer temperature of substrate 201, or cooling substrate 201. After the pretreatment of block 402, substrate 201 may be transferred to one or more processing chambers 160, 170 to form various layers of film stack 300 or 301 on the substrate. Processing chambers 160, 170 may include the components shown in processing chamber 200.

[0046] In block 404, a first crystalline layer 304 is formed on substrate 201. In some embodiments, the first crystalline layer 304 is formed on substrate 201 by PVD and / or annealing and oxidation processes. For example, a crystalline thin titanium film can be deposited by PVD at room temperature, followed by exposure of the titanium film to annealing and oxidation processes to form a TiO2 layer.

[0047] In block 406, a bottom electrode layer 306 is formed on a first crystal layer 304 in one of the processing chambers 160 and 170. For example, the bottom electrode layer 306 may be deposited on the first crystal layer 304 via a PVD process performed in a PVD chamber such as processing chamber 200. In some embodiments, the PVD process is performed between about 37°C and about 600°C, such as between about 400°C and about 600°C, and such as at about 500°C. In some embodiments, during the PVD process, a negative bias is applied to the target in the PVD chamber by providing a pulsed or continuous power supply with a power level between about 400 watts and about 1000 watts (such as between about 600 watts and about 800 watts). In some embodiments that may be combined with other embodiments described herein, during the PVD process, the argon flow rate is between about 20 sccm and about 60 sccm, such as between about 30 sccm and about 50 sccm, and the pressure in the PVD chamber is between about 4 mTorr and about 25 mTorr, such as between about 10 mTorr and about 20 mTorr.

[0048] As described above, in some embodiments, the bottom electrode layer 306 is composed of having <111> The oriented Pt formation thus supports the subsequent formation of a highly oriented piezoelectric material layer 312. In a further embodiment, a Pt bottom electrode layer 306 is deposited on a TiO2 first crystal layer 304.

[0049] In block 408, a second crystalline layer 308 is formed on the bottom electrode layer 306. Similar to the first crystalline layer 304, the second crystalline layer 308 can be formed by depositing a thin titanium layer via PVD at room temperature, followed by annealing the titanium layer to form a TiO2 layer. In other examples, the second crystalline layer 308 is formed from different materials and / or by different processes. The second crystalline layer 308 has a uniform thickness between about 0.5 nm and about 5 nm, such as between about 1 nm and about 3 nm, such as about 2 nm, and has uniform thickness. <001> Orientation. A highly uniform thin seed layer with conformal crystal orientation achieves uniformity in subsequent device layers and facilitates the formation of piezoelectric material layers with excellent piezoelectric properties.

[0050] Subsequently, in block 410, template layer 310 may be deposited on the second crystalline layer 308, as shown in film stack 301. <001> An oriented perovskite PZT film is formed by depositing the template layer via a PVD process at a temperature of about 500°C to about 750°C (e.g., about 650°C) and a pressure of about 5 mTorr to about 25 mTorr (e.g., about 18 mTorr to about 20 mTorr). In some embodiments, during the PVD process, a negative bias is applied to the target in the PVD chamber by providing a pulsed or continuous power supply with a power level between about 1000 watts and about 2500 watts, such as between about 1200 watts and about 2000 watts. In some embodiments that may be combined with other embodiments described herein, during the PVD process, the argon flow rate is between about 20 sccm and about 60 sccm, such as between about 30 sccm and about 50 sccm, while the oxygen flow rate is between about 0 sccm and about 20 sccm, such as between about 5 sccm and about 15 sccm.

[0051] The aforementioned deposition process results in a template layer 310 having a uniform thickness ranging from approximately 10 nm to approximately 200 nm, such as between approximately 50 nm and approximately 150 nm, and such as approximately 100 nm. As previously mentioned, the template layer 310 can be formed from a piezoelectric material with properties similar to those of the piezoelectric material layer 312, and therefore, forming a thicker template layer 310 will not adversely affect the piezoelectric properties of the film stack.

[0052] In block 412, the piezoelectric material layer 312 is formed, for example, by a PVD process substantially similar to that used to form the template layer 310. In some embodiments, the target in the PVD chamber is negatively biased by a pulsed or continuous power supply providing a power level between about 1000 watts and about 2500 watts, such as between about 1200 watts and about 2000 watts. In some embodiments that may be combined with other embodiments described herein, during the PVD process, the argon flow rate is between about 20 sccm and about 60 sccm, such as between about 30 sccm and about 50 sccm, while the oxygen flow rate is between about 0 sccm and about 20 sccm, such as between about 5 sccm and about 15 sccm.

[0053] In some embodiments, the piezoelectric material layer 312 is formed directly on the second crystalline layer 308, as shown in film stack 300. In some other embodiments, the piezoelectric material layer 312 is deposited on a template layer 310, as shown in film stack 301. Forming the piezoelectric material layer 312 on the template layer 310 is particularly advantageous when the piezoelectric material layer 312 is formed of a relaxor PT-type material (such as lead PMN-PT or PIN-PMN-PT). In this example, the template layer 310 can be formed with a crystal structure closely matching the crystal structure of the relaxor PT-type material, thereby contributing to… <001> Uniform heteroepitaxial growth of piezoelectric material layer 312 with orientation and excellent piezoelectric properties.

[0054] After the piezoelectric material layer 312 is formed, a top electrode layer 314 is formed on block 414, on film stack 300 or 301. Similar to the bottom electrode layer 306, the top electrode layer 314 may be formed of Pt deposited on the piezoelectric material layer 312 by a PVD process performed at a temperature between about 300°C and about 600°C, such as about 500°C. In some embodiments, during the PVD process, a negative bias is applied to the target in the PVD chamber by providing a pulsed or continuous power supply with a power level between about 400 watts and about 1000 watts (such as between about 600 watts and about 800 watts). In some embodiments that may be combined with other embodiments described herein, during the PVD process, the argon flow rate is between about 20 sccm and about 60 sccm, such as between about 30 sccm and about 50 sccm, and the pressure within the PVD chamber is between about 4 mTorr and about 25 mTorr, such as between about 10 mTorr and about 20 mTorr.

[0055] After blocks 402-414 have been completed and film stacks 300 or 301 have been formed, substrate 201 can be returned to factory interface 104 via one of the first and / or second transfer robots 132, 136 and factory interface robot 120.

[0056] Figure 5 This is a schematic plan view of controller 500, which can provide information to... during the execution of method 400. Figure 1-2 Any of the processing chambers shown in the diagram provides instructions.

[0057] Optional display unit 501 may be coupled to controller 500. Controller 500 includes a processor 504, memory 508, and support circuitry 512 coupled to each other. Controller 500 may be mounted on cluster tool 100, or, in an alternative embodiment, controller 500 may be mounted on... Figure 2 On the processing room or remote equipment (not shown).

[0058] Display unit 501 includes an input control unit, such as a power supply, clock, cache, and input / output (I / O) circuitry, which is coupled to various components of display unit 501 for control purposes. Processor 504 can be any type of general-purpose microprocessor or general-purpose central processing unit (CPU), each of which can be used in industrial environments, such as in programmable logic controllers (PLCs).

[0059] Memory 508 includes at least one non-transitory computer-readable medium and may be one or more readily available memories, such as random access memory (RAM), read-only memory (ROM), or any other form of local or remote digital storage. Memory 508 contains instructions that, when executed by processor 504 (e.g., central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC)), facilitate the processing of... Figure 1-2Operations and processing are performed within any of the processing chambers shown. The instructions in memory 508 are in the form of a program product, such as a program implementing the methods of this disclosure. The program code of the program product may conform to any of a variety of different programming languages. Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory elements within a computer, such as a CD-ROM disc readable by a CD-ROM drive, flash memory, ROM chip, or any type of solid-state non-volatile semiconductor memory), on which information is permanently stored; and (ii) writable storage media (e.g., a floppy disk or hard disk drive in a floppy disk drive, or any type of solid-state random access semiconductor memory), on which modifiable information is stored. Such computer-readable storage media are examples of this disclosure when carrying computer-readable instructions instructing the functions of the methods described herein. The program code in memory 508 may be executed by processor 504 to perform various processing methods in the apparatus, such as performing operations related to... Figure 4 Describe one or more method steps to use Figure 1 The various processing chambers and support components in the clustering tool 100 shown are used to produce membrane stacks 300 or 301.

[0060] In one instance, the controller 500 may be implemented as a program product stored on a computer-readable storage medium (e.g., 508) for use with a computer system (not shown). The program product defines the functions of this disclosure as described herein.

[0061] Figure 6A A comparison of X-ray diffraction (XRD) readings of a PMN-PT piezoelectric material layer 602 formed on a TiOx seed layer and a PMN-PT piezoelectric material layer 604 formed on a PZT template layer, according to an embodiment of the present invention, is shown. Piezoelectric material layers 602 and 604 are examples of the aforementioned piezoelectric material layer 312. Figure 6A The vertical axis represents the relative intensity based on arbitrary units (au), while the horizontal axis represents the 2θ scale in degrees (°). Both XRD readings show strong (001) and (002) peaks, indicating that the piezoelectric material layer has a highly uniform [structure / structure]. <001> Crystal orientation. Furthermore, pyrochlore, lead oxide (PbO), and (111) are suppressed to varying degrees in each of the piezoelectric material layers 602 and 604. Pyrochlore and PbO are parasitic phases that degrade piezoelectric properties and therefore need to be suppressed.

[0062] Figure 6B It shows Figure 6AThe XRD intensity values ​​are represented as the ratio of desired peaks to unwanted peaks. Specifically, bar 610 represents the ratio of (002) peak intensity to (111) peak intensity, while bar 620 represents the ratio of (002) peak intensity to the maximum value of PbO or pyrochlore peak intensity. As shown, piezoelectric layer 602 exhibits a higher (002) / maximum (PbO, pyrochlore) intensity ratio, while piezoelectric layer 604 exhibits a significantly larger (002) / (111) intensity ratio.

[0063] In summary, piezoelectric thin films with highly uniform thickness and crystal orientation can be formed using the methods disclosed herein. In some instances, highly uniform piezoelectric films are promoted by depositing an ultrathin TiOx seed layer with uniform thickness from the center to the edge. In other instances, highly uniform piezoelectric films are promoted by depositing a PZT template layer that closely matches the crystal structure of the subsequently formed piezoelectric film. The improved uniformity of the piezoelectric film results in excellent piezoelectric properties, thereby improving the piezoelectric performance of the resulting device.

[0064] Although the foregoing describes an embodiment of this disclosure, other and more embodiments of this disclosure may be designed without departing from the basic scope of this disclosure, and the scope of this disclosure is defined by the appended claims.

Claims

1. A stack of piezoelectric devices, comprising: The substrate includes a thermal oxide layer; A first crystalline layer is formed on the thermal oxide layer, the first crystalline layer comprising having <001> Oriented titanium oxide (TiOx) layer; A bottom electrode layer is formed on the first type of crystal layer; The second type of crystal layer, the second type of crystal layer comprising having <001> Oriented titanium (Ti) layer, titanium oxide layer, or platinum (Pt) layer, with a thickness between approximately 0.5 nm and approximately 5 nm and a thickness inhomogeneity of + / - 10%; and A piezoelectric material layer is formed on the second type of crystal layer, the piezoelectric material layer comprising a piezoelectric material.

2. The piezoelectric device stack as claimed in claim 1, wherein the piezoelectric material is a relaxor lead titanate (PT) type material.

3. The piezoelectric device stack as claimed in claim 2, wherein the relaxor lead titanate (PT) type material includes lead magnesium niobate-PT (PMN-PT) or lead indium niobate-lead magnesium niobate-PT (PIN-PMN-PT).

4. The piezoelectric device stack as claimed in claim 3, further comprising: A template layer is formed above the second crystal layer and below the piezoelectric material layer, the template layer having a crystal structure substantially the same as that of the piezoelectric material layer.

5. The piezoelectric device stack of claim 4, wherein the template layer comprises lead perovskite zirconate titanate (PZT).

6. The piezoelectric device stack of claim 4, wherein the thickness of the template layer is between about 10 nm and about 200 nm.

7. The piezoelectric device stack as claimed in claim 4, wherein the template layer and the piezoelectric material layer have <001> . orientation.

8. The piezoelectric device stack of claim 1, wherein the first crystalline layer comprises titanium dioxide.

9. The piezoelectric device stack of claim 1, wherein the second crystalline layer comprises titanium dioxide.

10. The piezoelectric device stack of claim 1, wherein the bottom electrode is composed of having <111> Platinum (Pt) is formed with an oriented orientation.

11. A stack of piezoelectric devices, comprising: The substrate includes a thermal oxide layer; A first titanium oxide (TiOx) seed layer is disposed on the thermal oxide layer, wherein the first titanium oxide (TiOx) seed layer has <001> orientation; The first platinum (Pt) electrode layer is disposed on the first TiOx seed crystal layer; A second TiOx seed layer is disposed on the first platinum (Pt) electrode layer, and the second TiOx seed layer has <001> Oriented and having a thickness between approximately 0.5 nm and approximately 5 nm and a thickness non-uniformity of + / - 10%; A perovskite lead zirconate titanate (PZT) template layer is disposed on the second TiOx seed layer; and A relaxor lead titanate (PT) type piezoelectric material layer is disposed on the perovskite lead zirconate titanate (PZT) template layer.

12. The piezoelectric device stack of claim 11, wherein the relaxor lead titanate (PT) type piezoelectric material layer comprises lead magnesium niobate-PT (PMN-PT) or lead indium niobate-lead magnesium niobate-PT (PIN-PMN-PT).

13. A method of forming a stack of piezoelectric devices, comprising: Forming a first crystalline layer on a substrate includes: A titanium (Ti) film was deposited on the substrate via physical vapor deposition (PVD); and The titanium film is exposed to an annealing process to form titanium dioxide (TiO2), and the seed layer has <001> Oriented and having a thickness between approximately 0.5 nm and approximately 5 nm and a thickness non-uniformity of + / - 10%; A bottom electrode layer is formed on the first type of crystal layer; A second crystalline layer is formed on the bottom electrode layer, wherein the second crystalline layer comprises having <001> An oriented titanium (Ti) layer, titanium oxide layer, or platinum (Pt) layer, wherein the second crystalline layer has a thickness between about 0.5 nm and about 5 nm and a thickness inhomogeneity of + / - 10%; and A piezoelectric material layer is formed on the second type of crystal layer, wherein the piezoelectric material is deposited via PVD.

14. The method of claim 13, wherein the first crystal layer has a thickness of about 2 nm.

15. The method of claim 13, wherein the piezoelectric material layer is directly deposited on the second crystalline layer.

16. The method of claim 13, wherein the piezoelectric material layer is deposited on a template layer formed on the second crystalline layer.

17. The method of claim 16, wherein the template layer has a crystal structure substantially the same as the crystal structure of the piezoelectric material layer.

18. The method of claim 17, wherein the template layer comprises lead perovskite zirconate titanate (PZT).

19. The method of claim 16, wherein the piezoelectric material is a relaxor lead titanate (PT) type material.

20. The method of claim 19, wherein the relaxor lead titanate (PT) type material comprises lead magnesium niobate-PT (PMN-PT) or lead indium niobate-lead magnesium niobate-PT (PIN-PMN-PT).

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