Method for improving low-voltage device leakage in metal gate high-voltage device integration process

Abstract

The application provides a method for improving leakage of low-voltage devices in a metal gate high-voltage device integration process, comprising the following steps: S1, providing a substrate, wherein the substrate comprises a low-voltage device area, a medium-voltage device area and a high-voltage device area; S2, etching back active areas of the medium-voltage device area and the low-voltage device area; S3, forming a first gate oxide layer in the medium-voltage device area and the low-voltage device area; S4, removing the first gate oxide layer in the low-voltage device area; and S5, forming a second gate oxide layer in the low-voltage device area. The active areas of the medium-voltage device area and the low-voltage device area are etched back simultaneously, avoiding consumption of isolation components of the low-voltage device area caused by etching back the high-voltage device area and the medium-voltage device area alone, ensuring that the isolation components of the low-voltage device area are higher than the active area, and not increasing the leakage of the low-voltage device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a method for improving leakage current of low-voltage devices in the integration process of metal-gate high-voltage devices. Background Technology

[0002] Organic light-emitting diodes (OLEDs), as the third generation of display technology, are current-injected composite light-emitting devices. Their main advantages include high brightness, high contrast, wide viewing angle, fast response speed, low operating voltage, strong adaptability, high energy conversion efficiency, and simple manufacturing process. Due to the huge technological advantages and application prospects of OLEDs, they have received widespread attention from academia and industry.

[0003] OLEDs are current-driven devices; the current density of an OLED depends on the driving voltage across its terminals, such as... Figure 1 As shown, higher voltage, greater current density, and greater luminous brightness. However, over long-term use, OLED devices age, and the relationship between voltage, current density, and luminous brightness no longer remains constant. The most direct manifestation of OLED aging is an increase in the OLED's turn-on voltage and a decrease in luminous efficiency. To maintain the same luminous brightness, the current flowing through the OLED must be increased; therefore, high-voltage devices need to be integrated into OLEDs to achieve high-current functionality. On the other hand, the internal storage modules of OLEDs are limited, necessitating the use of external memory to store image data. Static RAM (SRAM) is commonly used in OLEDs due to its high read / write speed and ability to retain data without refresh operations while powered on.

[0004] With advancements in logic device technology nodes, OLED technology combining advanced technology nodes is under continuous development. Currently, the most advanced mass production technology combines high-dielectric metal gate technology with low-process-node technology, which can leverage the high performance and low voltage of advanced nodes. This technology requires the integration of low-voltage SRAM and high-voltage driver devices. However, high-voltage devices require thick gate oxide layers, which can affect the implementation of metal gate processes. To ensure compatibility with metal gate processes, the active region of the high-voltage device (HV) is etched back, followed by the growth of thick silicon oxide to ensure the gate oxide layer is as close as possible to the height of the active region, facilitating subsequent process implementation.

[0005] During the active region etch-back process of high-voltage devices, a significant amount of shallow trench isolation (STI) located in the low-voltage device region (LV) is consumed. This results in the active region 200 of low-voltage devices such as active devices (MOS) and passive diodes being higher than the shallow trench isolation 201. Figure 2 As shown, this leads to an increase in leakage current. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a method for improving the leakage of low-voltage devices in the integration process of metal gate high-voltage devices, so as to solve the problem of increased leakage of low-voltage devices in the integration process of metal gate high-voltage devices.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for improving the leakage of low-voltage devices in the integration process of metal gate high-voltage devices, comprising:

[0008] Step S1, providing a substrate, the substrate comprising a low-voltage device region, a medium-voltage device region and a high-voltage device region;

[0009] Step S2, etching back the active region of the medium-voltage device region and the low-voltage device region;

[0010] Step S3, forming a first gate oxide layer in the medium-voltage device region and the low-voltage device region;

[0011] Step S4, removing the first gate oxide layer of the low-voltage device region;

[0012] Step S5, forming a second gate oxide layer in the low-voltage device region.

[0013] Preferably, the etching back is implemented by a dry etching process.

[0014] Preferably, before the etching back is implemented, the medium-voltage device region and the low-voltage device region are doped with a well region.

[0015] Preferably, before Step S2 is implemented, the active region of the high-voltage device region is etched back.

[0016] Preferably, after the active region of the high-voltage device region is etched back, the method further comprises a step of forming a third gate oxide layer in the high-voltage device region.

[0017] Preferably, the first gate oxide layer and the second gate oxide layer are formed by a thermal oxidation growth process.

[0018] Preferably, the first gate oxide layer of the low-voltage device region is removed by a wet etching process.

[0019] Preferably, the etching solution of the wet etching process is diluted hydrofluoric acid.

[0020] Preferably, after Step S5 is completed, the method further comprises a step of forming a pseudo-gate structure in the low-voltage device region, the medium-voltage device region and the high-voltage device region.

[0021] Preferably, after the pseudo-gate structure is formed, the method further comprises a step of removing the pseudo-gate structure to form a high-K dielectric / metal gate structure.

[0022] The method for improving the leakage of low-voltage devices in the metal gate high-voltage device integration process has the beneficial effects that the active regions of the medium-voltage device region and the low-voltage device region are etched back at the same time, the consumption of the isolation components of the low-voltage device region by etching back the high-voltage device region and the medium-voltage device region is avoided, and the isolation components of the low-voltage device region are ensured to be higher than the active region, without increasing the leakage of the low-voltage device. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings also belong to the protection scope of the present application.

[0024] Figure 1 A curve diagram showing the relationship among the voltage, current density and luminous brightness of OLEDs;

[0025] Figure 2 A cross-sectional structure diagram of a low-voltage device region prepared by the prior art metal gate high-voltage device integration process;

[0026] Figure 3 A flowchart of the method for improving the leakage of low-voltage devices in the metal gate high-voltage device integration process provided by the embodiments of the present application;

[0027] Figures 4A-4E A cross-sectional structure diagram of a device formed after each step in the method for improving the leakage of low-voltage devices in the metal gate high-voltage device integration process provided by the embodiments of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below through specific, concrete examples. Those of ordinary skill in the art can easily understand other advantages and effects of the present application from the content disclosed in the present specification. The present application can also be implemented or applied through different specific embodiments, and various modifications or changes can be made to the details in the present specification based on different viewpoints and applications without departing from the spirit of the present application.

[0029] The technical solutions in the present application will be described in detail below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0030] In the description of the present application, it should be explained that the orientation or position relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description and cannot be understood as indicating or implying relative importance.

[0031] In the description of the present application, it should be explained that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements, it can be wireless connection, or wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0032] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0033] In the existing metal gate high voltage device integration process, low voltage devices, medium voltage devices and high voltage devices are integrated in the same chip. Due to the need to grow a relatively thick gate oxide layer in the high voltage device region, the process implementation time is relatively long, in order to avoid the adverse effects on the well doping of the low voltage device region and the medium voltage device region, the active region of the high voltage device region is first etched back, and after the gate oxide layer is grown in the high voltage device region, the active region etching back and the gate oxide layer growth of the medium voltage device region are performed. After multiple active region etching back, too much shallow trench isolation in the low voltage device region is consumed, resulting in that the active region of the low voltage device region is higher than the shallow trench isolation, causing the increase of the leakage of the low voltage device formed subsequently.

[0034] If the formation process of the shallow trench isolation is changed to increase the height of the shallow trench isolation in the low voltage device region, the shallow trench isolation in the low voltage device region needs to be formed separately, resulting in the increase of the integration process time consumption and cost.

[0035] In order to solve this problem, the present application provides a method for improving the leakage of low voltage devices in the metal gate high voltage device integration process.

[0036] Please refer to Figure 3 which shows the flowchart of the method for improving the leakage of low voltage devices in the metal gate high voltage device integration process provided by the embodiments of the present application.

[0037] As Figure 3As shown, the method for improving the leakage of low-voltage devices in the integration process of metal gate high-voltage devices comprises the following steps:

[0038] Step S1, providing a substrate, the substrate comprising a low-voltage device region, a medium-voltage device region and a high-voltage device region;

[0039] Step S2, etching back the active region of the medium-voltage device region and the low-voltage device region;

[0040] Step S3, forming a first gate oxide layer in the medium-voltage device region and the low-voltage device region;

[0041] Step S4, removing the first gate oxide layer of the low-voltage device region;

[0042] Step S5, forming a second gate oxide layer in the low-voltage device region.

[0043] In step S1, as shown, Figure 4A Optionally, the substrate 400 is a silicon substrate, a germanium substrate or a silicon-on-insulator substrate, etc.; or the material of the substrate 400 can also include other materials, such as gallium arsenide and other III-V compound. Those skilled in the art can select the material of the substrate according to the type of the device structure formed on the substrate 400, and thus the type of the substrate 400 should not limit the protection scope of the present application.

[0044] A plurality of isolation components 401 are formed on the substrate 400, and the isolation components 401 divide the substrate 400 into a plurality of regions, including a low-voltage device region, a medium-voltage device region and a high-voltage device region. For simplicity, only the low-voltage device region and the medium-voltage device region are shown in the figure.

[0045] The isolation components 401 can be composed of any insulating material, such as silicon dioxide (SiO2), or a "high-K" dielectric with a high dielectric constant, which can be higher than 3.9, for example. In some cases, the isolation components 401 can be composed of an oxide material. The materials suitable for composing the isolation components 401 can include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), alumina (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials with similar properties that are currently known or later developed.

[0046] For example, the isolation components 401 are formed by a shallow trench isolation (STI) process, which includes but is not limited to shallow trench etching, oxide filling and oxide planarization.

[0047] The shallow trench etching includes, but is not limited to, isolation oxide layer, nitride deposition, shallow trench isolation using a mask, and STI shallow trench etching. The STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. The planarization of the silicon wafer surface can be achieved by various methods. The planarization of the silicon wafer can be achieved by filling the gap using SOG (spin-on-glass), which can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked, the solvent is evaporated, and the silicon dioxide is left in the gap. The entire surface can also be etched back to reduce the thickness of the entire silicon wafer. The planarization can also be effectively achieved by a CMP process (also known as a chemical mechanical polishing process), including but not limited to polishing of the trench oxide (chemical mechanical polishing can be used) and nitride removal.

[0048] In step S2, as shown in FIG. 2, the active regions of the medium-voltage device region and the low-voltage device region are etched back. Figure 4B

[0049] For example, the etching back is implemented by a dry etching process.

[0050] Before the etching back is implemented, the well regions of the medium-voltage device region and the low-voltage device region are doped.

[0051] Before step S2 is implemented, the active region of the high-voltage device region is etched back to form a third gate oxide layer in the high-voltage device region.

[0052] In step S3, as shown in FIG. 3, the first gate oxide layer 402 is formed in the medium-voltage device region and the low-voltage device region. Figure 4C

[0053] For example, the first gate oxide layer 402 is formed by a thermal oxidation growth process.

[0054] In step S4, as shown in FIG. 4, the first gate oxide layer 402 in the low-voltage device region is removed. Figure 4D

[0055] For example, the first gate oxide layer 402 in the low-voltage device region is removed by a wet etching process. The etching solution of the wet etching process is dilute hydrofluoric acid (DHF).

[0056] In step S5, as shown in FIG. 5, the second gate oxide layer 403 is formed in the low-voltage device region. Figure 4E

[0057] For example, the second gate oxide layer 403 is formed by a thermal oxidation growth process.

[0058] ​​​​In the embodiment of the present application, the active regions of the medium-voltage device region and the low-voltage device region are etched back simultaneously, avoiding the consumption of the isolation components of the low-voltage device region by etching back the high-voltage device region and the medium-voltage device region separately, ensuring that the isolation components of the low-voltage device region are higher than the active region, and not increasing the leakage of the low-voltage device. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0059] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The shapes, numbers and proportions of the components when actually implemented can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0060] After step S5, a step of forming a dummy gate structure in the low-voltage device region, the medium-voltage device region and the high-voltage device region is further included.

[0061] After the dummy gate structure is formed, steps of forming a side wall of the dummy gate structure, a metal silicide of the source / drain region, etc. are further included.

[0062] Next, steps of removing the dummy gate structure, forming a high-K dielectric / metal gate structure, etc. are further included.

[0063] For example, the devices formed in the low-voltage device region include conventional MOS tubes, diodes, triodes, devices for electrostatic protection (ESD) circuits, etc.

[0064] The above embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed in the present application should be covered by the claims of the present application.

Claims

1. A method for improving leakage current of low-voltage devices in the integration process of metal-gate high-voltage devices, characterized in that, The method includes: Step S1: Provide a substrate on which an isolation component is formed, the isolation component dividing the substrate into multiple regions including a low-voltage device region, a medium-voltage device region and a high-voltage device region; Step S2: Etch back the active regions of the medium-voltage device region and the low-voltage device region so that the active regions are lower than the isolation components; Step S3: A first gate oxide layer is formed in the medium-voltage device region and the low-voltage device region; Step S4: Remove the first gate oxide layer in the low-voltage device region; Step S5: A second gate oxide layer is formed in the low-voltage device region.

2. The method according to claim 1, characterized in that, The back etching is performed using a dry etching process.

3. The method according to claim 1 or 2, characterized in that, Before performing the back etching, the medium-voltage device region and the low-voltage device region are doped with well regions.

4. The method according to claim 1, characterized in that, Before performing step S2, the active region of the high-voltage device region is etched back.

5. The method according to claim 4, characterized in that, After etching back the active region of the high-voltage device region, the process further includes the step of forming a third gate oxide layer in the high-voltage device region.

6. The method according to claim 1, characterized in that, The first gate oxide layer and the second gate oxide layer are formed by a thermal oxidation growth process.

7. The method according to claim 1, characterized in that, The first gate oxide layer in the low-voltage device region is removed using a wet etching process.

8. The method according to claim 7, characterized in that, The etching solution used in the wet etching process is diluted hydrofluoric acid.

9. The method according to claim 1, characterized in that, After step S5 is completed, the method further includes forming a pseudo-gate structure in the low-voltage device region, the medium-voltage device region, and the high-voltage device region.

10. The method according to claim 9, characterized in that, After forming the pseudo-gate structure, the process further includes the step of removing the pseudo-gate structure to form a high-k dielectric / metal gate structure.

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