Package structure of semiconductor device and packaging method thereof

Abstract

The application provides a packaging structure of a semiconductor device and a packaging method thereof, and is applied to the technical field of semiconductors. The packaging structure is specifically composed of a chip, a plurality of TSV through holes manufactured on the front and back surfaces of the chip, and a protective layer on the back surface of the chip; a plurality of first TSV half through holes are formed on the back surface of the chip corresponding to the active region, and a plurality of second TSV through holes are formed in the chip corresponding to the non-active region, so that the back surface and the front surface of the chip corresponding to the non-active region are communicated through the second TSV through holes; then, a conductive layer is filled in the chip, so as to form a first conductive column and a second conductive column for electrically connecting the electrode arranged on the back surface of the chip corresponding to the active region to the non-active region of the front surface of the chip, thereby realizing the connection of the electrode on the back surface of the chip to the front surface of the chip through the conductive column, without the traditional wire bonding process, so as to reduce the packaging resistance and parasitic inductance of the packaging structure, and improve the heat dissipation capacity of the packaging structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a packaging structure of semiconductor device and a packaging method thereof. BACKGROUND

[0002] With the continuous development of the semiconductor industry, people's requirements for semiconductor are also getting higher and higher, hoping that the electrical performance of semiconductor is getting better and better, and the manufacturing cost is getting smaller and smaller. Among them, power semiconductor is the core device of power electronic energy conversion and circuit control. In recent years, low-voltage MOSFET power devices have rapidly developed towards high power density and miniaturization, and low-voltage MOSFET devices are widely used, but the packaging volume requirement is also getting smaller and smaller. This requirement has accelerated the development of low-voltage MOSFET miniaturization and high-density packaging technology.

[0003] At present, the specific process of the existing miniaturized packaging process of low-voltage MOSFET power devices includes: using a lead frame as a base, then, encapsulating a chip (formed with a low-voltage MOSFET power device) on the lead frame through a conductive film of a material such as tin paste, then, leading out the electrodes of the chip through copper wire solder (wire bonding), and finally, using a plastic packaging material such as epoxy resin to plastic package the outside of the chip and the lead frame structure to isolate the chip from external pollution.

[0004] However, since the existing miniaturized packaging process of low-voltage MOSFET power devices adopts the wire bonding method to lead out the electrodes of the chip, it will inevitably lead to the problem of high packaging resistance and parasitic inductance (or mutual inductance). Moreover, in the prior art, an insulating material is used as a plastic packaging material to isolate the chip from external pollution, and the problem of slow heat conduction of the plastic packaging material will cause poor heat dissipation of the product, thereby failing to meet the heat dissipation requirements of high-power devices. SUMMARY

[0005] The present application aims to provide a packaging structure of semiconductor device and a packaging method thereof, so as to reduce the packaging resistance and parasitic inductance of the packaging structure while improving the heat dissipation capacity of the packaging structure.

[0006] In a first aspect, in order to achieve the above-mentioned and other related purposes, the present application provides a packaging structure of semiconductor device, comprising:

[0007] a plurality of chips, each of the chips comprising an active region and a non-active region, the active region corresponding to the back surface of the chip being provided with a plurality of first TSV semi-holes, and the non-active region corresponding to the chip being provided with a plurality of second TSV holes, so as to communicate the back surface and the front surface of the non-active region corresponding to the chip through the second TSV holes;

[0008] a conductive layer, the conductive layer fills up each of the first TSV semi-via and the second TSV via to form a first conductive column and a second conductive column, and electrically connects the electrode arranged on the back surface of the active region of the chip to the non-active region on the front surface of the chip through the first conductive column and the second conductive column, and the conductive layer extends to cover the entire surface of the back surface of the chip and part of the surface of the front surface of the chip;

[0009] a protective layer, the protective layer is arranged on the surface of the conductive layer covering the back surface of the chip.

[0010] Further, the front surface of the active region of each of the chips can be provided with a source electrode and a gate electrode, and the back surface can be provided with a drain electrode.

[0011] Further, the depth of the first TSV semi-via can be less than half the thickness of the chip.

[0012] Further, the depth of the first TSV semi-via can be less than half the thickness of the chip.

[0013] Further, the material of the protective layer can be an insulating material, which can include silicon nitride or silicon oxide.

[0014] Further, the chip can include a power MOSFET chip.

[0015] Further, the material of the conductive layer can be metal copper.

[0016] In a second aspect, based on the same inventive concept, the present application also provides a packaging method, specifically comprising the following steps:

[0017] providing a plurality of chips, each of the chips comprising an active region and a non-active region, and each of the chips being provided with a source electrode and a gate electrode on the front surface, and a drain electrode on the back surface;

[0018] performing a first etching process on the chips to form a plurality of first TSV semi-vias on the back surface of the chip corresponding to the active region, and a plurality of second TSV vias in the chip corresponding to the non-active region, the second TSV vias connecting the back surface and the front surface of the chip corresponding to the non-active region;

[0019] forming a conductive layer, the conductive layer fills up each of the first TSV semi-via and the second TSV via to form a first conductive column and a second conductive column, and electrically connects the electrode arranged on the back surface of the active region of the chip to the non-active region on the front surface of the chip through the first conductive column and the second conductive column, and the conductive layer extends to cover the entire surface of the back surface of the chip and part of the surface of the front surface of the chip;

[0020] carrying the active region and the second TSV through hole and between other adjacent second TSV through holes, to separate the three electrodes on the front surface of the chip;

[0021] forming a protective layer on the surface of the conductive layer covering the back surface of the chip.

[0022] Further, after the first etching process on the chip and before forming the conductive layer, the packaging method can further include;

[0023] forming a seed layer on the surface of the first TSV half through hole, the second TSV through hole and the front and back surfaces of the chip.

[0024] Further, before the first etching process on the chip, the packaging method can further include a grinding and thinning process on the chip.

[0025] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0026] The present application provides a new type of packaging structure of semiconductor device, which is specifically composed of a chip, a plurality of TSV through holes manufactured on the front and back surfaces of the chip and a protective layer on the back surface of the chip; specifically, a plurality of first TSV half through holes are opened on the back surface of the chip corresponding to the active region, and a plurality of second TSV through holes are opened in the chip corresponding to the non-active region, so as to communicate the back surface and the front surface of the chip corresponding to the non-active region through the second TSV through hole, and then a conductive layer is filled in the first TSV half through hole, the second TSV through hole and the front and back surfaces of the chip, to form a first conductive column and a second conductive column for electrically connecting the electrode arranged on the back surface of the chip corresponding to the active region to the non-active region on the front surface of the chip, so as to realize the electrode on the back surface of the chip being led from the inside of the chip to the front surface of the chip through the conductive column, without the traditional wire bonding process, thereby reducing the packaging resistance and parasitic inductance of the packaging structure and improving the heat dissipation capacity of the packaging structure.

[0027] Further, since there is a groove structure in the active region of the chip in actual application, the chip will warp after being thinned due to the difference in structure between the two surfaces of the chip. In the packaging structure provided by the present application, the back surface of each active region of the chip is provided with a plurality of first TSV half through holes similar to the groove structure, so as to realize the matching of the grooves on the front and back surfaces of the active region of the chip, and thereby improve the problem of process flow and use failure caused by the stress problem of the chip after being thinned due to the difference in structure.

[0028] And, since in the packaging structure provided by the application, thick copper is arranged on both sides of the chip, and the protective layer with isolation effect is pasted on the surface of the conductive layer directly covering the back of the chip, without wrapping the chip with plastic sealing material as in the prior art, thereby improving the heat dissipation capacity of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a structural schematic diagram of a packaging structure of a semiconductor device provided in an embodiment of the application;

[0030] Figure 2 is a flowchart of a packaging method of a packaging structure of a semiconductor device provided in an embodiment of the application;

[0031] Figures 3a to 3e is a structural schematic diagram of a packaging structure of a semiconductor device in a manufacturing process provided in an embodiment of the application;

[0032] In the drawings, the reference signs are as follows:

[0033] 1-chip, A-active region, B-non-active region, 2 / 2c-2f-conductive layer, 3-protective layer, G-gate, D-drain, S-source, 101-first TSV semi-through hole, 102-second TSV through hole, 2a-first conductive column, 2b-second conductive column. DETAILED DESCRIPTION

[0034] As described in the background, at present, the specific process of the existing miniaturized packaging process of low-voltage MOSFET power devices includes: using a lead frame as a base, then, encapsulating the chip (forming a low-voltage MOSFET power device) on the lead frame through a conductive thin film of material such as tin paste, then, leading out the electrodes of the chip through copper wire solder (wire bonding), and finally, encapsulating the outside of the chip and the lead frame with plastic sealing material such as epoxy resin to isolate the chip from external pollution.

[0035] However, since the existing miniaturized packaging process of low-voltage MOSFET power devices leads out the electrodes of the chip by wire bonding, it will inevitably lead to the problem of high packaging resistance and parasitic inductance (or mutual inductance); and in the prior art, it is also necessary to use insulating material as plastic sealing material to isolate the chip from external pollution, and the problem of slow heat conduction of the plastic sealing material will cause the problem of poor heat dissipation of the product, thereby failing to meet the heat dissipation requirements of high-power devices.

[0036] Therefore, the application provides a packaging structure of a semiconductor device and a packaging method thereof, so as to reduce the packaging resistance and parasitic inductance of the packaging structure while improving the heat dissipation capacity of the packaging structure.

[0037] The packaging structure of the semiconductor device and the packaging method thereof provided by the present application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and non-precise in proportion, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0038] Firstly, the packaging structure of the semiconductor device provided by the present application will be introduced below.

[0039] Please refer to Figure 1 , Figure 1 for the structural schematic diagram of the packaging structure of the semiconductor device provided by an embodiment of the present application. As shown in Figure 1 , in the packaging structure provided by the present application, it can include:

[0040] a plurality of chips 1, each of the chip 1 includes an active area A and a non-active area B, the active area A corresponding chip back surface is provided with a plurality of first TSV semi-via, the non-active area B corresponding chip is provided with a plurality of second TSV via, so as to communicate the back surface and the front surface of the non-active area B corresponding chip through the second TSV via;

[0041] a conductive layer 2, the conductive layer 2 fills each of the first TSV semi-via and the second TSV via, to form a first conductive column 2a and a second conductive column 2b, and the electrode provided on the back surface of the active area A corresponding chip is electrically connected to the non-active area B on the front surface of the chip through the first conductive column 2a and the second conductive column 2b, and the conductive layer 2 extends and covers the entire surface of the back surface of the chip 1 and part of the surface of the front surface of the chip 1;

[0042] a protective layer 3, the protective layer 3 is arranged on the surface of the conductive layer covering the back surface of the chip 1.

[0043] Among them, the chip 1 can be a power MOSFET chip, and the front surface of the active area A of each chip 1 can be provided with a source S and a gate G, and the back surface is provided with a drain D. The depth of the first TSV semi-via can be less than the depth of the second TSV via. For example, the depth of the first TSV semi-via can be several microns less than the thickness of the chip 1 to half of the total thickness of the chip 1.

[0044] It can be understood that the depth of the first TSV semi-via provided in the embodiments of the present application can be specifically defined according to the actual thickness of the chip, and the present application only gives a possible case, but it can be determined that the depth of the first TSV semi-via formed in the packaging structure provided by the present application will not exceed the thickness of the chip, that is, the first TSV semi-via is a semi-via, not a full via like the second TSV via.

[0045] Further, the material of the protective layer 3 can be an insulating material for isolating the packaging structure. Exemplarily, the insulating material can be silicon nitride or silicon oxide. The material of the conductive layer 2 (specifically including 2a-2f) can be copper.

[0046] In the embodiments of the present application, a wafer can be provided first, wherein the wafer contains a plurality of chips, and each chip is formed with a power MOSFET chip containing source / drain / gate or other large-current power chip (at this time, the wafer containing a plurality of chips has not been diced). Then, the plurality of chips which have not been diced are subjected to thinning, photolithography and etching processes to form a plurality of first TSV semi-vias on the back surface of the chip corresponding to the active region A, that is, to Figure 1 The structure before 2a in the structure is not filled with the conductive layer; a plurality of second TSV vias are formed in the chip corresponding to the non-active region B, that is, Figure 1 The structure before 2b in the structure is not filled with the conductive layer. Among them, according to Figure 1 It can be known that the second TSV via can communicate the back surface and the front surface of the chip corresponding to the non-active region B, so that after the conductive layer 2 is filled, the drain D provided on the back surface of the chip corresponding to the active region A is electrically connected to the non-active region A on the front surface of the chip through the first conductive column 2a and the second conductive column 2b formed, so that the three electrodes of the chip can be electrically connected to other devices through the front surface of the chip.

[0047] In summary, according to the accompanying Figure 1 It can be known from the packaging structure provided by the present application that the packaging structure provided by the present application can have the following advantages:

[0048] (1) Since in the packaging structure provided by the present application, thick copper is provided on both surfaces of the chip and the protective layer having the functions of protecting the back copper from water vapor oxidation and back insulation is pasted on the surface of the conductive layer directly covering the back surface of the chip, the failure caused by interconnection with external devices can be prevented, and the packaging structure provided by the present application does not need to be wrapped with plastic packaging material like the prior art, thereby improving the heat dissipation capacity of the packaging structure.

[0049] (2) Since the electrodes of the existing MOSFET device are distributed on both sides of the chip, all the electrodes must be led to one side (one side of the chip) during use, and therefore, in the embodiment of the application, the drain electrode on the back side of the chip is led from the inside of the chip to the front side of the chip through the conductive column, without the traditional wire bonding process, thereby reducing the packaging resistance and parasitic inductance of the packaging structure, and completely eliminating the traditional packaging wire bonding.

[0050] (3) Since the current low-voltage MOSFET device has been widely used in SGT MOSFET, the active area of the chip has a groove, and a similar non-through region is also opened on the back side of the chip, and in the packaging structure provided by the application, a TSV through hole is formed in the chip, and then copper is plated in the TSV through hole. Since the thermal conductivity of copper is much higher than that of silicon, the heat generated during the operation of the active area of the chip can be quickly dissipated, which can greatly improve the heat dissipation problem. In addition, another important reason is that the active area of the chip has a groove, and the chip warps due to the difference in structure after being thinned. The similar groove region is opened on the back side to match the front and back grooves, which can improve the stress problem caused by the difference in structure after the chip is thinned, and can also improve the process flow and use failure problem caused by the stress problem.

[0051] Based on the packaging structure of the semiconductor device as described above, as shown in Figure 2 The application also provides a packaging method, which can specifically include the following steps:

[0052] Step S100, providing a plurality of chips, each of which includes an active area and a non-active area, and each of which is provided with a source electrode and a gate electrode on the front side and a drain electrode on the back side.

[0053] Step S200, performing a first etching process on the chip to open a plurality of first TSV half-through holes on the back side of the chip corresponding to the active area, and a plurality of second TSV through holes in the chip corresponding to the non-active area, the second TSV through holes connecting the back side and the front side of the chip corresponding to the non-active area.

[0054] Step S300, forming a conductive layer, the conductive layer filling each of the first TSV half-through holes and the second TSV through holes to form a first conductive column and a second conductive column, so as to electrically connect the drain electrode provided on the back side of the chip corresponding to the active area to the non-active area on the front side of the chip through the first conductive column and the second conductive column, and the conductive layer extends and covers the entire surface of the back side of the chip and the entire surface of the front side of the chip.

[0055] Step S400, a second etching process is performed on the conductive layer covering the front surface of the chip to remove part of the conductive layer while retaining the conductive layer covering the top surface of the source and the gate in the active area and covering the top surface of the second TSV through hole and between other adjacent second TSV through holes in the non-active area, so as to separate the three electrodes on the front surface of the chip.

[0056] Step S500, a protective layer is formed on the surface of the conductive layer covering the back surface of the chip.

[0057] The packaging method of the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and non-precise in scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. Figures 3a to 3e In step S100, referring to FIG. 1, a plurality of chips 1 are provided, each of which includes an active area A and a non-active area B, and each of which is provided with a source S and a gate G on the front surface and a drain D on the back surface.

[0058] Figure 3a In step S200, referring to FIG. 2, a first etching process is performed on the chip 1 to open a plurality of first TSV half through holes 101 on the back surface of the chip corresponding to the active area A, and a plurality of second TSV through holes 102 on the chip corresponding to the non-active area B, the second TSV through holes 102 connecting the back surface and the front surface of the chip corresponding to the non-active area B.

[0059] In step S300, referring to FIG. 3, a conductive layer 2 is formed, which fills each of the first TSV half through holes 101 and the second TSV through holes 102 to form a first conductive column 2a and a second conductive column 2b, so as to electrically connect the drain D provided on the back surface of the chip corresponding to the active area A to the non-active area B on the front surface of the chip through the first conductive column 2a and the second conductive column 2b, and the conductive layer 2 extends and covers the entire surface of the back surface of the chip and the entire surface of the front surface of the chip. For example, the conductive layer 2 is a copper layer with a certain thickness. Figure 3b In step S400, a second etching process is performed on the conductive layer covering the front surface of the chip to remove part of the conductive layer while retaining the conductive layer covering the top surface of the source and the gate in the active area and covering the top surface of the second TSV through hole and between other adjacent second TSV through holes in the non-active area, so as to separate the three electrodes on the front surface of the chip.

[0060] In step S500, a protective layer is formed on the surface of the conductive layer covering the back surface of the chip.

[0061] Figure 3c The packaging method of the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and non-precise in scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0062] ​​In the embodiment, a seed layer (not shown) can be formed on the surfaces of the first TSV semi-via 101, the second TSV via 102, and the front and back surfaces of the chip 1 after step S200 and before step S300, to provide nucleation points, so that the copper layer deposited in step S300 is well adhered to the surfaces of the first TSV semi-via 101, the second TSV via 102, and the front and back surfaces of the chip 1.

[0063] In step S400, referring to FIG. 4, a second etching process is performed on the conductive layer 2 covering the front surface of the chip 1, to remove part of the conductive layer while retaining the conductive layers 2d and 2e covering the top surfaces of the source and gate in the active area A, and the conductive layer 2f covering the top surface of the second TSV via in the non-active area B and between other adjacent second TSV vias, to separate the three electrodes on the front surface of the chip. Figure 3d

[0064] In step S500, referring to FIG. 5, a protective layer 3 is formed on the surface of the conductive layer 2c covering the back surface of the chip 1. Figure 3e

[0065] Since the drawings provided in the embodiment are exemplary drawings, only the packaging process of one chip is shown, and when a plurality of chips are included on a wafer, the plurality of chips can be packaged in batches, and then singulated. Finally, after product FT testing of each packaging structure, the packaging structure is packaged.

[0066] As can be seen from the above, the packaging structure of the semiconductor device is provided, which specifically comprises a chip, a plurality of TSV vias formed on the front and back surfaces of the chip, and a protective layer on the back surface of the chip. Specifically, a plurality of first TSV semi-vias are formed on the back surface of the chip corresponding to the active area, and a plurality of second TSV vias are formed in the chip corresponding to the non-active area, to communicate the back surface and the front surface of the chip corresponding to the non-active area through the second TSV vias. Then, the conductive layer is filled in the first TSV semi-vias, the second TSV vias, and the front and back surfaces of the chip, to form the first and second conductive pillars for electrically connecting the electrode arranged on the back surface of the chip corresponding to the active area to the non-active area on the front surface of the chip, so that the electrode on the back surface of the chip is led to the front surface of the chip through the conductive pillars without the traditional wire bonding process, thereby reducing the packaging resistance and parasitic inductance of the packaging structure, and improving the heat dissipation capacity of the packaging structure.

[0067] ​​Further, since in actual application, the chip active area is provided with a groove structure, after the chip is thinned, warping occurs due to the difference in structure between the two surfaces of the chip. In the packaging structure provided by the application, the back surface of the active area of each chip is provided with a plurality of first TSV semi-holes similar to the groove structure, so that the groove matching of the front and back surfaces of the chip active area is realized, and the problems of process flow and use failure caused by the stress problem of the chip after thinning due to the difference in structure are improved.

[0068] In addition, since in the packaging structure provided by the application, thick copper is provided on both surfaces of the chip, and the protective layer with isolation effect is pasted directly on the surface of the conductive layer covering the back surface of the chip, without wrapping the chip with plastic packaging material as in the prior art, the heat dissipation capacity of the packaging structure is improved.

[0069] In addition, it can be understood that, although the application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the application. For any person skilled in the art, many possible changes and modifications or equivalent embodiments of the above disclosed technical content can be made to the technical solution of the application without departing from the scope of the technical solution of the application. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the application without departing from the content of the technical solution of the application, all still belong to the scope of protection of the technical solution of the application.

[0070] It should also be understood that the application is not limited to the particular methods, compounds, materials, manufacturing techniques, uses and applications described herein, as these can vary. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present application. It must be noted that, as used herein and in the appended claims, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" is a reference to one or more steps and can include sub-steps. All conjunctions used herein are to be understood in the widest sense possible, i.e., conjunctive as well as disjunctive. Thus, for example, "and" should be understood to mean "and / or" unless the context clearly dictates otherwise. Structures described herein are to be understood to refer to functional equivalents as well. Language that could be construed as limiting will be understood to be merely illustrative and not restrictive.

Claims

1. A packaging structure of a semiconductor device, characterized by comprising: The package method comprises the following steps: providing a plurality of chips, each of which comprises an active region and a non-active region, and the front surface of each of the chips is provided with a source electrode and a gate electrode, and the back surface is provided with a drain electrode; performing a first etching process on the chips to form a plurality of first TSV semi-through holes on the back surface of the chip corresponding to the active region, and a plurality of second TSV through holes in the chip corresponding to the non-active region, the second TSV through holes connecting the back surface and the front surface of the chip corresponding to the non-active region; forming a conductive layer, the conductive layer filling each of the first TSV semi-through holes and the second TSV through holes to form first conductive columns and second conductive columns, and electrically connecting the drain electrode provided on the back surface of the chip corresponding to the active region to the non-active region on the front surface of the chip through the first conductive columns and the second conductive columns, and the conductive layer extending and covering the entire surface of the back surface of the chip and part of the surface of the front surface of the chip; 2. The packaging structure of a semiconductor device according to Claim 1, wherein forming a protective layer on the surface of the conductive layer covering the back surface of the chip.

3. The packaging structure of a semiconductor device according to Claim 1, wherein The front surface of the active region of each of the chips is provided with a source electrode and a gate electrode, and the back surface is provided with a drain electrode.

4. The packaging structure of a semiconductor device according to Claim 3, wherein The depth of the first TSV semi-through hole is less than the depth of the second TSV through hole.

5. The packaging structure of a semiconductor device according to Claim 1, wherein The depth of the first TSV semi-through hole is less than half the thickness of the chip.

6. The packaging structure of a semiconductor device according to Claim 1, wherein The material of the protective layer is an insulating material, which comprises silicon nitride or silicon oxide.

7. The packaging structure of a semiconductor device according to Claim 1, wherein The chip comprises a power MOSFET chip.

8. A packaging method for the packaging structure according to any one of claims 1 to 7, characterized by, The material of the conductive layer is metal copper. The package method comprises the following steps: providing a plurality of chips, each of which comprises an active region and a non-active region, and the front surface of each of the chips is provided with a source electrode and a gate electrode, and the back surface is provided with a drain electrode; performing a first etching process on the chips to form a plurality of first TSV semi-through holes on the back surface of the chip corresponding to the active region, and a plurality of second TSV through holes in the chip corresponding to the non-active region, the second TSV through holes connecting the back surface and the front surface of the chip corresponding to the non-active region; forming a conductive layer, the conductive layer filling each of the first TSV semi-through holes and the second TSV through holes to form first conductive columns and second conductive columns, and electrically connecting the drain electrode provided on the back surface of the chip corresponding to the active region to the non-active region on the front surface of the chip through the first conductive columns and the second conductive columns, and the conductive layer extending and covering the entire surface of the back surface of the chip and part of the surface of the front surface of the chip; forming a protective layer on the surface of the conductive layer covering the back surface of the chip.

9. The packaging method of claim 8, wherein, The package method further comprises the following steps after the first etching process is performed on the chips and before the conductive layer is formed: forming a seed layer on the surfaces of the first TSV semi-through holes, the second TSV through holes, and the front and back surfaces of the chips.

10. The packaging method of claim 8, wherein, The package method further comprises a grinding and thinning process on the chips before the first etching process is performed on the chips.

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