Semiconductor structure and method of manufacturing the same
By setting sidewall pads on the substrate sidewalls, the layout area of the pads is increased, which solves the problem of low pad area utilization in traditional packaging forms and achieves a more efficient pad layout, which is suitable for semiconductor structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ICLEAGUE TECH CO LTD
- Filing Date
- 2023-01-29
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional packaging methods cannot meet the requirements of pad layout when chips are miniaturized, resulting in low pad area utilization.
Sidewall pads are provided on the sidewalls of the substrate to increase the layout area of the pads. By arranging pads on both the sidewalls and the top surface of the substrate, a three-dimensional structure is formed.
It improves the area utilization of the pads, alleviates the pad layout problems caused by chip miniaturization, and enhances the flexibility of the pad layout.
Smart Images
Figure CN116207063B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor structure and its manufacturing method. Background Technology
[0002] The electronics and semiconductor industry is developing rapidly. With the popularization of smaller manufacturing processes, chip sizes are getting smaller and smaller. However, the area of the pads (PADs) cannot be reduced much. The size of the pads is about 1,000 times the critical dimension (CD). Traditional two-dimensional packaging can no longer meet the requirements of device interconnect density.
[0003] Traditional packaging typically uses a fan-out or adapter board fan-out approach for soldering, spreading densely packed solder pads to a larger area via interconnects. However, this interconnect method merely redistributes the chip's solder pins; the area occupied by the solder pads themselves remains almost unchanged, which cannot meet the requirements of solder pad layout in chip miniaturization.
[0004] Therefore, improving the utilization rate of pad area and meeting the pad layout requirements when chips are miniaturized are problems that need to be solved at present. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to improve the utilization rate of pad area and meet the requirements of pad layout when chip miniaturization, and to provide a semiconductor structure and its manufacturing method.
[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including at least one die, the top surface of the die having a plurality of conductive connection pads; and sidewall pads disposed on the sidewalls of the substrate and electrically connected to at least a portion of the conductive connection pads.
[0007] To address the aforementioned problems, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: providing an initial semiconductor structure, the initial semiconductor structure including a substrate, the substrate including at least one die, the top surface of the die having a plurality of conductive connection pads, and the top surface of the substrate having a dicing groove region; forming a groove in the dicing groove region; forming an initial conductive structure in the groove; and dicing the initial semiconductor structure into individual semiconductor structures along the dicing groove region, wherein the dicing line passes through the groove, and the portion of the initial conductive structure exposed on the sidewall of the substrate serves as a sidewall pad.
[0008] The above technical solution increases the area of the semiconductor structure that can be laid out with pads by adding sidewall pads and arranging some pads on the sidewall of the substrate. This increases the surface utilization of the semiconductor structure and alleviates the pad layout problem caused by chip miniaturization. Attached Figure Description
[0009] Figure 1 The diagram shown is a side view of an embodiment of the semiconductor structure described in this invention.
[0010] Figure 2 for Figure 1 A cross-sectional view along the AA' direction.
[0011] Figure 3 The diagram shown is a side view of another embodiment of the semiconductor structure described in this invention.
[0012] Figure 4 for Figure 3 A cross-sectional view along the BB' direction.
[0013] Figure 5 The diagram shown is a side view of another embodiment of the semiconductor structure described in this invention.
[0014] Figure 6 for Figure 5 A sectional view along the CC' direction.
[0015] Figure 7 The diagram shown is a flowchart of one embodiment of the method for fabricating the semiconductor structure described in this invention.
[0016] Figures 8A to 8E The diagram shown is a process flow chart of an embodiment of the semiconductor structure fabrication method of the present invention.
[0017] Figures 9A to 9G The diagram shown is a process flow chart of another embodiment of the semiconductor structure fabrication method described in this invention. Detailed Implementation
[0018] The embodiments of the semiconductor structure and its manufacturing method provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0019] Figure 1 The diagram shown is a side view of an embodiment of the semiconductor structure described in this invention. Figure 2 for Figure 1 A sectional view along the AA' direction. (Refer to reference.) Figures 1-2 The semiconductor structure includes a substrate 100 and sidewall pads 110. The substrate 100 includes a die, and a plurality of conductive pads 102 are disposed on the top surface of the die. The sidewall pads 110 are disposed on the sidewalls of the substrate 100 and are electrically connected to at least a portion of the conductive pads 102.
[0020] By adding sidewall pads 110, some pads can be arranged on the sidewalls of the substrate 100. Thus, the pads of the semiconductor structure can be arranged on the top surface and sidewalls of the substrate 100, increasing the area of the semiconductor structure where pads can be arranged from a three-dimensional perspective, improving the surface utilization of the semiconductor structure, alleviating the pad layout problem caused by chip miniaturization, and further improving the flexibility of pad layout.
[0021] As one embodiment, the substrate 100 is monocrystalline silicon. The substrate 100 exposes the surface of the sidewall pads 110. The substrate 100 is electrically connected to an external circuit via the conductive connection pads 102 on top of the die. As one embodiment, the material of the sidewall pads 110 includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0022] As one embodiment, the semiconductor structure further includes a top surface connection pad 111 disposed on the top surface of the substrate 100. The sidewall pads 110 are electrically connected to the conductive connection pads 102 via the top surface connection pads 111, thereby connecting the sidewall pads 110 to the redistribution layer. The redistribution layer is located on the topmost layer of the die and is connected to the pads via the conductive connection pads 102. As one embodiment, the material of the top surface connection pads 111 includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0023] The thickness of the top surface connection line 111 in the first direction D1 is greater than the thickness of the sidewall pad 110 in the second direction D2, where the first direction D1 is perpendicular to the second direction D2 or forms an acute angle with it. As an embodiment, the first direction D1 is perpendicular to the top surface of the substrate 100, and the second direction D2 is parallel to the top surface of the substrate 100. This is due to the inherent characteristics of the process; during conductive layer deposition, the thickness of the conductive layer in the first direction D1 is greater than its thickness in the second direction D2.
[0024] The semiconductor structure further includes planar pads 120, which are disposed on the top surface of the substrate 100 and electrically connected to at least a portion of the conductive pads 102. The planar pads 120 are electrically connected to the chip redistribution layer via the conductive pads 102. As an embodiment, the material of the planar pads 120 includes, but is not limited to, tungsten, metal silicide, copper, and copper-tungsten alloys. By adding sidewall pads 110 to the existing planar pads 120 located on the surface of the substrate 100, some pads can be arranged on the sidewalls of the substrate 100. This allows the pads of the semiconductor structure to be arranged on both the top surface and sidewalls of the substrate 100, increasing the area of the semiconductor structure where pads can be placed from a three-dimensional perspective, improving the surface utilization of the semiconductor structure, alleviating the pad layout problems caused by chip miniaturization, and further improving the flexibility of pad layout.
[0025] An insulating layer 130 is provided on the top surface of the planar pad 120 and the sidewall pad 110, and the insulating layer 130 covers part of the top surface of the planar pad 120 and the entire top surface of the sidewall pad 110. The insulating layer 130 can be a silicon dioxide layer, used to protect the planar pad 120 and the sidewall pad 110 and prevent accidental contact of the circuit.
[0026] Figure 3 The diagram shown is a side view of another embodiment of the semiconductor structure described in this invention. Figure 4 for Figure 3 A sectional view along the BB' direction. (Refer to reference) Figures 3-4 The semiconductor structure includes a substrate 100 and sidewall pads 110. The substrate 100 includes a die, and a plurality of conductive pads 102 are disposed on the top surface of the die. The sidewall pads 110 are disposed on the sidewalls of the substrate 100 and are electrically connected to at least a portion of the conductive pads 102.
[0027] By adding sidewall pads 110, some pads are arranged on the sidewalls of the substrate 100, increasing the area of the semiconductor structure that can be laid out with pads from a three-dimensional perspective, improving the surface utilization of the semiconductor structure, and alleviating the pad layout problem caused by chip miniaturization.
[0028] As one embodiment, the substrate 100 is monocrystalline silicon. The substrate 100 exposes the surface of the sidewall pads 110. The substrate 100 is electrically connected to an external circuit via the conductive connection pads 102 on top of the die. As one embodiment, the material of the sidewall pads 110 includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0029] As one embodiment, the semiconductor structure further includes a top surface connection pad 111 disposed on the top surface of the substrate 100. The sidewall pads 110 are electrically connected to the conductive connection pads 102 via the top surface connection pads 111, thereby connecting the sidewall pads 110 to the redistribution layer. The redistribution layer is located on the topmost layer of the die. As one embodiment, the material of the top surface connection pads 111 includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0030] As one embodiment, in the first direction D1, the sidewall pad 110 does not extend to the top surface connection pad 111, but is connected to the top surface connection pad 111 via a sidewall connection line 112, that is, the semiconductor structure also includes the sidewall connection line 112. Figure 3 The sidewall connection line 112 described herein is shielded by the substrate 100 and is therefore shown as a dashed line. The sidewall connection line 112 is disposed on the sidewall of the substrate 100, and the sidewall pad 110 is connected to the top surface connection pad 111 via the sidewall connection line 112. The width of the sidewall connection line 112 is smaller than the width of the sidewall pad 110 to reduce cost while meeting electrical connection requirements. The surface of the sidewall connection line 112 is covered by a dielectric layer to prevent accidental connection. As one embodiment, the material of the sidewall connection line 112 includes, but is not limited to, tungsten, metal silicide, copper, and copper-tungsten alloys.
[0031] In one embodiment, the sidewall pads 110 are distributed in one or more layers along a first direction D1 on the sidewall of the substrate 100, and the multiple layers of sidewall pads 110 are staggered along the first direction D1, which is perpendicular to the top surface of the substrate 100 or forms an acute angle with the top surface of the substrate 100. In a specific embodiment, the sidewall pads 110 are distributed in three layers along the first direction D1 on the sidewall of the substrate 100, where the first direction D1 is perpendicular to the top surface of the substrate 100. Multiple layers of the sidewall pads 110 can fully utilize the area of the sidewall of the substrate 100 to arrange a larger number of sidewall pads 110 with more reasonable spacing. The sidewall pads 110 located in different layers are connected to the top surface connecting pads 111 through sidewall connecting lines 112 of different lengths, and the sidewall pads 110 located in different layers are not connected to each other.
[0032] The semiconductor structure further includes planar pads 120 disposed on the top surface of the substrate 100 and electrically connected to at least a portion of the conductive connection pads 102. The planar pads 120 are electrically connected to the chip redistribution layer via the conductive connection pads 102. As one embodiment, the material of the planar pads 120 includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0033] An insulating layer 130 is provided on the top surface of the planar pad 120 and the sidewall pad 110, covering part of the top surface of the planar pad 120 and the entire top surface of the sidewall pad 110. The insulating layer 130 can be a silicon dioxide layer, used to protect the planar pad 120 and the sidewall pad 110 and prevent accidental contact of circuits. By adding sidewall pads 110 to the existing planar pads 120 located on the surface of the substrate 100, some pads can be arranged on the sidewalls of the substrate 100. Therefore, the pads of the semiconductor structure can be arranged on the top surface and sidewalls of the substrate 100, increasing the area of the semiconductor structure where pads can be placed from a three-dimensional perspective, improving the surface utilization of the semiconductor structure, alleviating the pad layout problems caused by chip miniaturization, and further improving the flexibility of pad layout.
[0034] Figure 5 The diagram shown is a structural schematic of another embodiment of the semiconductor structure described in this invention. Figure 6 for Figure 5 A sectional view along the CC' direction. (Refer to reference) Figures 5-6 The semiconductor structure includes a substrate 100 and sidewall pads 110. The substrate 100 includes a plurality of stacked dies, and each die has a plurality of conductive pads 102 disposed on its top surface. The sidewall pads 110 are disposed on the sidewalls of the substrate 100 and are electrically connected to at least a portion of the conductive pads 102.
[0035] In this embodiment, the semiconductor structure includes a plurality of bare dies 101, which are stacked along a first direction D1. Adjacent bare dies 101 are electrically connected by conductive connection pads 102 disposed on the upper surface of the lower bare die 101. At least a portion of the edges of the conductive connection pads 102 of each bare die 101 extend beyond the side surface of the bare die 101 to electrically connect to the sidewall pads 110. The first direction D1 is perpendicular to the top surface of the substrate 100 or forms an acute angle with the top surface of the substrate 100. As a specific embodiment, the first direction D1 is perpendicular to the top surface of the substrate 100.
[0036] As one embodiment, the semiconductor structure further includes a top surface connection pad 111 disposed on the top surface of the substrate 100. The sidewall pads 110 are electrically connected to the conductive connection pads 102 via the top surface connection pads 111, thereby connecting the sidewall pads 110 to the redistribution layer. The redistribution layer is located on the topmost layer of the die. As one embodiment, the material of the top surface connection pads 111 includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0037] As one embodiment, the semiconductor structure further includes sidewall interconnects 112 disposed on the sidewall of the substrate 100. The sidewall pads 110 are connected to the top surface pads 111 via the sidewall interconnects 112, and the width of the sidewall interconnects 112 is smaller than the width of the sidewall pads 110. The surface of the sidewall interconnects 112 is covered by the dielectric layer to prevent accidental interconnection. Figure 5 The sidewall connection lines 112 described herein are shielded by the substrate 100 and are therefore shown as dashed lines. The sidewall pads 110 are provided with sidewall connection lines 112 of varying lengths as needed to connect the conductive pads 102 on the surfaces of different layers of the die 101. As one embodiment, the materials of the sidewall connection lines 112 include, but are not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0038] As one embodiment, the sidewall pads 110 are distributed in one or more layers along a first direction D1 on the sidewall of the substrate 100, and the multiple layers of sidewall pads 110 are staggered along the first direction D1, which is perpendicular to the top surface of the substrate 100 or forms an acute angle with the top surface of the substrate 100. Multiple layers of the sidewall pads 110 can fully utilize the area of the sidewall of the substrate 100 to arrange a larger number of sidewall pads 110 with more reasonable spacing. Each layer of sidewall pads 110 can be connected to at least a portion of the conductive pads 102 of the corresponding layer of die 101. By setting sidewall connection lines 112 of different lengths, multiple layers of sidewall pads 110 can achieve electrical connection with different layers of die 101.
[0039] The semiconductor structure further includes planar pads 120 disposed on the top surface of the substrate 100 and electrically connected to at least a portion of the conductive connection pads 102. The planar pads 120 are electrically connected to the chip redistribution layer via the conductive connection pads 102. As one embodiment, the material of the planar pads 120 includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0040] An insulating layer 130 is provided on the top surface of the planar pad 120 and the sidewall pad 110, and the insulating layer 130 covers part of the top surface of the planar pad 120 and the entire top surface of the sidewall pad 110. The insulating layer 130 can be a silicon dioxide layer, used to protect the planar pad 120 and the sidewall pad 110 and prevent accidental contact of the circuit.
[0041] Figure 7The diagram shows a flowchart of an embodiment of the semiconductor structure fabrication method of the present invention, including the following steps: Step S71, providing an initial semiconductor structure, the initial semiconductor structure including a substrate, the substrate including at least one die, the top surface of the die having a plurality of conductive connection pads, and the top surface of the substrate having a dicing groove region; Step S72, forming a groove in the dicing groove region; Step S73, forming an initial conductive structure in the groove; Step S74, dicing the initial semiconductor structure into independent semiconductor structures along the dicing groove region, wherein the dicing line passes through the groove, and the portion of the initial conductive structure exposed on the sidewall of the substrate serves as a sidewall pad.
[0042] Figures 8A to 8E The diagram shown is a process flow chart of an embodiment of the semiconductor structure fabrication method of the present invention.
[0043] Refer to step S71 and Figure 8A An initial semiconductor structure 700 is provided, the initial semiconductor structure 700 including a substrate 100, the substrate 100 including at least one die, the top surface of the die having a plurality of conductive connection pads 102, and the top surface of the substrate 100 having a scribe groove region 701. As an embodiment, the substrate 100 is monocrystalline silicon. The substrate 100 is electrically connected to an external circuit through the conductive connection pads 102 on the top of the die.
[0044] Refer to step S72 and Figure 8B A groove 702 is formed in the dicing groove region 701. As one embodiment, the groove 702 is formed by etching the dicing groove region 701. Refer to step S73 and... Figure 8C In the groove 702 (shown in) Figure 8B An initial conductive structure 710 is formed within it. For example... Figure 8C As shown, in the groove 702 (illustrated in...) Figure 8B Forming an initial conductive structure 710 within the groove 702 further includes the following steps: at least in the groove 702 (shown in...) Figure 8B A conductive layer is formed between the sidewall and the bottom surface, the conductive layer having a U-shaped opening 703, and the groove 702 (shown in...) Figure 8B The thickness of the conductive layer at the bottom is greater than that of the groove 702 (shown in the diagram). Figure 8B The thickness of the conductive layer on the sidewall; in the groove 702 (shown in) Figure 8B In the step of forming the initial conductive structure 710 within the substrate 100, the conductive layer is also formed on the top surface of the substrate 100, and the thickness of the conductive layer on the top surface of the substrate 100 is greater than that of the groove 702 (shown in the diagram). Figure 8B The thickness of the conductive layer on the sidewall; the groove 702 (shown in) Figure 8B The conductive layer on the sidewall, the groove 702 (shown in) Figure 8B The conductive layer on the bottom surface of the substrate 100 and the conductive layer on the top surface of the substrate 100 together constitute the initial conductive structure 710. In some embodiments, chemical vapor deposition, atomic layer deposition, and other processes can be used to deposit conductive layers on the top surface of the substrate 100 and the groove 702 (shown in the figure). Figure 8B A conductive layer is deposited on the sidewalls and bottom surface. The conductive material includes, but is not limited to, tungsten, metal silicide, copper, and copper-tungsten alloys. Due to the inherent characteristics of the process, during metal deposition, the thickness of the conductive layer in the first direction D1 is greater than its thickness in the second direction D2.
[0045] As an example, such as Figures 8D to 8E As shown, in the groove 702 (illustrated in...) Figure 8B After the initial conductive structure 710 is formed within the ) it also includes the following steps:
[0046] like Figure 8D As shown, the conductive layer on the top surface of the substrate 100 is patterned to form a top surface connection pad 111 and a planar pad 120. The initial conductive structure 710 is connected to the top surface connection pad 111, the top surface connection pad 111 is connected to at least a portion of the conductive connection pads 102, and the planar pad 120 is electrically connected to at least a portion of the conductive connection pads 102.
[0047] like Figure 8E As shown, an insulating layer 130 is formed on the top surface of the substrate 100, covering a portion of the top surface of the planar pad 120 and the entire top surface of the top surface connector pad 111. The insulating layer 130 may be a silicon dioxide layer, used to protect the planar pad 120 and the sidewall pad 110, preventing accidental contact. In some embodiments, the method of forming the insulating layer 130 includes: forming an insulating material layer on the top surface of the substrate 100, the insulating material layer covering the top surface connector pad 111 and the planar pad 120, and filling the gaps between the top surface connector pad 111 and the planar pad 120, and between the planar pads 120; patterning the insulating material layer to expose the entire surface of the top surface connector pad 111 and a portion of the surface of the planar pad 120, thus forming the insulating layer 130. Methods for forming the insulating material layer include, but are not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.
[0048] Refer to step S74 and Figure 2 The initial semiconductor structure 700 is cut into individual semiconductor structures along the dicing groove region 701, wherein the dicing line DD' (illustrated in...) Figure 8E ) through the groove 702 (illustrated in Figure 8BThe portion of the initial conductive structure 710 exposed on the sidewall of the substrate 100 serves as a sidewall pad 110. As one embodiment, dicing the initial semiconductor structure 700 into individual semiconductor structures along the dicing groove region 701 further includes the following steps: the dicing line DD' passes through the U-shaped opening 703, and the conductive layer at the bottom of the groove 702 (shown in Figure 8B) is removed. Figure 8B The conductive layer retained on the sidewall serves as the sidewall pad 110.
[0049] After completing the above steps, you will get the following: Figures 1-2 The semiconductor structure shown.
[0050] The above technical solution increases the area of the semiconductor structure that can be laid out with pads by adding sidewall pads 110 and arranging some pads on the sidewall of the substrate 100 from a three-dimensional perspective, thereby improving the surface utilization of the semiconductor structure and alleviating the pad layout problem caused by chip miniaturization.
[0051] The present invention also proposes other embodiments for forming an initial conductive structure 710 within the groove 702 and cutting the initial semiconductor structure 700 into individual semiconductor structures along the dicing groove region 701.
[0052] Figures 9A to 9G The diagram shown is a process flow chart of another embodiment of the semiconductor structure fabrication method described in this invention. Figures 9A to 9E As shown, forming the initial conductive structure 910 within the groove 702 further includes the following steps:
[0053] like Figure 9A As shown, Figure 9A Is Figure 8B Based on the structure shown, a conductive layer 911 is formed, which fills the groove 702 (shown in the diagram). Figure 8B In some embodiments, a conductive layer 911 may be deposited using processes such as chemical vapor deposition or atomic layer deposition to fill the groove 702 (illustrated in...). Figure 8B The conductive layer 911 material includes, but is not limited to, tungsten metal, metal silicide, copper, and copper-tungsten alloy.
[0054] like Figure 9B As shown, thinning the conductive layer 911 forms the first hole 704. Thinning methods include, but are not limited to, etching.
[0055] like Figure 9CAs shown, the first hole 704 is filled with an insulating material 912. The insulating material 912 may be silicon dioxide. In some embodiments, the method for depositing the insulating material 912 includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.
[0056] like Figure 9D As shown, a second hole 705 is formed within the insulating material 912, the bottom of the second hole 705 exposing the conductive layer 911, and the inner diameter of the second hole 705 is smaller than that of the first hole 704 (illustrated in...). Figure 9C ).
[0057] like Figure 9E As shown, in the second hole 705 (illustrated in...) Figure 9D A conductive material 913 is deposited within the conductive layer 911, and the conductive material 913 is connected to the conductive layer 911 to form an initial conductive structure 910. In some embodiments, the conductive material 913 may be deposited using processes such as chemical vapor deposition or atomic layer deposition. The conductive material 913 includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.
[0058] After completing the above steps, you will get the following: Figure 9E The initial conductive structure 910 is shown. An initial conductive structure 910 located on the same plane is formed using the method described above. When multiple layers of the sidewall pads 110 are included (e.g.) Figure 3 As shown), the bottommost initial conductive structure 910 is first formed, and holes are etched between two adjacent initial conductive structures 910, with the bottom surface of the holes higher than the top surface of the conductive structure 910. (Refer to...) Figures 9A to 9E The method shown forms the initial conductive structure of the next lower layer; each initial conductive structure 910 is formed sequentially until the top layer.
[0059] As an example, such as Figures 9F to 9G As shown, after the step of depositing conductive material 913 in the second hole 705, the following steps are also included:
[0060] like Figure 9FAs shown, a top surface connection pad 111 and a planar pad 120 are electrically formed on the top surface of the substrate 100. The conductive material 913 is connected to the top surface connection pad 111, and the top surface connection pad 111 is connected to at least a portion of the conductive connection pads 102. The planar pad 120 is electrically connected to at least a portion of the conductive connection pads 102. In some embodiments, a conductive layer can be formed on the top surface of the substrate 100 using processes such as chemical vapor deposition or atomic layer deposition, and then the conductive layer can be patterned to form the top surface connection pad 111 and the planar pad 120. The materials of the top surface connection pad 111 and the planar pad 120 include, but are not limited to, tungsten, metal silicide, copper, and copper-tungsten alloys.
[0061] like Figure 9G As shown, an insulating layer 130 is deposited on the top surface of the planar pad 120, the insulating layer 130 covering a portion of the top surface of the planar pad 120 and the entire top surface of the top surface bonding pad 111. The material of the insulating layer 130 may be silicon dioxide. In some embodiments, the methods for forming the insulating layer 130 include, but are not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.
[0062] After completing the above steps, you will get the following: Figure 9G The semiconductor structure shown.
[0063] As an example, such as Figure 9G as well as Figure 4 As shown, cutting the initial semiconductor structure 700 into independent semiconductor structures along the dicing groove region 701 further includes the following steps: the cutting line EE' passes through the conductive layer 911 and the insulating material 912 on the side away from the substrate 100 of the conductive material 913, the remaining conductive layer 911 is exposed on the sidewall of the substrate 100 as the sidewall pad 110, and the conductive material 913 serves as the sidewall connection line 112.
[0064] After completing the above steps, you will get the following: Figures 3-4 The semiconductor structure shown.
[0065] Furthermore, when the semiconductor structure is a multilayer stack of the substrate 100, through Figures 9A to 9E The method shown sequentially forms multiple layers of the initial conductive structure 910, and the required length of the sidewall connection line 112 is set according to the distance between the sidewall pad 110 and the conductive connection pads 102 of different layers. After forming multiple layers of the initial conductive structure 910, planar pads 120 and insulating layers 130 are formed sequentially, and the initial semiconductor structure is cut to form an independent semiconductor structure, wherein the cutting line passes through the groove, and the portion of the initial conductive structure exposed on the sidewall of the substrate 100 serves as the sidewall pad, such as... Figures 5-6 As shown.
[0066] The above technical solution increases the area of the semiconductor structure that can be laid out with pads by adding sidewall pads 110 and arranging some pads on the sidewall of the substrate 100 from a three-dimensional perspective, thereby improving the surface utilization of the semiconductor structure and alleviating the pad layout problem caused by chip miniaturization.
[0067] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, The process includes the following steps: providing an initial semiconductor structure, the initial semiconductor structure including a substrate, the substrate including at least one die, the top surface of the die having a plurality of conductive connection pads, the top surface of the substrate having a scribe groove region; forming a groove in the scribe groove region; and forming an initial conductive structure in the groove. The initial semiconductor structure is cut into independent semiconductor structures along the dicing groove region, wherein the dicing line passes through the groove, and the portion of the initial conductive structure exposed on the sidewall of the substrate serves as a sidewall pad. The sidewall pads are distributed in multiple layers on the sidewall of the substrate along a first direction, and the multiple layers of sidewall pads are staggered along the first direction. The sidewall pads located in different layers are not connected to each other. The first direction is perpendicular to the top surface of the substrate or forms an acute angle with the top surface of the substrate. Forming an initial conductive structure within the groove further includes the following steps: A conductive layer is formed, which fills the groove; the conductive layer is then thinned to form a first hole. An insulating material is filled into the first hole; a second hole is formed within the insulating material, the bottom of which exposes the conductive layer, and the inner diameter of the second hole is smaller than that of the first hole; a conductive material is deposited within the second hole, the conductive material being connected to the conductive layer, and the conductive material and the conductive layer together forming the initial conductive structure; Cutting the initial semiconductor structure into independent semiconductor structures along the dicing groove region further includes the following steps: the cutting line passes through the conductive layer and the insulating material on the side away from the bare die, the remaining conductive layer is exposed on the substrate sidewall as the sidewall pad, and the conductive material serves as the sidewall connection line.
2. The method according to claim 1, characterized in that, After forming an initial conductive structure in the groove, the method further includes the following steps: forming a hole between two adjacent initial conductive structures, wherein the bottom surface of the hole is higher than the top surface of the initial conductive structure; and forming an initial conductive structure in the hole. Each initial conductive structure is formed sequentially until the top layer.
3. The method according to claim 1, characterized in that, After the step of depositing conductive material in the second hole, the method further includes the following steps: forming a top surface bonding pad and a planar pad on the top surface of the substrate, wherein the conductive material is connected to the top surface bonding pad, the top surface bonding pad is connected to at least a portion of the conductive bonding pad, and the planar pad is electrically connected to at least a portion of the conductive bonding pad; and forming an insulating layer on the top surface of the substrate, wherein the insulating layer covers a portion of the top surface of the planar pad and the entire top surface of the top surface bonding pad.
4. The method according to claim 1, characterized in that, The substrate includes multiple stacked dies; after forming an initial conductive structure in the groove, the method further includes the following steps: forming a hole between two adjacent initial conductive structures, the bottom surface of the hole being higher than the top surface of the initial conductive structure; forming an initial conductive structure in the hole, and connecting the conductive pads of the corresponding dies to the sidewall connecting lines of different lengths; Each initial conductive structure is formed sequentially until the top layer.
5. A semiconductor structure, formed using the manufacturing method of the semiconductor structure as described in claim 1, characterized in that, include: The substrate includes at least one bare die, and a plurality of conductive connection pads are disposed on the top surface of the bare die; Sidewall pads are disposed on the sidewall of the substrate and are electrically connected to at least a portion of the conductive connection pads; The sidewall pads are distributed in multiple layers on the sidewall of the substrate along the first direction, and the multiple layers of sidewall pads are staggered along the first direction. The sidewall pads located in different layers are not connected to each other. The first direction is perpendicular to the top surface of the substrate or forms an acute angle with the top surface of the substrate.
6. The semiconductor structure according to claim 5, characterized in that, It also includes a top surface connection pad, which is disposed on the top surface of the substrate, and the sidewall pads are electrically connected to the conductive connection pad through the top surface connection pad.
7. The semiconductor structure according to claim 6, characterized in that, The thickness of the top surface connecting line in the first direction is greater than the thickness of the side wall pad in the second direction, and the first direction is perpendicular to the second direction or forms an acute angle with it.
8. The semiconductor structure according to claim 6, characterized in that, It also includes sidewall connection lines, which are disposed on the sidewall of the substrate. The sidewall pads are connected to the top surface pads through the sidewall connection lines, and the width of the sidewall connection lines is smaller than the width of the sidewall pads.
9. The semiconductor structure according to claim 5, characterized in that, The device includes a plurality of said bare dies, which are stacked along a first direction, wherein at least a portion of the conductive pad edge of each said bare die extends beyond the bare die to electrically connect to the sidewall pad, and the first direction is perpendicular to the top surface of the substrate or forms an acute angle with the top surface of the substrate.
10. The semiconductor structure according to claim 5, characterized in that, It also includes planar pads disposed on the top surface of the substrate and electrically connected to at least a portion of the conductive pads.
11. The semiconductor structure according to claim 10, characterized in that, An insulating layer is provided on the top surface of the planar pad and the sidewall pad, and the insulating layer covers part of the top surface of the planar pad and the entire top surface of the sidewall pad.