Electrostatic discharge protection structure

Abstract

The application provides an electrostatic discharge protection structure. In the electrostatic discharge protection structure, a substrate has a first conductive type; a source region and a drain region both have a second conductive type opposite to the first conductive type and are arranged in the substrate at intervals; a gate structure is arranged on the substrate between the source region and the drain region; a first doped region arranged in the substrate away from the gate structure on one side of the drain region has the first conductive type and is arranged in the substrate away from the drain region at intervals, and the first doped region has a doping concentration greater than that of the substrate; the source region and the gate structure are electrically connected to a first potential end in common, and the drain region is electrically connected to a second potential end. The first doped region can reduce the avalanche breakdown voltage of the collector junction of a parasitic NPN transistor of the electrostatic discharge protection structure, and help to reduce the trigger voltage of the electrostatic discharge protection structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an electrostatic discharge protection structure. Background Technology

[0002] In chip design, electrostatic discharge (ESD) protection is crucial to chip reliability. As ESD protection requirements become increasingly stringent, the protective structures on the chip responsible for ESD protection need continuous optimization.

[0003] Figure 1 The structure of an ESD protection network with I / O ports and power clamps is shown. For example... Figure 1 As shown, for the ESD protection structure ESD3, if a GGNMOS (Gate Ground NMOS) device with the same operating voltage, modified from a 5V NMOS, is selected, the trigger voltage of ESD3 and the MOSFET M3 will be the same, causing ESD3 to fail to protect M3. Therefore, a low trigger voltage ESD protection structure is required. Meanwhile, the ESD protection structure ESD5, as a power clamping protection, requires a more compatible ESD protection structure due to cost considerations, but it also needs a low trigger voltage. Furthermore, from the perspective of reducing cost and area, the ESD protection structure needs to have strong robustness. From the perspective of latch-up protection, the ESD protection structure needs to have a high sustaining voltage. Summary of the Invention

[0004] To reduce the trigger voltage of the electrostatic discharge protection structure, this invention provides an electrostatic discharge protection structure.

[0005] The electrostatic discharge protection structure provided by the present invention includes: a substrate having a first conductivity type; a source region and a drain region, each having a second conductivity type opposite to the first conductivity type, disposed at intervals in the substrate; a gate structure disposed on the substrate between the source region and the drain region, wherein the source region and the gate structure are electrically connected to a first potential terminal, and the drain region is electrically connected to a second potential terminal; and a first doped region having a first conductivity type and being floating, disposed in the substrate on the side of the drain region away from the gate structure, and disposed at intervals from the drain region, wherein the doping concentration of the first doped region is greater than the doping concentration of the substrate.

[0006] Optionally, the spacing between the first doped region and the drain region is set according to the magnitude of the trigger voltage required by the electrostatic discharge protection structure.

[0007] Optionally, the electrostatic discharge protection structure comprises a second doped region having the first conductivity type, disposed in the substrate between the gate structure and the source region, the second doped region being floating.

[0008] Optionally, the electrostatic discharge protection structure comprises a SAB layer covering the substrate upper surface of the first doped region and the second doped region.

[0009] Optionally, the electrostatic discharge protection structure comprises a first isolation structure disposed in the substrate between the gate structure and the source region.

[0010] Optionally, the electrostatic discharge protection structure comprises a deep well region having the second conductivity type, formed in the substrate; a top portion of the deep well region forms a first well region having the first conductivity type, the source region, the drain region and the first doped region being formed in a top portion of the first well region, the first doped region having a doping concentration greater than that of the first well region.

[0011] Optionally, a top portion of the first well region forms a first well region pull-out region having the first conductivity type, the first well region pull-out region being located on a side of the source region away from the gate structure, and the first well region pull-out region being electrically connected to the first potential terminal.

[0012] Optionally, the electrostatic discharge protection structure comprises a second well region having the second conductivity type, the second well region being located on a top portion of the deep well region and surrounding the first well region; a top portion of the second well region forms a second well region pull-out region having the second conductivity type, the second well region pull-out region having a doping concentration greater than that of the second well region; the second well region pull-out region being electrically connected to a third potential terminal; an isolation structure is disposed between the first well region pull-out region and the source region; an isolation structure is disposed between the first well region pull-out region and the second well region pull-out region.

[0013] Optionally, the electrostatic discharge protection structure comprises a third well region having the first conductivity type, the third well region having a doping concentration greater than that of the substrate; a top portion of the third well region forms a third well region pull-out region, the third well region pull-out region having the first conductivity type and a doping concentration greater than that of the third well region; the third well region pull-out region being electrically connected to a fourth potential terminal.

[0014] Optionally, the third potential terminal has a different potential from the first potential terminal, the second potential terminal and the fourth potential terminal; and the first potential terminal and the fourth potential terminal have the same or different potentials.

[0015] Optionally, the first potential end is a cathode end, and the second potential end is an anode end, and the potential of the anode end is different from the potential of the cathode end.

[0016] Optionally, the electrostatic discharge protection structure is a GGNMOS.

[0017] Optionally, the electrostatic discharge protection structure comprises at least two interdigital units, each of the interdigital units comprises a gate structure, a source region and a drain region; each two adjacent interdigital units are a pair, the drain regions of the pair of interdigital units are close to each other, the first doped region is located between the two drain regions close to each other, and the pair of interdigital units are axisymmetric about the corresponding first doped region.

[0018] The electrostatic discharge protection structure provided by the application has the first doped region with the first conductive type arranged in the substrate away from the gate structure on one side of the drain region with the second conductive type, the first doped region is arranged apart from the drain region and is arranged as a floating, and the doping concentration of the first doped region is greater than the doping concentration of the substrate. The first doped region arranged can reduce the avalanche breakdown voltage of the collector junction (i.e. the PN junction formed between the drain region and the substrate) of the parasitic NPN transistor in the electrostatic discharge protection structure, and can further reduce the trigger voltage of the electrostatic discharge protection structure, and compared with the conventional electrostatic discharge protection structure (such as the conventional GGNMOS), the ESD robustness of the electrostatic discharge protection structure of the application is higher under the same chip area. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a structure of an ESD protection network clamped at I / O port and power supply.

[0020] Figure 2 It is a sectional view of a GGNMOS device.

[0021] Figure 3 It is Figure 2 It is a schematic view of a GGNMOS device and an equivalent triode circuit inside the device.

[0022] Figure 4 It is a sectional view of a GGNMOS_P+ device.

[0023] Figure 5 It is an IV curve diagram of TLP test of GGNMOS device and GGNMOS_P+ device with the same chip area.

[0024] Figure 6 It is a simulation distribution diagram of current density after the parasitic NPN junction of the GGNMOS device is opened.

[0025] Figure 7The current density simulation distribution diagram after the parasitic NPN junction of the GGNMOS_P+ device is turned on.

[0026] Figure 8 The TLP test IV diagram of the hanging resistance experiment of the GGNMOS device.

[0027] Figure 9 The TLP test IV diagram of the hanging resistance experiment of the GGNMOS_P+ device.

[0028] Figure 10 The cross-sectional schematic diagram of the GGNMOS_P+ device with a P-type ESD injection region.

[0029] Figure 11 The current path schematic diagram after the GGNMOS_P+ device without a P-type ESD injection region is turned on.

[0030] Figure 12 The current path schematic diagram after the GGNMOS_P+ device with a P-type ESD injection region is turned on.

[0031] Figure 13 The IV diagram of the TLP test of different GGNMOS_P+ devices with P-type ESD injection regions introduced under different injection conditions.

[0032] Figure 14 The cross-sectional schematic diagram of the electrostatic discharge protection structure of an embodiment of the present application.

[0033] Figure 15 The cross-sectional schematic diagram of the electrostatic discharge protection structure of another embodiment of the present application.

[0034] The figure mark explanation: 10-substrate; 100-interdigital unit; 101-gate structure; 102-drain region; 103-source region; 104-first doped region; 105-second doped region; 106-first well region leading-out region; 107-second isolation structure; 108-SAB layer; 109-first well region; 110-second well region; 111-second well region leading-out region; 112-third well region; 113-third well region leading-out region; 114-deep well region; 115-first isolation structure; 116-P-type ESD injection region. DETAILED DESCRIPTION

[0035] The GGNMOS device for ESD protection provided by the present application is further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are all in a very simplified form and all use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0036] Figure 2Fig. 1 is a schematic diagram of a cross section of a GGNMOS device. As shown in Fig. 1, in the GGNMOS device, a deep N well is provided in a P-type substrate 10 (P_substrate), a first well region 109 is provided in the deep N well, and at least two interdigital cells 100 are formed in the first well region 109 and above the first well region 109, each of the interdigital cells 100 including a gate structure 101 formed on the substrate 10 and a source region 103 and a drain region 102 formed in the substrate 10 and located on both sides of the gate structure 101, respectively. Figure 2

[0037] Figure 3 Fig. 2 is a schematic diagram of a GGNMOS device and an equivalent triode circuit inside the GGNMOS device. As shown in Fig. 2, the GGNMOS device includes a deep N well provided in a P-type substrate 10 (P_substrate), a first well region 109 provided in the deep N well, and at least two interdigital cells 100 formed in the first well region 109 and above the first well region 109, each of the interdigital cells 100 including a gate structure 101 formed on the substrate 10 and a source region 103 and a drain region 102 formed in the substrate 10 and located on both sides of the gate structure 101, respectively. Figure 2 Figure 2 Figure 3 In the working process of the GGNMOS device, a parasitic NPN transistor Q is formed between the drain region 102, the first well region 109 and the source region 103. When a positive ESD pulse occurs at an anode end, the N+ / Pwell junction between the drain region 102 and the first well region 109 is reverse biased, i.e., the collector junction of Q is reverse biased. When the ESD pulse voltage reaches a certain size, Q is in avalanche breakdown, and an avalanche current is generated. The avalanche current flows to the first well region extraction area 106 through a well resistance R, and the potential at the base b of Q is raised. When the avalanche current continues to increase, the potential at the base b is raised to the positive bias voltage drop of the emitter junction of Q, and the entire Q is in an amplification state, forming an emitter e current, which indicates that the GGNMOS device is triggered. Since the emitter e current in the amplification state of Q is larger than the current flowing out of the first well region extraction area 106 outside the source region, a negative resistance region (snapback region) appears on the current-voltage (IV) curve of the transmission line pulse (TLP) test, and the ESD current at the anode end is mainly discharged by Q.

[0038] As can be seen from the above analysis, Figure 2 the trigger voltage of the GGNMOS device is determined by the avalanche breakdown voltage of the collector junction (i.e., the N+ / Pwell PN junction between the drain region 102 and the first well region 109) of the parasitic NPN transistor Q. Therefore, an improved GGNMOS device reduces the breakdown voltage (BV) of Q by adding a P+ ESD implantation region below the drain region 102, thereby reducing the trigger voltage of the GGNMOS device. In addition, the trigger of the GGNMOS device can also be accelerated by introducing other currents, one of the commonly used methods being coupling a certain voltage on the gate structure 101 of the GGNMOS device to introduce a channel current, which can achieve the purpose of a trigger voltage lower than the breakdown voltage.

[0039] ​​​Figure 4 This is a cross-sectional schematic diagram of a GGNMOS P+ device. (Example) Figure 4 As shown, this GGNMOS_P+ device, compared to Figure 2 The GGNMOS structure shown includes a gate structure 101 formed on the substrate 10, and a source region 103 and a drain region 102 formed in the substrate 10 and located on both sides of the gate structure 101, respectively. However, the difference is that a second doped region 105 (P-type) is formed between the gate structure 101 and the source region 103 of each interdigitated cell 100.

[0040] TLP tests were performed on GGNMOS devices and GGNMOS_P+ devices with the same chip area, and the test results are as follows: Figure 5 As shown, it can be seen that the GGNMOS_P+ device has a higher overcurrent capability compared to the GGNMOS device. Specifically, in the GGNMOS_P+ device, after the parasitic NPN junction in each interdigital cell 100 is turned on, the addition of the second doped region 105 at the source end of the GGNMOS_P+ device causes the electron current path to flow into the first well region 109. Figure 6 The simulation distribution of current density after the parasitic NPN junction of the GGNMOS device is turned on. Figure 7 This is a simulated current density distribution of the parasitic NPN junction in a GGNMOS_P+ device after it is turned on. (Comparison) Figure 6 and Figure 7 It can be seen that the added second doped region 105 in the GGNMOS_P+ device helps to improve the current path distribution and prevents current accumulation near the channel surface. (Refer to...) Figure 5 This allows the secondary breakdown point to occur later, resulting in stronger ESD robustness for GGNMOS_P+ devices. Because the current path in GGNMOS_P+ devices is longer, the sustaining voltage increases, thus giving the GGNMOS_P+ structure the advantage of high sustaining voltage.

[0041] For the GGNMOS_P+ structure, a second doped region 105 is added to the source, forming a channel current blocking structure. Even under ESD pulses, when a certain voltage is coupled to the gate structure 101 through a resistor, no channel current can be formed. Therefore, the GGNMOS_P+ device cannot reduce the trigger voltage by introducing channel current. Figure 8 and Figure 9 These are TLP test IV diagrams of the on-resistance (Res) experiments for GGNMOS and GGNMOS_P+ devices using the same process and chip area. It can be observed that... Figure 8When the hanging resistance Res = 160k ohm, the GGNMOS device can achieve the reduction of the trigger voltage; unlike, Figure 9 The GGNMOS_P+ structure cannot achieve the reduction of the trigger voltage regardless of the hanging resistance.

[0042] Figure 10 The cross-sectional view of the GGNMOS_P+ device with P-type ESD implant region. For reducing the trigger voltage of the GGNMOS_P+ device, one idea is to reduce the breakdown voltage of the drain end, as shown in Figure 10 The commonly used method is to form a P-type ESD implant region 116 (P_ESD_IMP) under the drain region 102. However, in the manufacturing process, the addition of the P-type ESD implant region 116 requires the addition of a P-type ESD implant mask, and due to the common extrusion of the P-type ESD implant region 116 and the second doped region 105 of the source end, the area of the electron current distribution of the parasitic NPN junction after the GGNMOS_P+ device is turned on is very small, and the current concentration effect is easy to occur, which makes the thermal breakdown appear in advance. Figure 11 The current path schematic diagram of the GGNMOS_P+ device without P-type ESD implant region after being turned on. Figure 12 The current path schematic diagram of the GGNMOS_P+ device with P-type ESD implant region after being turned on. From Figure 11 And Figure 12 It can be seen that after the P-type ESD implant region 116 is added, the area where the current of the GGNMOS_P+ device can be distributed is smaller.

[0043] Figure 13 The IV curves of TLP tests of different GGNMOS_P+ devices with P-type ESD implant regions of different implant conditions. Different doses and energies of the P-type ESD implant region are compared, and actual flow verification is performed, as shown in Figure 13 Although the trigger voltage of the GGNMOS_P+ device with the P-type ESD implant region 116 is reduced to a certain extent, compared with the GGNMOS_P+ device without the P-type ESD implant region (No_P_ESD_IMP), the current capacity is seriously degraded. That is, although the trigger voltage of the GGNMOS_P+ device with the P-type ESD implant region 116 can be reduced, it cannot obtain high current capacity and high sustain voltage.

[0044] Therefore, the above-mentioned GGNMOS_P+ device has the advantages of high current capacity and high sustain voltage, but the trigger voltage cannot be reduced by introducing channel current, and the introduction of the P-type ESD implant region 116 will cause the reduction of the current capacity and the increase of the mask plate, and the process manufacturing cost is increased. The existing devices cannot achieve low trigger voltage while obtaining high current capacity and high sustain voltage.

[0045] In order to reduce the trigger voltage of the electrostatic discharge protection structure and maintain high ESD robustness, high over-current capability and high sustain voltage, the following embodiment provides an electrostatic discharge protection structure.

[0046] Figure 14 A cross-sectional view of an electrostatic discharge protection structure according to an embodiment of the present application. Figure 15 A cross-sectional view of an electrostatic discharge protection structure according to another embodiment of the present application. Figure 14 and Figure 15 As shown in the drawings, the electrostatic discharge protection structure includes a substrate 10, a source region 103, a drain region 102, a gate structure 101 and a first doped region 104.

[0047] The substrate 10 has a first conductivity type. The source region 103 and the drain region 102 have a second conductivity type opposite to the first conductivity type and are spaced apart in the substrate 10. The gate structure 101 is disposed on the substrate between the source region 103 and the drain region 102. The first doped region 104 has the first conductivity type, is disposed in the substrate away from the gate structure 101 on a side of the drain region 102 and is spaced apart from the drain region 102. The first doped region 104 has a doping concentration greater than that of the substrate 10. The source region 103 and the gate structure 101 are electrically connected to a first potential end (cathode end, Cathode), the drain region 102 is electrically connected to a second potential end (anode region, Anode), and the first doped region 104 is floating.

[0048] The floating of the first doped region 104 can mean that the first doped region 104 is not connected to any external circuit. In the embodiment, a SAB layer 108 is covered on the upper surface of the substrate of the first doped region 104 to avoid the formation of metal silicide on the upper surface of the substrate of the first doped region 104, thereby avoiding the connection of the first doped region 104 to the external circuit to achieve the floating of the first doped region 104. The arrangement of the first doped region 104 can reduce the avalanche breakdown voltage of the collector junction of the parasitic NPN transistor of the electrostatic discharge protection structure, thereby helping to reduce the trigger voltage of the electrostatic discharge protection structure.

[0049] In the embodiment, the electrostatic discharge protection structure can be a GGNMOS. In another embodiment, the electrostatic discharge protection structure can be a GGPMOS.

[0050] In this embodiment, the first conductivity type is P-type and the second conductivity type is N-type. In another embodiment, the first conductivity type is N-type and the second conductivity type is P-type. The electrostatic discharge protection structure will be described below using the example of the first conductivity type being P-type and the second conductivity type being N-type.

[0051] In one embodiment, such as Figure 14 As shown, the electrostatic discharge protection structure includes a second doped region 105. The second doped region 105 is floating and has a first conductivity type, and is disposed in the substrate between the gate structure 101 and the source region 103. The floating second doped region 105 between the gate structure 101 and the source region 103 improves the current path distribution of the electrostatic discharge protection structure and prevents current accumulation near the channel surface, thus delaying the secondary breakdown point and enhancing the ESD robustness of the electrostatic discharge protection structure. Furthermore, the longer current path when the electrostatic discharge protection structure is turned on due to the second doped region 105 increases the sustaining voltage of the electrostatic discharge protection structure.

[0052] like Figure 14 As shown, the SAB layer 108 can cover the substrate upper surfaces of the first doped region 104 and the second doped region 105, as well as a portion of the substrate upper surfaces of the source region 103 and the drain region 102. When a metal silicide layer (not shown) is formed on the substrate 10, due to the obstruction of the SAB layer 108, the metal silicide forms on the exposed substrate surfaces of the source region 103 and the drain region 102, and the metal silicide does not form on the substrate upper surfaces of the first doped region 104 and the second doped region 105. This prevents conductive structures such as metal silicides located above the substrate 10 from causing the first doped region 104 to conduct with the adjacent drain region 102 and the second doped region 105 to conduct with the adjacent source region 103, thus helping to improve the performance of the electrostatic discharge protection structure. However, it is not limited to this; the SAB layer 108 can also cover other areas of the substrate 10, and a metal silicide layer can be formed on the exposed upper surfaces of the substrate 10 that are not covered by the SAB layer.

[0053] In another embodiment, such as Figure 15As shown, the ESD protection structure can include a first isolation structure 115 in the substrate between the gate structure 101 and the source region 103. The first isolation structure 115 is similar in function to the second doped region 105, and can also improve the current path distribution of the ESD protection structure, and help to avoid the formation of current crowding effect near the surface of the channel region, enhance the ESD robustness of the ESD protection structure and increase the holding voltage of the ESD protection structure. The first isolation structure 115 can be a shallow trench isolation (STI). However, the first isolation structure 115 can also be a junction isolation or a local oxidation of silicon isolation (LOCOS), without being limited thereto.

[0054] As shown in FIG. 1A and FIG. 1B, the ESD protection structure can include a first doped region 104 having a first conductivity type, which is formed in the substrate 10 (P_substrate). The source region 103, the drain region 102 and the second doped region 105 are formed in the top portion of the first doped region 104. The doping concentration of the second doped region 105 is greater than the doping concentration of the first doped region 104. Figure 14 and Figure 15 As shown, the ESD protection structure can include a deep well region 114 (Deep_NWell) having a second conductivity type, which is formed in the substrate 10 (P_substrate). A top portion of the deep well region 114 is formed with a first well region 109 (Pwell) having a first conductivity type, and the source region 103, the drain region 102 and the first doped region 104 are formed in the top portion of the first well region 109. The doping concentration of the first doped region 104 is greater than the doping concentration of the first well region 109. The formation of the first well region 109 helps to improve the isolation protection of the ESD protection structure. The collector junction of the parasitic NPN transistor Q is the PN junction between the drain region 102 and the first well region 109, i.e. the PN junction of N+ / Pwell.

[0055] It should be noted that in other embodiments, for device structures that do not require isolation protection, the source region 103 and the drain region 102 having a second conductivity type, and the first doped region 104 having a first conductivity type can be directly formed in the substrate 10 having a first conductivity type, which helps to simplify the process flow. The collector junction of the parasitic NPN transistor Q is the PN junction between the drain region 102 and the substrate 10, i.e. the PN junction of N+ / P_substrate.

[0056] As shown in FIG. 1A and FIG. 1B, the ESD protection structure can include a first doped region 104 having a first conductivity type, which is formed in the substrate 10 (P_substrate). The source region 103, the drain region 102 and the second doped region 105 are formed in the top portion of the first doped region 104. The doping concentration of the second doped region 105 is greater than the doping concentration of the first doped region 104. Figure 14 and Figure 15 As shown in FIG. 1A and FIG. 1B, the ESD protection structure can include a first doped region 104 having a first conductivity type, which is formed in the substrate 10 (P_substrate). The source region 103, the drain region 102 and the second doped region 105 are formed in the top portion of the first doped region 104. The doping concentration of the second doped region 105 is greater than the doping concentration of the first doped region 104.

[0057] The electrostatic discharge protection structure can further comprise a second well region 110 (Nwell) having the second conductivity type, the second well region 110 being located at the top of the deep well region 114 and surrounding the first well region 109; a top of the second well region 110 is formed with a second well region extraction region 111 having the second conductivity type, the second well region extraction region 111 having a doping concentration greater than that of the second well region 110; and the second well region extraction region 111 is electrically connected to a third potential terminal (ISO).

[0058] The first well region extraction region 106 and the source region 103 are provided with an isolation structure (i.e., a second isolation structure 107); and the first well region extraction region 106 and the second well region extraction region 111 are provided with an isolation structure. Referring to Figure 15 , the second isolation structure 107, the first isolation structure 115, and the isolation structure between the first well region extraction region 106 and the second well region extraction region 111 can have the same depth, so that these isolation structures can be formed by the same process, which helps to save manufacturing costs.

[0059] As shown in Figure 14 and Figure 15 , the electrostatic discharge protection structure can further comprise a third well region 112 (Pwell) having the first conductivity type, the third well region 112 having a doping concentration greater than that of the substrate 10; a top of the third well region 112 is formed with a third well region extraction region 113 having the first conductivity type and a doping concentration greater than that of the third well region 112; and the third well region extraction region 113 is electrically connected to a fourth potential terminal (Psub).

[0060] Referring to Figure 14 and Figure 15 , the first well region 109, the second well region 110, and the third well region 112 can have the same depth. However, the depths of the first well region 109, the second well region 110, and the third well region 112 can be different.

[0061] It should be noted that the spacing k (as shown in Figure 15 ) between the first doped region 104 and the drain region 102 can be adjusted according to the size of the trigger voltage required by the electrostatic discharge protection structure, and the value of K can be different in different processes. Without considering the saving of mask plates, and when the spacing between the first doped region 104 and the drain region 102 is fixed, the first doped region 104 can be doped using a separate mask plate, and by increasing the concentration of the first doped region 104, the trigger voltage of the electrostatic discharge protection structure is lower.

[0062] To save on mask space, the doping depth and concentration of the first doped region 104, the second doped region 105, the first well region lead-out region 106, and the third well region lead-out region 113 can be the same. That is, the first doped region 104, the second doped region 105, the first well region lead-out region 106, and the third well region lead-out region 113 can be obtained using the same mask, which helps to save costs. However, compared with the technical solution of using a separate mask to fabricate the first doped region 104, the adjustable range of the doping concentration of the first doped region 104 is narrower, and it is necessary to adjust the spacing between the first doped region 104 and the drain region 102 to obtain the target trigger voltage.

[0063] In this embodiment, the potential of the third potential terminal is different from the potentials of the first, second, and fourth potential terminals. The potentials of the first and fourth potential terminals may be the same or different. As an example, the first potential terminal is the cathode, the second potential terminal is the anode, and the potential of the anode is different from the potential of the cathode.

[0064] like Figure 14 As shown, in this embodiment, the electrostatic discharge protection structure may include at least two interdigitated units 100. Each interdigitated unit 100 includes a gate structure 101, a source region 103, and a drain region 102. Every two adjacent interdigitated units 100 form a pair. The drain regions 102 of a pair of interdigitated units 100 are close to each other, while the source regions 103 are far apart. The first doped region 104 may be located between two close drain regions 102 and shared by the two interdigitated units 100. Furthermore, the pair of interdigitated units 100 are axially symmetrical about their corresponding first doped regions 104. This helps to reduce the chip area occupied by the electrostatic discharge protection structure. However, this is not a limitation; the drain region 102 of each interdigitated unit 100 may correspond to a single first doped region 104.

[0065] In the electrostatic discharge protection structure, the first doped region 104 with the first conductive type is disposed in the substrate away from the gate structure 101 on the side of the drain region 102 with the second conductive type, the first doped region 104 is disposed apart from the drain region 102, and the doping concentration of the first doped region 104 is greater than the doping concentration of the substrate 10. The first doped region 104 can reduce the avalanche breakdown voltage of the collector junction (i.e. the PN junction formed between the drain region 102 and the substrate 10) of the parasitic NPN transistor in the electrostatic discharge protection structure, thereby reducing the trigger voltage of the electrostatic discharge protection structure. Compared with the conventional electrostatic discharge protection structure (e.g. the conventional GGNMOS), the ESD robustness of the electrostatic discharge protection structure is higher under the same chip area. In addition, the electrostatic discharge protection structure does not need to introduce the P-type ESD implant region 116 in the GGNMOS_P+ device, and the first doped region 104 does not reduce the current capacity of the electrostatic discharge protection structure. Figure 10

[0066] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made according to the technical essence of the present application to the above embodiments, which does not depart from the technical solutions of the present application, belongs to the protection scope of the present application.​

Claims

1. An electrostatic discharge protection structure, characterized by, The static discharge protection structure comprises: a substrate having a first conductivity type; a source region and a drain region each having a second conductivity type opposite to the first conductivity type and spaced apart in the substrate; a gate structure disposed on the substrate between the source region and the drain region; a first doped region having the first conductivity type and disposed in the substrate away from the drain region and spaced apart from the drain region, the first doped region having a doping concentration greater than a doping concentration of the substrate, and a spacing between the first doped region and the drain region being set according to a magnitude of a trigger voltage required by the static discharge protection structure; the source region and the gate structure are electrically connected to a first potential terminal, the drain region is electrically connected to a second potential terminal, and the first doped region is floating.

2. The electrostatic discharge protection structure of claim 1, wherein, a second doped region having the first conductivity type and disposed in the substrate between the gate structure and the source region, the second doped region being floating.

3. The electrostatic discharge protection structure of claim 2, wherein, a SAB layer covering a top surface of the substrate on which the first doped region and the second doped region are disposed.

4. The electrostatic discharge protection structure of claim 1, wherein, a first isolation structure disposed in the substrate between the gate structure and the source region.

5. The electrostatic discharge protection structure of claim 1, wherein, a deep well region having the second conductivity type and formed in the substrate; a top portion of the deep well region forms a first well region having the first conductivity type, and the source region, the drain region and the first doped region are formed in a top portion of the first well region, and the first doped region has a doping concentration greater than a doping concentration of the first well region.

6. The electrostatic discharge protection structure of claim 5, wherein, a first well region pull-out region having the first conductivity type is formed in a top portion of the first well region, the first well region pull-out region is located away from the gate structure on a side of the source region, and the first well region pull-out region is electrically connected to the first potential terminal.

7. The electrostatic discharge protection structure of claim 6, wherein, a second well region having the second conductivity type is formed in a top portion of the deep well region and surrounds the first well region; a second well region pull-out region having the second conductivity type is formed in a top portion of the second well region, and the second well region pull-out region has a doping concentration greater than a doping concentration of the second well region; and the second well region pull-out region is electrically connected to a third potential terminal. an isolation structure is disposed between the first well region pull-out region and the source region, and an isolation structure is disposed between the first well region pull-out region and the second well region pull-out region.

8. The electrostatic discharge protection structure of claim 7, wherein, a third well region having the first conductivity type and having a doping concentration greater than a doping concentration of the substrate; a third well region pull-out region having the first conductivity type and having a doping concentration greater than a doping concentration of the third well region is formed in a top portion of the third well region; and the third well region pull-out region is electrically connected to a fourth potential terminal.

9. The electrostatic discharge protection structure of claim 8, wherein, a potential of the third potential terminal is different from potentials of the first potential terminal, the second potential terminal and the fourth potential terminal, and potentials of the first potential terminal and the fourth potential terminal are the same or different.

10. The electrostatic discharge protection structure of claim 1, wherein, the first potential terminal is a cathode terminal, the second potential terminal is an anode terminal, and a potential of the anode terminal is different from a potential of the cathode terminal.

11. The electrostatic discharge protection structure of claim 1, wherein, the static discharge protection structure is a GGNMOS.

12. The electrostatic discharge protection structure of claim 1, wherein, The application comprises at least two interdigital units, each of which comprises a gate structure, a source region and a drain region; every two adjacent interdigital units form a pair, the drain regions of a pair of interdigital units are close to each other, the first doped region is located between the two drain regions close to each other, and a pair of interdigital units is axially symmetric about the corresponding first doped region.

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