Flyback circuit, auxiliary switch control circuit for flyback circuit, and control method

Abstract

Disclosed are an auxiliary switch control circuit for a flyback circuit, a flyback circuit, and a control method of an auxiliary switch in the flyback circuit. The auxiliary switch is connected in series with a clamping capacitor and then connected in parallel with a primary winding of the flyback circuit. The auxiliary switch control circuit comprises a power supply end for receiving a power supply voltage, a detection end, a ground end, a driving end, and a conduction control circuit. The detection end is coupled to one end of a current detection resistor connected in series with the primary switch, the ground end is coupled to the other end of the current detection resistor, and the driving end is coupled to a control end of the auxiliary switch. The conduction control circuit is coupled to the power supply end and the detection end, generates a conduction control signal based on the logic state of the power supply end voltage and the voltage across the current detection resistor, to control the conduction of the auxiliary switch.

Description

Technical Field

[0001] This invention relates primarily to an electronic circuit, and more particularly, but not exclusively, to a flyback circuit, an auxiliary switching control circuit for the flyback circuit, and a control method thereof. Background Technology

[0002] Figure 1 It is a flyback circuit 100 that uses a traditional RCD absorption circuit. For example... Figure 1 As shown, the RCD snubber circuit 11 includes a snubber resistor Rsn, a clamping capacitor Csn, and a diode Dsn. When the primary-side control signal GP provided by the primary-side control circuit 10 turns off the primary-side switch QP, the leakage inductance Lk of the transformer T charges the clamping capacitor Csn through the diode Dsn, transferring and storing the leakage inductance energy in the clamping capacitor Csn. After the charging process of the clamping capacitor Csn is completed, the energy stored in the clamping capacitor Csn is depleted in the snubber resistor Rsn. Figure 1 The voltage spikes of the flyback circuit 100 can be well suppressed by the RCD absorption circuit 11 shown. However, since the leakage inductance energy is consumed rather than recovered, the efficiency of the flyback circuit 100 is not substantially improved. Summary of the Invention

[0003] To address one or more problems in the prior art, the present invention aims to provide a flyback circuit, an auxiliary switch control circuit for the flyback circuit, and a control method thereof, which can suppress voltage spikes in the flyback circuit and recover energy while avoiding false triggering of the auxiliary switch.

[0004] In one aspect of the invention, an auxiliary switch control circuit for a flyback circuit is provided. The auxiliary switch is connected in series with a clamping capacitor and then in parallel with the primary winding of the flyback circuit. The auxiliary switch control circuit includes: a power supply terminal for receiving an externally input power supply voltage; a detection terminal coupled to one end of a current sensing resistor connected in series with the primary switch; a ground terminal coupled to the other end of the current sensing resistor; a drive terminal coupled to the control terminal of the auxiliary switch; and a conduction control circuit coupled to the power supply terminal and the detection terminal, which generates a conduction control signal based on the logic state of the power supply terminal voltage and the voltage across the current sensing resistor to control the conduction of the auxiliary switch.

[0005] In another aspect of the invention, a flyback circuit is provided, comprising: a transformer having a primary winding and a secondary winding; a primary switch coupled to the primary winding via a current sensing resistor; an energy recovery branch coupled in parallel with the primary winding, the energy recovery branch including an auxiliary switch and a clamping capacitor coupled in series; and an auxiliary switch control circuit as described above.

[0006] In another aspect of the invention, a control method for an auxiliary switch in a flyback circuit is provided. The flyback circuit includes a primary switch coupled to a primary winding via a current-sensing resistor, an energy recovery branch coupled in parallel with the primary winding, and an auxiliary switch control circuit. The energy recovery branch includes a clamping capacitor coupled in series with the auxiliary switch. The control method includes: receiving an externally input supply voltage at the power supply terminal of the auxiliary switch control circuit; coupling the detection terminal of the auxiliary switch control circuit to one end of the current-sensing resistor; coupling the ground terminal of the auxiliary switch control circuit to the other end of the current-sensing resistor; coupling the drive terminal of the auxiliary switch control circuit to the control terminal of the auxiliary switch; and determining whether to turn on the auxiliary switch based on the logic state of the power supply voltage and the voltage across the current-sensing resistor.

[0007] According to embodiments of the present invention, not only can voltage spikes in the flyback circuit be suppressed, but leakage inductance energy of the transformer can also be recovered, while avoiding false triggering of the auxiliary switch due to voltage oscillation when it operates in discontinuous current mode. Attached Figure Description

[0008] To better understand the present invention, it will be described in detail with reference to the following drawings:

[0009] Figure 1 It is a flyback circuit 100 that uses a traditional RCD absorption circuit.

[0010] Figure 2 It is a flyback circuit 200 with an auxiliary switch.

[0011] Figure 3 This is a circuit schematic diagram of a flyback circuit 300 according to an embodiment of the present invention;

[0012] Figure 4 This is a circuit schematic diagram of an auxiliary switch control circuit 31A according to an embodiment of the present invention;

[0013] Figure 5 This is a circuit diagram of a conduction control circuit 310A according to an embodiment of the present invention;

[0014] Figure 6 This is a circuit diagram of the conduction duration control circuit 311A ​​and logic circuit 312A according to an embodiment of the present invention;

[0015] Figure 7 According to an embodiment of the present invention Figure 3 The waveform diagram of the flyback circuit 300 shown is shown.

[0016] Figure 8 This is a circuit schematic diagram of a flyback circuit 300B according to another embodiment of the present invention;

[0017] Figure 9 This is a flowchart of a control method 600 for an auxiliary switch in a flyback circuit according to an embodiment of the present invention;

[0018] Figure 10 This is a flowchart of a method 605 for providing a conduction control signal according to an embodiment of the present invention. Detailed Implementation

[0019] The following will describe in detail specific embodiments of the isolated resonant converter and control method of the present invention. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to implement the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0020] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0021] Figure 2 It is a flyback circuit 200 with an auxiliary switch. For example... Figure 2As shown, the flyback circuit 200 includes two switches: an auxiliary switch QA and a primary-side switch QP. The auxiliary switch QA is coupled to the input power supply to receive the input voltage Vin. The primary-side switch QP is coupled between the auxiliary switch QA and the primary-side reference ground PGND. When the primary-side switch QP is on, the auxiliary switch QA remains off. Current flows through the primary winding Np and the primary-side switch QP to the primary-side reference ground PGND, and energy is stored in the transformer T and the leakage inductance Lk. When the primary-side switch QP is off, the leakage inductance Lk of the transformer T charges the clamping capacitor Csn through the body diode of the auxiliary switch QA, transferring the leakage inductance energy and storing it in the clamping capacitor Csn. Subsequently, the auxiliary switch QA is turned on, and the energy stored in the clamping capacitor Csn is not consumed but recovered through the auxiliary switch QA and the transformer T. The addition of the auxiliary switch QA provides a bidirectional current path, which helps to recover energy. Figure 1 The RCD absorption circuit 11 absorbs the dissipated energy and releases the recovered energy completely to the secondary output, thereby improving the efficiency of the flyback circuit 200.

[0022] Auxiliary switch QA and primary switch QP are controlled by auxiliary switch control circuit 21 and primary control circuit 20, respectively. When operating, auxiliary switch control circuit 21 must first determine whether primary switch QP is in the off state to prevent auxiliary switch QA and primary switch QP from being turned on simultaneously, or to prevent auxiliary switch QA from being mistakenly turned on. This requires additional pins or circuitry (e.g.,...). Figure 2 The SYNC1 synchronization pin of the auxiliary switch control circuit 21 and the SYNC2 synchronization pin of the primary-side control circuit 20 are used to achieve synchronous communication between the auxiliary switch control circuit 21 and the primary-side control circuit 20, and to determine the on / off state of the primary-side switch QP. Undoubtedly, this increases the complexity and cost of the design. Furthermore, the auxiliary switch control circuit 21 and the primary-side control circuit 20 have different power reference grounds; for example, the reference ground pin VSS of the auxiliary switch control circuit 21 is coupled to the common node of the auxiliary switch QA and the primary-side switch QP. In practical applications, after the primary-side switch QP is turned off, the reference ground VSS of the auxiliary switch control circuit 21 may be affected by voltage oscillations in discontinuous current mode, and may even falsely trigger the auxiliary control signal GA of the auxiliary switch QA. Therefore, the auxiliary switch QA is at risk of false turn-on.

[0023] To address the aforementioned problems, the inventors proposed an auxiliary switching control circuit for flyback circuits. Figure 3 This is a circuit schematic diagram of a flyback circuit 300 according to an embodiment of the present invention. Figure 3As shown, the flyback circuit 300 includes a transformer T having a primary winding Np and a secondary winding Ns. An auxiliary switch QA is coupled in series with a clamping capacitor Csn, forming an energy recovery branch. This energy recovery branch is connected in parallel with the primary winding Np of the flyback circuit 300. The primary switch QP is coupled in series with the primary winding Np via a current sensing resistor Rcs. The primary control circuit 10 has a power supply terminal for receiving the primary supply voltage VPR, a drive terminal for providing the primary control signal GP to the primary switch QP, and a ground terminal GND. In one embodiment, the primary supply voltage VPR is the voltage generated by the auxiliary winding of the transformer T charging the capacitor C0 through a diode.

[0024] The auxiliary switch control circuit 31 includes multiple terminals. Figure 3 In the illustrated embodiment, the plurality of terminals include: a power supply terminal VCC that receives an external input power supply voltage, a detection terminal CS coupled to one end of a current sensing resistor Rcs, a ground terminal VSS coupled to the other end of the current sensing resistor Rcs, and a drive terminal DRV coupled to the control terminal of the auxiliary switch QA. The power supply terminal VCC receives the primary-side power supply voltage VPR via diode D0. The auxiliary switch control circuit 31 also includes a conduction control circuit. This conduction control circuit is coupled to the power supply terminal VCC and the detection terminal CS, based on the power supply voltage VPR. CC-SS The logic state and the voltage Vcs across the current sensing resistor Rcs generate a conduction control signal S_ON to control the conduction of the auxiliary switch QA.

[0025] Furthermore, the auxiliary switch control circuit 31 also includes a setting terminal SET and an on-time control circuit. The on-time control circuit is coupled to an external resistor Rset via the setting terminal SET, and the on-time of the auxiliary switch QA is limited by adjusting the resistance value of the external resistor Rset.

[0026] exist Figure 3 In the illustrated embodiment, the auxiliary switch control circuit 31 further includes a voltage adjustment terminal VDD coupled to the external capacitor Cdd and an internal voltage regulator. The internal voltage regulator is coupled between the power supply terminal VCC and the voltage adjustment terminal VDD to adjust the power supply terminal voltage VDD. CC-SS The internal supply voltage Vs is adjusted to a lower value to power other internal circuits in the auxiliary switch control circuit 31, such as logic circuits. In one embodiment, the internal voltage regulator includes a linear regulator.

[0027] Figure 4 This is a circuit diagram of an auxiliary switch control circuit 31A according to an embodiment of the present invention. Figure 4 As shown, the auxiliary switch control circuit 31A includes a conduction control circuit 310, a conduction duration control circuit 311, and a logic circuit 312. Figure 4In the embodiment shown, the conduction control circuit 310 includes a logic state judgment circuit 301, an enable circuit 302, and an enable logic circuit 303.

[0028] The logic state determination circuit 301 is coupled to the power supply terminal VCC to receive the power supply voltage V. CC-SS Where the power supply voltage V CC-SS When the duration of the logic high level exceeds a preset duration Tblank, a trigger signal ST with a first level is provided at the first output terminal. In one embodiment, the first level of the trigger signal ST is a high level.

[0029] The enable circuit 302 is coupled to the detection terminal CS to receive a detection signal V1 representing the voltage Vcs across the current sensing resistor Rcs. Specifically, during the period when the trigger signal ST has a first level, when the detection signal V1 decreases to a first threshold voltage V... TH1-Hys An enable signal SEN with a first level is provided. In one embodiment, a first threshold voltage V... TH1-Hys The voltage is -50mV. In one embodiment, the first level of the enable signal SEN is a high level.

[0030] The enable logic circuit 303 is configured to allow the auxiliary switch QA to detect the supply voltage V during the period when the enable signal SEN has a first level. CC-SS The falling edge of the circuit temporarily activates the circuit.

[0031] In a further embodiment, when the detection signal V1 increases to the second threshold voltage V TH1 At this time, the enable circuit 302 provides a reset signal R0 with an enable window Tw. Wherein, if the power supply voltage V... CC-SS The falling edge occurs within the enable window Tw, controlling the auxiliary switch QA to turn on after the set dead time. If the power supply voltage V CC-SS If the falling edge does not occur within the enable window Tw, the enable signal SEN switches from the first level to the second level, for example, from high level to low level. In one embodiment, the second threshold voltage V TH1 It is -25mV.

[0032] Continue as Figure 4 As shown, the conduction duration control circuit 311 is coupled to the setting terminal SET and the driving terminal DRV. By adjusting the resistance value of the external resistor Rset, it provides a conduction duration control signal S_OFF at the output terminal to limit the conduction duration of the auxiliary switch QA.

[0033] Logic circuit 312 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the output terminal of conduction control circuit 310 to receive the conduction control signal S_ON, and the second input terminal is coupled to the output terminal of conduction duration control circuit 311 to receive the conduction duration control signal S_OFF. Based on the conduction control signal S_ON and the conduction duration control signal S_OFF, logic circuit 312 provides an auxiliary control signal GA at its output terminal to the driver terminal DRV to control the conduction and cutoff of auxiliary switch QA.

[0034] Figure 5 This is a circuit diagram of a conduction control circuit 310A according to an embodiment of the present invention. Figure 5 In the embodiment shown, the conduction control circuit 310A includes a logic state judgment circuit 301A, an enable circuit 302A, and an enable logic circuit 303A.

[0035] like Figure 5 As shown, the logic state determination circuit 301A includes a sampling circuit 314, a comparator CMP1, a leading-edge blanking circuit 315, and a falling-edge triggering circuit 316. Figure 5 In the illustrated embodiment, the sampling circuit 314 has an input terminal and an output terminal, wherein the input terminal is coupled to the power supply terminal VCC, and the output terminal provides the power supply terminal voltage V. CC-SS The non-inverting input of comparator CMP1 receives the supply voltage V. CC-SS The inverting input receives the threshold voltage V. TH Comparator CMP1 will convert the supply voltage V... CC-SS Same threshold voltage V TH In contrast, a comparison signal SP with a pulse width is provided at the output.

[0036] The leading-edge blanking circuit 315 is used to blank the leading edge of the comparison signal SP pulse for a preset duration Tblank, and then provide a trigger signal ST at the output terminal to avoid current spikes caused by the primary-side switch QP being turned on. In one embodiment, in response to a comparison signal SP with a pulse width greater than the preset duration Tblank, the leading-edge blanking circuit 315 outputs the portion of the comparison signal SP after the preset duration Tblank as a high-level trigger signal ST to the turn-on enable circuit 302A; in response to a comparison signal SP with a pulse width not exceeding the preset duration Tblank, the leading-edge blanking circuit 315 prevents the high-level trigger signal ST from being transmitted to the turn-on enable circuit 302A. Figure 5In the illustrated embodiment, the leading-edge blanking circuit 315 includes a delay element DLY1 and a logic AND gate AND1. The delay element DLY1 is coupled to the output of the comparator CMP1 to receive the comparison signal SP and delay the comparison signal SP for a preset duration Tblank. In one embodiment, the preset duration Tblank is 200ns to 250ns. The logic AND gate AND1 has a first input, a second input, and an output, wherein the first input receives the output signal of the delay element DLY1, the second input receives the comparison signal SP, and the output provides a trigger signal ST.

[0037] In addition, the falling edge trigger circuit 316 is coupled to the output of the sampling circuit 314 to trigger the sampling circuit when the power supply voltage V is detected. CC-SS The falling edge trigger signal FL is output when the falling edge is reached.

[0038] Continue as Figure 5 As shown, the enable circuit 302A includes a sampling circuit 324, a set circuit 325, a reset circuit 326, and a trigger circuit 327. The sampling circuit 324 is coupled to the detection terminal CS to provide a detection signal V1 representing the voltage Vcs across the current sensing resistor.

[0039] The set circuit 325 is configured to, during the period when the trigger signal ST has a first level, when the detection signal V1 decreases to a first threshold voltage V TH1-Hys At that time, a set signal S0 with a first level is provided. Figure 5 In the illustrated embodiment, the set circuit 325 includes a comparator CMP2, an AND gate AND2, and a rising-edge flip-flop 328. The inverting input of the comparator CMP2 receives the detection signal V1, and the non-inverting input receives the first threshold voltage V. TH1-Hys The AND gate 2 has a first input, a second input, and an output. The first input receives the trigger signal ST output by the logic state judgment circuit 301A, and the second input receives the output signal of the comparator CMP2. A rising-edge flip-flop 328 is coupled to the output of the AND gate 2, providing a set signal S0 at the output.

[0040] Reset circuit 326 is configured to activate when the detection signal V1 increases to the second threshold voltage V. TH1 At that time, a reset signal R0 with an enable window Tw is provided. Figure 5 In the illustrated embodiment, the reset circuit includes a comparator CMP3, a delay element DLY2, and a rising-edge trigger 329. The non-inverting input of the comparator CMP3 receives the detection signal V1, and the inverting input receives the second threshold voltage V. TH1The output is coupled to the rising edge flip-flop 329 via a delay element DLY2. The delay element DLY2 is used to delay the output of comparator CMP3 by an enable window Tw. The rising edge flip-flop 329 provides a reset signal R0 with the enable window Tw at its output.

[0041] The trigger circuit 327 includes a flip-flop FF1 and an OR gate circuit OR1. The flip-flop FF1 has a set terminal, a reset terminal, and an output terminal, wherein the set terminal is coupled to the output terminal of the set circuit 325 to receive a set signal S0, and the output terminal provides an enable signal SEN. The OR gate circuit OR1 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a reset signal R0, the second input terminal receives a conduction control signal S_ON, and the output terminal is coupled to the reset terminal of the flip-flop FF1.

[0042] The enable logic circuit 303A includes an AND gate circuit AND3. The AND gate circuit AND3 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the output terminal of the logic state determination circuit 301A to receive the falling edge trigger signal FL. The second input terminal is coupled to the output terminal of the enable circuit 302A to receive the enable signal SEN. The output terminal provides a conduction control signal S_ON.

[0043] Figure 6 This is a circuit diagram of a conduction duration control circuit 311A ​​and a logic circuit 312A according to an embodiment of the present invention. The conduction duration control circuit 311A ​​is configured to provide a conduction duration control signal S_OFF to control the conduction duration of the auxiliary switch QA. Figure 6 In the embodiment shown, the conduction duration control circuit 311A ​​includes a first current source 231, a second current source 232, a first capacitor C1, a first transistor M1, a comparator CMP4, and a flip-flop FF2.

[0044] The flip-flop FF2 has a set input, a reset input, and an output, wherein the set input is coupled to... Figure 5 The output terminal of the shown conduction control circuit 310A receives the conduction control signal S_ON, and the reset terminal receives the conduction duration control signal S_OFF.

[0045] The first current source 231 has a first terminal and a second terminal, wherein the first terminal is coupled to the voltage adjustment terminal VDD to receive the internal supply voltage Vs, and the second terminal is coupled to the setting terminal SET, wherein the first current source 231 provides a first current Iset at its second terminal. An external resistor Rset is disposed outside the auxiliary switch control circuit 31A and coupled between the setting terminal SET and the ground terminal VSS. The second current source 232 has a first terminal and a second terminal, wherein the first terminal is coupled to the voltage adjustment terminal VDD to receive the internal supply voltage Vs, and the second current source 232 provides a second current Ich at its second terminal, and the second current Ich is proportional to the first current Iset. The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the second current source 232, and its second terminal is coupled to the ground terminal VSS. The first transistor M1 has a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor C1, the second terminal is coupled to the ground terminal VSS, and the control terminal is coupled to the output terminal of the flip-flop FF2. The comparator CMP4 has an inverting input, a non-inverting input, and an output. The inverting input receives the control voltage V. BG The non-inverting input terminal is coupled to the first terminal of the first capacitor C1, and the comparator CMP4 generates a conduction duration control signal S_OFF at its output terminal.

[0046] Logic circuit 312A includes flip-flop FF3. Flip-flop FF3 has a set terminal, a reset terminal, and an output terminal. The set terminal is coupled to the output terminal of conduction control circuit 310A and receives the conduction control signal S_ON. The reset terminal is coupled to the output terminal of conduction duration control circuit 311A ​​and receives the conduction duration control signal S_OFF. Based on the conduction control signal S_ON and the conduction duration control signal S_OFF, logic circuit 312A provides an auxiliary control signal GA at its output terminal, which is coupled to the drive terminal DRV via a drive circuit (not shown) to control the conduction and cutoff of auxiliary switch QA.

[0047] Figure 7 According to an embodiment of the present invention Figure 3 The waveform diagram of the flyback circuit 300 shown is as follows. Figure 3 As shown, in the flyback circuit 300, when the primary-side switch QP is turned on, the current flowing through the current sensing resistor Rcs gradually increases, providing a voltage Vcs across the current sensing resistor Rcs. Simultaneously, the primary-side supply voltage VPR supplies power to the auxiliary switch control circuit 31 through diode D0, at which point the supply terminal voltage V... CC-SS This is equal to the primary-side supply voltage VPR. During the secondary-side freewheeling period after the primary-side switch QP is turned off, the voltage across the current sensing resistor Rcs will decrease to 0, and the voltage V at the switching node will... SW It will oscillate in discontinuous current mode. Because... Figure 3The ground terminal VSS of the auxiliary switch control circuit 31 is coupled to the switching node via the current sensing resistor Rcs. The voltage at the ground terminal VSS will change with the voltage at the switching node V. SW The voltage V at the power supply terminal changes accordingly. CC-SS It will also oscillate with the voltage Vsw at the switching node.

[0048] It is important to note that, in Figure 7 In the waveforms shown, the waveform of Vsw is plotted with the primary-side reference ground of the flyback circuit 300 as the reference ground potential. Supply terminal voltage V CC-SS The waveforms of the detection signal V1 and the waveform of the auxiliary switch control circuit 31 are plotted with reference ground VSS as the reference potential.

[0049] like Figure 7 As shown, at time t1, the voltage V at the power supply terminal is... CC-SS The voltage is equal to the primary-side supply voltage VPR, and the comparison signal SP switches from a low level to a high level. At time t2, the leading edge of the comparison signal SP is blanked for a preset duration Tblank, and then the trigger signal ST changes from a low level to a high level to avoid current spikes caused by the primary-side switch QP turning on.

[0050] At time t3, while the trigger signal ST remains high, the detection signal V1 decreases to the first threshold voltage V. TH1-Hys The enable signal SEN switches from low to high, allowing the auxiliary switch QA to operate at the power supply voltage V. CC-SS The falling edge of the circuit temporarily activates the circuit.

[0051] exist Figure 7 In the embodiment shown, the power supply voltage V CC-SS The falling edge of the signal arrives at time t4, the auxiliary control signal GA goes high, the auxiliary switch QA is turned on, and the enable signal SEN is reset to low. Furthermore, at time t4, the detection signal V1 increases to the second threshold voltage V. TH1 The reset signal R0 goes high and then returns to low after the enable window Tw is opened.

[0052] At time t5, the conduction duration of auxiliary switch QA reaches the conduction duration set by the conduction duration control circuit, and auxiliary switch QA is turned off.

[0053] At time t6, although the trigger signal ST goes high again, the detection signal V1 remains at 0. Therefore, despite the power supply voltage V... CC-SSThe falling edge of the signal arrives at time t7. The enable signal SEN remains low, the auxiliary control signal GA is not triggered, and the auxiliary switch QA remains off, avoiding false triggering caused by the oscillation of the switch node voltage Vsw during discontinuous current mode. At time t8, the primary-side switch QP is turned on again, entering the next working cycle. The above process is repeated continuously.

[0054] Figure 8 This is a circuit schematic diagram of a flyback circuit 300B according to another embodiment of the present invention. Figure 3 Compared to the flyback circuit 300, the difference is that... Figure 8 In the flyback circuit 300B shown, the connection between the auxiliary switch control circuit 31B and the current sensing resistor Rcs is slightly different. Figure 8 In the illustrated embodiment, the ground terminal VSS of the auxiliary switch control circuit 31B is directly coupled to the common node of the auxiliary switch QA and the primary switch QP, and the detection terminal CS is coupled to the end of the current sensing resistor Rcs connected to the primary winding. Figure 8 The embodiment shown is based on the power supply voltage V. CC-SS The logic state and the voltage V across the current sensing resistor Rcs CS Similarly, it can determine whether to turn on the auxiliary switch QA.

[0055] Figure 9 This is a flowchart of a control method 600 for an auxiliary switch in a flyback circuit according to an embodiment of the present invention. The flyback circuit includes a primary-side switch coupled to the primary winding via a current-sensing resistor, an energy recovery branch coupled in parallel with the primary winding, and an auxiliary switch control circuit, wherein the energy recovery branch includes a clamping capacitor coupled in series with the auxiliary switch. Figure 9 As shown, the control method 600 includes steps 601 to 605.

[0056] In step 601, the power supply terminal of the auxiliary switch control circuit receives the externally input power supply voltage. In one embodiment, the power supply terminal receives the primary-side power supply voltage of the primary-side control circuit via a diode.

[0057] In step 602, the detection terminal of the auxiliary switch control circuit is coupled to one end of the current sensing resistor.

[0058] In step 603, the ground terminal of the auxiliary switch control circuit is coupled to the other end of the current sensing resistor. It should be noted that the ground terminal of the auxiliary switch control circuit is different from the primary reference ground of the flyback circuit.

[0059] In step 604, the drive terminal of the auxiliary switch control circuit is coupled to the control terminal of the auxiliary switch.

[0060] In step 605, a conduction control signal is generated based on the logic state of the power supply voltage and the voltage across the current sensing resistor to determine whether to turn on the auxiliary switch.

[0061] Furthermore, in one embodiment, the control method 600 further includes step 606. In step 606, the setting terminal of the auxiliary switch control circuit is coupled to an external resistor, and a conduction duration control signal is provided based on the resistance value of the external resistor to control the conduction duration of the auxiliary switch. In another embodiment, the auxiliary switch can be turned off in other ways.

[0062] Figure 10 This is a flowchart of a method 605 for providing a conduction control signal according to an embodiment of the present invention. Figure 10 In the illustrated embodiment, the method 605 for providing the conduction control signal includes steps 6051 to 6055.

[0063] In step 6051, the logic state of the power supply voltage is detected.

[0064] In step 6052, when the duration of the power supply voltage being at a logic high level exceeds a preset duration, a trigger signal with a first level is provided.

[0065] In step 6053, a detection signal representing the voltage across the current sensing resistor is provided.

[0066] In step 6054, during the period when the trigger signal has a first level, when the detection signal is detected to decrease to a first threshold voltage, an enable signal with a first level is provided.

[0067] In step 6055, during the period when the enable signal has a first level, the auxiliary switch is allowed to turn on temporarily when the falling edge of the power supply voltage arrives.

[0068] In a further embodiment, method 605 further includes steps 6056 and 6067.

[0069] In step 6056, when the detection signal increases to the second threshold voltage, a reset signal with an enable window is provided. In one embodiment, both the first threshold voltage and the second threshold voltage are threshold voltages less than 0 and close to 0.

[0070] In step 6057, in response to the falling edge of the power supply voltage within the enable window, the auxiliary switch is turned on after a dead time delay. If the falling edge of the power supply voltage does not appear within the enable window, the enable signal switches from the first level to the second level.

[0071] Note that in the flowchart described above, the functions marked in the boxes can also be arranged differently. Figure 9 or Figure 10The sequence shown occurs. For example, two consecutively represented boxes can actually be executed in essentially parallel order, and they can sometimes be executed in reverse order, depending on the specific function involved.

[0072] In the specification, terms such as "first" and "second" may be used merely to distinguish one entity or action from another, and do not necessarily imply any relationship or order between these entities or actions. Numerical orders such as "first," "second," and "third" refer only to different individuals among a plurality and do not imply any order or sequence unless specifically defined in the language of the claims. The order of the text in any claim does not imply that the processing steps must be performed in a provisional or logical order according to such order, unless specifically specified in the language of the claims. These processing steps may be interchanged in any order without departing from the scope of the invention, provided that such interchange does not contradict the language of the claims and does not result in logical absurdity.

[0073] The specific embodiments described above are merely illustrative of the invention and are not exhaustive, nor are they intended to limit the scope of the invention. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of elements in the embodiments can be understood by those skilled in the art. Other variations and modifications to the embodiments disclosed in this invention do not depart from the spirit and scope of protection of this invention.

Claims

1. An auxiliary switch control circuit for a flyback circuit, the auxiliary switch being coupled in series with a clamping capacitor and in parallel with a primary winding of the flyback circuit, the auxiliary switch control circuit comprising: a supply terminal for receiving an externally input supply voltage; a detection terminal coupled to one end of a current detection resistor coupled in series with the primary switch; a ground terminal coupled to the other end of the current detection resistor; a drive terminal coupled to a control terminal of the auxiliary switch; and a turn-on control circuit coupled to the supply terminal and the detection terminal for generating a turn-on control signal to control the turn-on of the auxiliary switch based on a logic state of the supply terminal voltage and a voltage across the current detection resistor, wherein the turn-on control circuit comprises: a logic state determining circuit coupled to the supply terminal for receiving the supply terminal voltage, wherein a trigger signal having a first level is provided when the supply terminal voltage is at a logic high level for more than a predetermined time duration; a turn-on enabling circuit coupled to the detection terminal for receiving a detection signal representing the voltage across the current detection resistor, wherein an enabling signal having the first level is provided when the detection signal decreases to a first threshold voltage during the trigger signal having the first level; and an enabling logic circuit for allowing the turn-on of the auxiliary switch at a falling edge of the supply terminal voltage during the enabling signal having the first level.

2. The auxiliary switch control circuit of claim 1, wherein the turn-on enabling circuit provides a reset signal having a turn-on enabling window when the detection signal increases to a second threshold voltage, wherein: if the falling edge of the supply terminal voltage occurs within the turn-on enabling window, the auxiliary switch is controlled to turn on after a dead time; and if the falling edge of the supply terminal voltage does not occur within the turn-on enabling window, the enabling signal is reset from the first level to a second level.

3. The auxiliary switch control circuit of claim 2, wherein the first threshold voltage is less than the second threshold voltage, and the second threshold voltage is a threshold voltage less than and close to 0.

4. The auxiliary switch control circuit of claim 2, wherein the turn-on enabling circuit comprises: a first comparison circuit for comparing the detection signal with the first threshold voltage to generate a first comparison signal; an AND gate circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the trigger signal and the second input terminal receives the first comparison signal; a second comparison circuit for comparing the detection signal with the second threshold voltage to generate a second comparison signal; a delay element for delaying the second comparison signal to provide the reset signal at the output terminal; and a flip-flop having a set terminal, a reset terminal and an output terminal, wherein the set terminal is coupled to the output terminal of the AND gate circuit, the reset terminal receives the reset signal, and the output terminal provides the enabling signal.

5. The auxiliary switch control circuit of claim 1, further comprising a setting terminal and a turn-on duration control circuit coupled to an external resistor via the setting terminal for limiting the turn-on duration of the auxiliary switch by adjusting a resistance value of the external resistor.

6. A flyback circuit comprising: a transformer having a primary winding and a secondary winding; a primary switch coupled to the primary winding via a current detection resistor; and an auxiliary switch control circuit according to any one of claims 1 to 5. ​ ​ an energy recovery branch coupled in parallel with the primary winding, the energy recovery branch comprising a clamping capacitor and an auxiliary switch coupled in series; and the auxiliary switch control circuit of any one of claims 1 to 5.

7. A control method for an auxiliary switch in a flyback circuit, the flyback circuit comprising a primary switch coupled to a primary winding via a current sensing resistor, an energy recovery branch coupled in parallel with the primary winding and an auxiliary switch control circuit, wherein the energy recovery branch comprises a clamping capacitor coupled in series with the auxiliary switch, the control method comprising: receiving an externally input supply voltage at a supply terminal of the auxiliary switch control circuit; coupling a detection terminal of the auxiliary switch control circuit to one end of the current sensing resistor; coupling a ground terminal of the auxiliary switch control circuit to the other end of the current sensing resistor; coupling a drive terminal of the auxiliary switch control circuit to a control terminal of the auxiliary switch; and determining whether to turn on the auxiliary switch based on a logic state of the supply terminal voltage and a voltage across the current sensing resistor, wherein the determining whether to turn on the auxiliary switch comprises: detecting the logic state of the supply terminal voltage; providing a trigger signal having a first level when the supply terminal voltage is at a logic high level for more than a predetermined time duration; providing a detection signal representing the voltage across the current sensing resistor; providing an enable signal having the first level when the detection signal decreases to a first threshold voltage during the trigger signal having the first level; and allowing the auxiliary switch to turn on at a falling edge of the supply terminal voltage during the enable signal having the first level.

8. The control method of claim 7, further comprising providing a reset signal having a turn-on enable window when the detection signal increases to a second threshold voltage, wherein: if the falling edge of the supply terminal voltage occurs within the turn-on enable window, controlling the auxiliary switch to turn on after a dead time; and if the falling edge of the supply terminal voltage does not occur within the turn-on enable window, switching the enable signal from the first level to a second level.

9. The control method of claim 8, wherein the first threshold voltage is less than the second threshold voltage, and the second threshold voltage is a threshold voltage less than and close to 0. ​ ​

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