Signal output circuit, transmitting circuit, and integrated circuit

Abstract

This invention relates to signal output circuits, transmitting circuits, and integrated circuits. The objective is to provide a signal output circuit capable of adjusting multiple signal levels. The signal output circuit includes: a driver circuit (300a) having a variable current source and outputting a multi-value signal; a replication circuit (702) having a circuit configuration equivalent to the driver circuit; and a control circuit (704) controlling the characteristics of the driver circuit based on the output of the replication circuit. The replication circuit includes: a first replication circuit section (705) outputting a first output signal having a signal level of a first subset of the multiple signal levels corresponding to the multi-value signal; and a second replication circuit section (706) outputting a second output signal having a signal level of a second subset of the multiple signal levels. The control circuit controls the characteristics of the variable current source based on the first output signal and the second output signal.

Description

[0001] This application is a divisional application of the invention patent application with application number 201910091018.X, application date January 30, 2019, and invention title "Signal Output Circuit, Transmitting Circuit and Integrated Circuit". Technical Field

[0002] This invention relates to signal output circuits, transmitting circuits, and integrated circuits. Background Technology

[0003] A known transmitting circuit has a driver circuit and a bias circuit (see Patent Document 1). The driver circuit has a first transistor for adjusting the output impedance and a switching circuit connected to the first transistor for switching the output polarity for differential output. The bias circuit has a first replica circuit including a second transistor corresponding to the first transistor, generates a gate voltage whose current and voltage characteristics correspond to the output impedance of the first transistor, and supplies the gate voltage to the gate of the first transistor.

[0004] Furthermore, a differential driver circuit is known to drive a transmission line pair by allowing current to flow through a terminating resistor connected between the transmission line pairs (see Patent Document 2). The driver body includes a first current source transistor on the power supply side, a second current source transistor on the ground side, and multiple output switching transistors connected between each of the first and second current source transistors for controlling the current flowing through the terminating resistor via the transmission line pair. A replication circuit includes a replication terminating resistor having a resistance value larger than the terminating resistor, and multiple replication transistors having on-resistance values ​​larger than the on-resistance values ​​of each of the multiple output switching transistors, connected between the first and second current source transistors, and generating positive and negative virtual potentials by allowing current to flow through the replication terminating resistor. A feedback circuit controls the first current source transistor based on the positive virtual potential and the second current source transistor based on the negative virtual potential, such that the positive and negative potentials of the transmission line pair are respectively predetermined potentials.

[0005] Additionally, an output driver having a first pair of stacked metal-oxide-semiconductor field-effect transistors (MOS) devices and a second pair of stacked MOS devices is known (see Patent Document 3). The first pair of stacked MOS devices is coupled between a power terminal and a first differential output terminal. The second pair of stacked MOS devices is coupled between a second differential output terminal and a ground terminal.

[0006] Furthermore, a current driver is known to drive a transmission line pair by allowing current to flow through a terminating resistor connected between the transmission line pairs (see Patent Document 4). The output circuit is supplied with positive and negative control signals and outputs a differential signal to the transmission line pair. A first current source circuit is connected between a first power supply and the output circuit. A second current source circuit is connected between the output circuit and a second power supply. The current source control circuit controls both the first and second current source circuits with reference to a common-mode voltage that serves as the intermediate voltage of the differential signal.

[0007] Patent Document 1: International Publication No. 2016 / 035192

[0008] Patent Document 2: International Publication No. 2012 / 117456

[0009] Patent Document 3: Japanese Patent Publication No. 2016-502307

[0010] Patent Document 4: Japanese Patent Application Publication No. 2009-038546

[0011] The driver circuit can output multiple signal levels. However, these multiple signal levels are prone to variation. Summary of the Invention

[0012] In one respect, the present invention aims to provide a signal output circuit, a transmitting circuit, and an integrated circuit capable of adjusting multiple signal levels.

[0013] The signal output circuit includes: a driver circuit having a variable current source and outputting a multi-value signal; a replication circuit having a circuit configuration equivalent to the driver circuit; and a control circuit that controls the characteristics of the driver circuit based on the output of the replication circuit. The replication circuit includes: a first replication circuit section that outputs a first output signal having a signal level of a first subset of a plurality of signal levels corresponding to the multi-value signal; and a second replication circuit section that outputs a second output signal having a signal level of a second subset of the plurality of signal levels. The control circuit controls the characteristics of the variable current source based on the first output signal and the second output signal.

[0014] Additionally, the signal output circuit includes: a driver circuit having a variable current source and outputting a multi-value signal; a first detection circuit that detects the signal level of a first subset of the multiple signal levels corresponding to the multi-value signal output from the driver circuit; a second detection circuit that detects the signal level of a second subset of the multiple signal levels corresponding to the multi-value signal output from the driver circuit; and a control circuit that controls the characteristics of the driver circuit based on the signal levels of the first subset and the second subset, and the control circuit controls the characteristics of the variable current source based on the signal levels of the first subset and the second subset.

[0015] On one side, it is possible to adjust multiple signal levels corresponding to multi-value signals. Attached Figure Description

[0016] Figure 1 This is a diagram illustrating an example of the configuration of the integrated circuit according to the first embodiment.

[0017] Figure 2 (A) is a voltage waveform diagram representing an example of a four-valued signal output by a signal output circuit. Figure 2 (B) is a diagram showing examples of voltage waveforms that overlap various migration patterns of a four-valued signal relative to time.

[0018] Figure 3 (A) and (B) are diagrams illustrating examples of signal output circuit configurations.

[0019] Figure 4 (A) and (B) are diagrams illustrating examples of signal output circuit configurations.

[0020] Figure 5 (A) is a diagram showing a signal output circuit that adjusts the signal level by controlling the value of the resistor. Figure 5 (B) is a graph showing an example of the relationship between the resistance code adjustment and RLM.

[0021] Figure 6 (A) is a diagram showing an example of the configuration of the driver circuit according to the first embodiment. Figure 6 (B) is a graph showing an example of the relationship between the current of a variable current source and the RLM.

[0022] Figure 7 This is a diagram illustrating an example of the configuration of the signal output circuit according to the first embodiment.

[0023] Figure 8 This is a flowchart illustrating the control method of the integrated circuit according to the first embodiment.

[0024] Figure 9This is a diagram illustrating a configuration example of a portion of the signal output circuit according to the second embodiment.

[0025] Figure 10 This is a diagram illustrating a configuration example of a portion of the signal output circuit according to the third embodiment.

[0026] Figure 11 This is a diagram illustrating an example of the configuration of the comparison circuit according to the fourth embodiment.

[0027] Figure 12 This is a diagram illustrating a configuration example of a portion of the signal output circuit according to the fifth embodiment.

[0028] Figure 13 This is a diagram illustrating an example of the configuration of the signal output circuit according to the sixth embodiment.

[0029] Figure 14 This is a diagram illustrating an example of the configuration of a voltage holding circuit.

[0030] Figure 15 This is a flowchart illustrating the control method of the integrated circuit according to the sixth embodiment.

[0031] Figure 16 This is a diagram illustrating an example of the configuration of the signal output circuit according to the seventh embodiment.

[0032] Figure 17 This is a flowchart illustrating the control method of the integrated circuit according to the seventh embodiment.

[0033] Figure 18 This is a diagram illustrating an example of the configuration of the signal output circuit according to the eighth embodiment.

[0034] Figure 19 This is a flowchart illustrating the control method of the integrated circuit according to the eighth embodiment. Detailed Implementation

[0035] (First Implementation)

[0036] Figure 1 This diagram illustrates a configuration example of integrated circuits 100 and 130 according to the first embodiment. Integrated circuits 100 and 130 are interconnected via transmission lines 161 and 162. Integrated circuit 100 includes a central processing unit (CPU) 101, a transmitting circuit 102, a receiving circuit 103, and a phase-locked loop (PLL) circuit 104. The central processing unit 101 is an internal circuit that generates internal data and outputs the internal data in parallel to the transmitting circuit 102.

[0037] The transmitting circuit 102 includes a multiplexer 111 and a signal output circuit 112. The multiplexer 111 receives a first-bit parallel data input generated by the central processing unit 101 and multiplexes the first-bit parallel data with a second-bit parallel data input that is less than the first bit. For example, the multiplexer 111, synchronized with a clock signal generated by the phase-locked loop circuit 104, multiplexes sixteen bits of parallel data into two bits of parallel data and outputs the two bits of parallel data to the signal output circuit 112. The signal output circuit 112 transmits a four-valued signal corresponding to the two bits of parallel data to the integrated circuit 130 via transmission line 161. Furthermore, the signal output circuit 112 can receive more than two bits of parallel data and output multi-valued signals. Multi-valued signals are signals with three or more values.

[0038] The receiving circuit 103 includes a decision feedback equalizer (DFE) 121 and a demultiplexer 122. The DFE 121 receives a four-valued signal (multi-valued signal) from the integrated circuit 130 via transmission line 162, performs equalization and four-value determination on the received four-valued signal, and outputs two bits of parallel data. The demultiplexer 122, synchronized with a clock signal generated by the phase-locked loop circuit 104, demultiplexes the two bits of parallel data output by the DFE 121 into, for example, sixteen bits of parallel data, and outputs, for example, the sixteen bits of parallel data to the central processing unit 101. The central processing unit 101, for example, processes the sixteen bits of parallel data.

[0039] Integrated circuit 130 is identical to integrated circuit 100, including a central processing unit 131, a transmitting circuit 132, a receiving circuit 133, and a phase-locked loop circuit 134. The transmitting circuit 132 is identical to the transmitting circuit 102 described above, including a multiplexer 141 and a signal output circuit 142, and transmits a four-valued signal to integrated circuit 100 via transmission line 162. The receiving circuit 133 is identical to the receiving circuit 103 described above, including a DFE 151 and a demultiplexer 152, and receives the four-valued signal from integrated circuit 100 via transmission line 161. The processing of integrated circuit 130 is the same as that of integrated circuit 100 described above.

[0040] Figure 2 (A) represents Figure 1The voltage waveform diagram is an example of the four-valued signal output by the signal output circuit 112. The following description uses signal output circuit 112 as an example, but signal output circuit 142 is the same as signal output circuit 112. Signal output circuit 112 inputs two parallel data bits and outputs a four-valued signal. During period T1, signal output circuit 112 outputs a signal level V(-1) corresponding to the two parallel data bits "00". During period T2, signal output circuit 112 outputs a signal level V(-1 / 3) corresponding to the two parallel data bits "01". During period T3, signal output circuit 112 outputs a signal level V(+1 / 3) corresponding to the two parallel data bits "10". During period T4, signal output circuit 112 outputs a signal level V(+1) corresponding to the two parallel data bits "11".

[0041] Figure 2 Figure (B) is a diagram showing an example of a voltage waveform that overlaps various migration patterns of a four-valued signal relative to time. The voltage waveform changes according to the past signal level of the four-valued signal. Eye diagram 201 is an eye diagram formed between signal levels V(-1) and V(-1 / 3). Eye diagram 202 is an eye diagram formed between signal levels V(-1 / 3) and V(+1 / 3). Eye diagram 203 is an eye diagram formed between signal levels V(+1 / 3) and V(+1).

[0042] Ideally, signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) are equally spaced voltage values. The differences between signal levels V(+1) and V(+1 / 3), V(+1 / 3) and V(-1 / 3), and V(-1 / 3) and V(-1) are each 1 / 3 of the difference between signal levels V(+1) and V(-1), and are identical to each other.

[0043] Next, we will explain RLM (Level Separation Mismatch Ratio). RLM is expressed by the following formula.

[0044] Vmid = {V(-1) + V(+1)} / 2

[0045] ES1={V(-1 / 3)-Vmid} / {V(-1)-Vmid}

[0046] ES2={V(+1 / 3)-Vmid} / {V(+1)-Vmid}

[0047] RLM=min{(3·ES1), (3·ES2), (2-3·ES1), (2-3·ES2)}

[0048] RLM is the minimum value among (3·ES1), (3·ES2), (2-3·ES1), and (2-3·ES2). RLM represents the degree of balance of the three eye diagrams 201 to 203. When the amplitudes of the three eye diagrams 201 to 203 are all the same, RLM is 1. The signal output circuit 112 requires, for example, an RLM of 0.95 or higher. By increasing RLM, the quality of the transmitted quaternary signal is improved, and the receiving circuit 133 can reduce the reproduction error of the quaternary signal. To increase RLM, the signal output circuit 112 adjusts the signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) to be equally spaced voltage values.

[0049] Figure 3 (A), (B) and Figure 4 Figures (A) and (B) are examples illustrating the configuration of the signal output circuit 112. The signal output circuit 112 includes a driver circuit 300 and is connected to... Figure 1 The DFE151 is connected. The DFE151 has a 50Ω resistor 331 and a 50Ω resistor 332. Resistors 331 and 332 are connected in series between node N1 and node N2.

[0050] The driver circuit 300 has 150Ω resistors 301-304, 75Ω resistors 305-308, p-channel field-effect transistors (switches) 311-314, and n-channel field-effect transistors (switches) 321-324.

[0051] P-channel MOSFET 311 and resistor 301 are connected in series between the power supply potential node and node N1. P-channel MOSFET 312 and resistor 305 are connected in series between the power supply potential node and node N1. Resistor 302 and n-channel MOSFET 321 are connected in series between node N1 and the reference potential node (ground potential node). Resistor 306 and n-channel MOSFET 322 are connected in series between node N1 and the reference potential node.

[0052] P-channel MOSFET 313 and resistor 303 are connected in series between the power supply potential node and node N2. P-channel MOSFET 314 and resistor 307 are connected in series between the power supply potential node and node N2. Resistor 304 and n-channel MOSFET 323 are connected in series between node N2 and the reference potential node. Resistor 308 and n-channel MOSFET 324 are connected in series between node N2 and the reference potential node.

[0053] Figure 3Figure (A) shows the signal output circuit 112, which outputs a signal level V(+1) from node N1. If two parallel data bits "11" are input, signal output circuit 112 outputs a signal level V(+1) from node N1 and a signal level V(-1) from node N2. If two parallel data bits "11" are input, p-channel MOSFETs 311 and 312 are turned on, n-channel MOSFETs 321 and 322 are turned off, p-channel MOSFETs 313 and 314 are turned off, and n-channel MOSFETs 323 and 324 are turned on. The combined resistance of the parallel 150Ω resistor and the 75Ω resistor is 50Ω. Node N1 becomes signal level V(+1). Node N2 becomes signal level V(-1).

[0054] Figure 3 (B) is a diagram showing the signal output circuit 112 that outputs a signal level V(+1 / 3) from node N1. If the signal output circuit 112 receives two parallel data bits "10", it outputs a signal level V(+1 / 3) from node N1 and a signal level V(-1 / 3) from node N2. If the input is two parallel data bits "10", then p-channel MOSFETs 312 and 313 are turned on, n-channel MOSFETs 321 and 324 are turned on, p-channel MOSFETs 311 and 314 are turned off, and n-channel MOSFETs 322 and 323 are turned off. Node N1 becomes signal level V(+1 / 3). Node N2 becomes signal level V(-1 / 3).

[0055] Figure 4 Figure (A) shows the signal output circuit 112, which outputs a signal level V(-1 / 3) from node N1. If two parallel data bits "01" are input, signal output circuit 112 outputs a signal level V(-1 / 3) from node N1 and a signal level V(+1 / 3) from node N2. If two parallel data bits "01" are input, p-channel MOSFETs 311 and 314 are turned on, n-channel MOSFETs 322 and 323 are turned on, p-channel MOSFETs 312 and 313 are turned off, and n-channel MOSFETs 321 and 324 are turned off. Node N1 becomes signal level V(-1 / 3). Node N2 becomes signal level V(+1 / 3).

[0056] Figure 4(B) is a diagram showing the signal output circuit 112 that outputs a signal level V(-1) from node N1. If two parallel data bits "00" are input, signal output circuit 112 outputs a signal level V(-1) from node N1 and a signal level V(+1) from node N2. If two parallel data bits "00" are input, p-channel MOSFETs 313 and 314 are turned on, n-channel MOSFETs 321 and 322 are turned on, p-channel MOSFETs 311 and 312 are turned off, and n-channel MOSFETs 323 and 324 are turned off. The combined resistance of the parallel 150Ω resistor and the 75Ω resistor is 50Ω. Node N1 becomes signal level V(-1). Node N2 becomes signal level V(+1).

[0057] Here, the signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) vary due to the deviation of resistors 301 to 308 and the nonlinear characteristics of field-effect transistors 311 to 314 and 321 to 324, and RLM decreases.

[0058] Figure 5 Figure (A) shows a signal output circuit 112 that adjusts the signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) by controlling the values ​​of resistors 301 to 308. Resistors 301 to 308 are variable resistors. The signal output circuit 112 can adjust the signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) by controlling the values ​​of resistors 301 to 308.

[0059] Figure 5 (B) is a graph showing an example of the relationship between the code adjustment amount of the 75Ω resistors 305-308 and the RLM. The signal output circuit 112 can adjust the RLM by controlling the value of the 75Ω resistors 305-308 using the code adjustment amount.

[0060] However, when refining the variable resolution of the values ​​of resistors 301 to 308, the number of switchable resistors within each of resistors 301 to 308 increases, and the area of ​​each of resistors 301 to 308 increases. With limited area, it is difficult to achieve an RLM of, for example, above 0.95.

[0061] Figure 6 Figure (A) is a diagram showing an example of the configuration of the driver circuit 300a according to the first embodiment. The signal output circuit 112 includes the driver circuit 300a. The driver circuit 300a is for... Figure 3The driver circuit 300 of (A) is supplemented with variable current sources 341 to 344. Variable current source 341 is connected between the power supply potential node and node N1. Variable current source 342 is connected between node N1 and the reference potential node. Variable current source 343 is connected between the power supply potential node and node N2. Variable current source 344 is connected between node N2 and the reference potential node. Variable current sources 341 to 344 can respectively change the current by controlling the number of transistors constituting the current mirror. Therefore, variable current sources 341 to 344 can easily adjust the adjustment range and resolution of the RLM, and... Figure 5 Compared to the variable resistor of (A), it can suppress the increase in area.

[0062] exist Figure 3 (A) and Figure 3 Under control state (B), the signal output circuit 112 can control the current flowing through resistors 331 and 332 by controlling variable current sources 341 and 344, thereby controlling the voltage drop across resistors 331 and 332. Thus, the signal output circuit 112 can control the signal levels V(+1) and V(+1 / 3) to adjust RLM.

[0063] exist Figure 4 (A) and Figure 4 Under control state (B), the signal output circuit 112 can control the current flowing through resistors 331 and 332 by controlling variable current sources 342 and 343, thereby controlling the voltage drop across resistors 331 and 332. Thus, the signal output circuit 112 can control the signal levels V(-1 / 3) and V(-1) to adjust RLM.

[0064] Figure 6 (B) is a graph showing an example of the relationship between the current of the variable current source 341 and RLM. The signal output circuit 112 can adjust RLM by controlling the variable current sources 341 to 344.

[0065] Figure 7 This diagram illustrates a configuration example of the signal output circuit 112 according to the first embodiment. The signal output circuit 112 includes a driver circuit 300a, a control circuit 701, a copy circuit 702, a comparison circuit 703, and a control circuit 704. The control circuit 701 is based on... Figure 1 The two parallel data bits D1 and D2 input to the multiplexer 111 are as follows: Figure 3 (A), (B) and Figure 4 As shown in (A) and (B), control field-effect transistors 311-314 and 321-324. Driver circuit 300a has... Figure 6The driver circuit 300a shown in (A) outputs signal levels V(-1), V(-1 / 3), V(+1 / 3) or V(+1) corresponding to the four-valued signals from nodes N1 and N2.

[0066] The replication circuit 702 has a first replication circuit section 705 and a second replication circuit section 706, and has a circuit configuration equivalent to that of the driver circuit 300a. The first replication circuit section 705 has a variable current source 707. The second replication circuit section 706 has a variable current source 708. The variable current sources 707 and 708 are connected to... Figure 6 The variable current source 341 to 344 corresponds to the driver circuit 300a of (A).

[0067] The first replication circuit unit 705 generates a first subset of the four signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) corresponding to the four-valued signal. For example, the first replication circuit unit 705 generates the first subset signal levels V(-1 / 3) and V(+1 / 3).

[0068] The second replication circuit unit 706 outputs the signal level of a second subset of the four signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) corresponding to the four-valued signal. For example, the second replication circuit unit 706 generates the second subset signal levels V(-1) and V(+1).

[0069] The comparator circuit 703 compares signal level V1 and signal level V2 and outputs the comparison result signal Vc. Signal level V1 is based on the first comparison target level of signal level V(-1 / 3) and signal level V(+1 / 3) generated by the first copy circuit unit 705, and is expressed, for example, by the following formula.

[0070] V1 = V(+1 / 3) - V(-1 / 3)

[0071] The signal level V2 is a second comparison object level based on the signal level V(-1) and V(+1) generated by the second replication circuit section 706, for example, expressed by the following formula.

[0072] V2=(V(+1)-V(-1))×1 / 3

[0073] Based on the comparison result signal Vc, control circuit 704 controls the current of variable current sources 707 and 708 through adjustment code C1 to make signal level V1 close to signal level V2. If signal level V1 and signal level V2 are the same, control circuit 704 fixes adjustment code C1 and outputs adjustment code C2 corresponding to adjustment code C1 to driver circuit 300a. Control circuit 704 controls the current of variable current sources 707 and 708 through adjustment code C2. Figure 6The variable current sources 341 to 344 within the driver circuit 300a (A) have current characteristics. The variable current sources 341 to 344 within the driver circuit 300a control the current according to the adjustment code C2. As a result, the RLM of the four-value signal output by the driver circuit 300a is adjusted to 0.95 or higher. Furthermore, the details of the copy circuit 702 and the comparison circuit 703 will be described using the following embodiments.

[0074] Figure 8 This is a flowchart illustrating the control method of integrated circuit 100. In step S801, integrated circuit 100 performs a test mode preparation process. Integrated circuit 100 activates replication circuit 702. Control circuit 704 resets adjustment code C1 to its initial value and outputs the initial value of adjustment code C1 to variable current sources 707 and 708. For example, the initial value of adjustment code C1 is the minimum value. Variable current sources 707 and 708 cause current to flow based on adjustment code C1.

[0075] Next, in step S802, the control circuit 704 increments the adjustment code C1 by 1 and outputs the calculated adjustment code C1 to the variable current sources 707 and 708. The variable current sources 707 and 708 then cause current to flow based on the adjustment code C1.

[0076] Next, in step S803, the control circuit 704 determines whether signal level V1 and signal level V2 are the same based on the comparison result signal Vc from the comparison circuit 703. If signal level V1 and signal level V2 are not the same, the control circuit 704 returns to step S802 and repeats the above process. As the adjustment code C1 increases, signal level V1 gradually approaches signal level V2. If the control circuit 704 determines that signal level V1 and signal level V2 are the same, it proceeds to step S804.

[0077] In step S804, the control circuit 704 determines the adjustment code C2 corresponding to the current adjustment code C1, outputs the adjustment code C2 to the variable current sources 341 to 344 in the driver circuit 300a, and ends the test mode processing. Thereafter, the integrated circuit 100 performs normal mode processing. The variable current sources 341 to 344 in the driver circuit 300a respectively cause current to flow based on the adjustment code C2. The driver circuit 300a can output signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) that are the same as the signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) generated by the replication circuit 702.

[0078] The driver circuit 300a can output equally spaced signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) based on the adjustment code C2. This improves the Regeneration Length Modulation (RLM) of the quaternary signal output by the driver circuit 300a. By increasing the RLM, the quality of the quaternary signal is improved, and the receiving circuit 133 can reduce the regeneration error of the quaternary signal.

[0079] (Second Implementation)

[0080] Figure 9 This diagram illustrates an example configuration of the first copying circuit unit 705, the second copying circuit unit 706, the comparison circuits 703a and 703b, and the control circuit 704 according to the second embodiment. The comparison circuits 703a and 703b... Figure 7 The comparator circuit 703 corresponds to this. The differences between the second embodiment and the first embodiment will be explained below.

[0081] The first replication circuit section 705 includes resistors 905a, 902a, 903a, 908a, 951 to 954, p-channel field-effect transistors (switches) 912a and 913a, n-channel field-effect transistors (switches) 921a and 924a, and variable current sources 941a to 944a.

[0082] Variable current source 941a and Figure 6 The variable current source 341 of the driver circuit 300a of (A) corresponds to the connection between the power supply potential node and node N1a. The variable current source 942a and... Figure 6 The variable current source 342 of the driver circuit 300a of (A) is connected between node N1a and the reference potential node.

[0083] A p-channel field-effect transistor 912a and a resistor 905a are connected in series between the power supply potential node and node N1a. The p-channel field-effect transistor 912a and... Figure 6 The driver circuit of (A) corresponds to the p-channel field-effect transistor 312 of 300a. A 75Ω resistor 905A is used. Figure 6 The 75Ω resistor 305 corresponds to the driver circuit 300a of (A).

[0084] A resistor 902a and an n-channel field-effect transistor 921a are connected in series between node N1a and the reference potential node. The 150Ω resistor 902a and... Figure 6 The 150Ω resistor 302 corresponds to the driver circuit 300a of (A). The n-channel field-effect transistor 921a and... Figure 6 The driver circuit 300a of (A) corresponds to the n-channel field-effect transistor 321.

[0085] Variable current source 943a and Figure 6 The variable current source 343 of the driver circuit 300a of (A) corresponds to the connection between the power supply potential node and node N2a. The variable current source 944a and... Figure 6 The variable current source 344 of the driver circuit 300a of (A) is connected between node N2a and the reference potential node.

[0086] A p-channel field-effect transistor 913a and a resistor 903a are connected in series between the power supply potential node and node N2a. The p-channel field-effect transistor 913a and... Figure 6 The driver circuit 300a of (A) corresponds to the p-channel field-effect transistor 313. A 150Ω resistor 903a is used. Figure 6 The 150Ω resistor 303 corresponds to the driver circuit 300a of (A).

[0087] A resistor 908A and an n-channel field-effect transistor 924A are connected in series between node N2a and the reference potential node. The 75Ω resistor 908A and... Figure 6 The 75Ω resistor 308 corresponds to the driver circuit 300a of (A). The n-channel field-effect transistor 924a and... Figure 6 The driver circuit 300a of (A) corresponds to the n-channel field-effect transistor 324.

[0088] Resistors 951 and 952 are connected in series between node N1a and node N5. Node N5 is a common voltage node. Resistor 951 has a resistance of (50 × 2 / 3) Ω. Resistor 952 has a resistance of (50 × 1 / 3) Ω. The combined resistance of the series-connected resistors 951 and 952 is 50 Ω. Figure 6 The resistance of (A) corresponds to 331.

[0089] Resistors 953 and 954 are connected in series between node N5 and node N2a. Resistor 953 has a resistance of (50 × 1 / 3) Ω. Resistor 954 has a resistance of (50 × 2 / 3) Ω. The combined resistance of the series-connected resistors 953 and 954 is 50 Ω. Figure 6 The resistance of (A) corresponds to 332.

[0090] First copying circuit section 705 and Figure 3 The same as (B), output signal level V(+1 / 3) from node N1a and signal level V(-1 / 3) from node N2a.

[0091] The second replication circuit section 706 includes resistors 901b, 905b, 904b, 908b, 961 to 964, p-channel field-effect transistors (switches) 911b and 912b, n-channel field-effect transistors (switches) 923b and 924b, and variable current sources 941b to 944b.

[0092] Variable current source 941b and Figure 6 The variable current source 341 of the driver circuit 300a of (A) corresponds to the variable current source 341, which is connected between the power supply potential node and node N1b. The variable current source 942b and... Figure 6 The variable current source 342 of the driver circuit 300a of (A) is connected between node N1b and the reference potential node.

[0093] A p-channel field-effect transistor 911b and a resistor 901b are connected in series between the power supply potential node and node N1b. The p-channel field-effect transistor 911b and... Figure 6 The driver circuit 300a of (A) corresponds to the p-channel field-effect transistor 311. The 150Ω resistor 901b is... Figure 6 The 150Ω resistor 301 corresponds to the driver circuit 300a of (A).

[0094] A p-channel field-effect transistor 912b and a resistor 905b are connected in series between the power supply potential node and node N1b. The p-channel field-effect transistor 912b and... Figure 6 The driver circuit 300a of (A) corresponds to the p-channel field-effect transistor 312. The 75Ω resistor 905b is... Figure 6 The 75Ω resistor 305 corresponds to the driver circuit 300a of (A).

[0095] Variable current source 943b and Figure 6 The variable current source 343 of the driver circuit 300a (A) corresponds to the variable current source 343, which is connected between the power supply potential node and node N2b. The variable current source 944b and... Figure 6 The variable current source 344 of the driver circuit 300a of (A) is connected between node N2b and the reference potential node.

[0096] A resistor 904b and an n-channel field-effect transistor 923b are connected in series between node N2b and the reference potential node. The 150Ω resistor 904b and... Figure 6 The 150Ω resistor 304 corresponds to the driver circuit 300a of (A). The n-channel field-effect transistor 923b is... Figure 6 The driver circuit 300a of (A) corresponds to the n-channel field-effect transistor 323.

[0097] A resistor 908b and an n-channel field-effect transistor 924b are connected in series between node N2b and the reference potential node. The 75Ω resistor 908b and... Figure 6 The 75Ω resistor 308 corresponds to the driver circuit 300a of (A). The n-channel field-effect transistor 924b is... Figure 6 The driver circuit 300a of (A) corresponds to the n-channel field-effect transistor 324.

[0098] Resistor 961, with a resistance of (50 × 2 / 3) Ω, is connected between node N1b and node N3. Resistor 962, with a resistance of (50 × 1 / 3) Ω, is connected between node N3 and node N6. Node N6 is a common voltage node. The combined resistance of resistors 961 and 962, connected in series, is 50 Ω. Figure 6 The resistance of (A) corresponds to 331.

[0099] Resistor 963, with a resistance of (50 × 1 / 3) Ω, is connected between nodes N6 and N4. Resistor 964, with a resistance of (50 × 2 / 3) Ω, is connected between nodes N4 and N2b. The combined resistance of resistors 963 and 964, connected in series, is 50 Ω. Figure 6 The resistance of (A) corresponds to 332. The combined resistance of resistors 961 to 964 is the same as that of resistors 951 to 954.

[0100] In the second replication circuit section 706, with Figure 3 Similar to (A), node N1b has a signal level V(+1), and node N2b has a signal level V(-1). The voltage between node N4 and node N2b is one-third of the difference between the signal level V(+1) of node N1b and the signal level V(-1) of node N2b. Therefore, node N4 outputs a signal level equal to the sum of the difference between the signal levels V(+1) and V(-1) of node N1b and node N2b, which is the signal level V(-1) of node N2b. The signal level of node N4 corresponds to the signal level V(-1 / 3).

[0101] The comparison circuit 703b compares the signal level V(-1 / 3) output from node N2a of the first replication circuit section 705 with the signal level V(-1 / 3) output from node N4 of the second replication circuit section 706, and outputs the comparison result signal to the control circuit 704.

[0102] The voltage between nodes N1b and N3 is one-third of the difference between the signal level V(+1) of node N1b and the signal level V(-1) of node N2b. Therefore, the output voltage of node N3 is the signal level of node N3 minus the difference between the signal levels V(+1) of node N1b and V(-1) of node N2b. The signal level of node N3 corresponds to the signal level V(+1 / 3).

[0103] The comparison circuit 703a compares the signal level V(+1 / 3) output from node N1a of the first replication circuit section 705 with the signal level V(+1 / 3) output from node N3 of the second replication circuit section 706, and outputs the comparison result signal to the control circuit 704.

[0104] Based on the comparison result signals of the comparison circuits 703a and 703b, the control circuit 704 controls the current of the variable current sources 941a to 944a and 941b to 944b by adjusting the code C1, so that the signal level V(-1 / 3) of node N2a is close to the signal level V(-1 / 3) of node N4, and the signal level V(+1 / 3) of node N1a is close to the signal level V(+1 / 3) of node N3.

[0105] When the comparison results from comparator circuits 703a and 703b are consistent, control circuit 704 fixes adjustment code C1 and outputs adjustment code C2 corresponding to adjustment code C1 to driver circuit 300a. Control circuit 704 controls the driver circuit 300a by adjusting code C2. Figure 6 The variable current sources 341 to 344 within the driver circuit 300a of (A) are adjusted to a current of 0.95 or higher.

[0106] (Third Implementation)

[0107] Figure 10 This diagram illustrates an example configuration of the first copying circuit unit 705, the second copying circuit unit 706, the comparison circuit 1001, and the control circuit 704 according to the third embodiment. The comparison circuit 1001 and... Figure 7 The comparator circuit 703 corresponds to this. Figure 10 Compared to Figure 9 Instead of comparator circuits 703a and 703b, comparator circuit 1001 is provided. The differences between the third embodiment and the second embodiment will be explained below.

[0108] The comparison circuit 1001 compares the difference between the signal level V(+1 / 3) of node N1a and the signal level V(-1 / 3) of node N2a in the first replication circuit section 705, and the difference between the signal level V(+1 / 3) of node N3 and the signal level V(-1 / 3) of node N4 in the second replication circuit section 706, and outputs the comparison result signal to the control circuit 704. Here, the level difference between the signal level V(+1 / 3) of node N3 and the signal level V(-1 / 3) of node N4 in the second replication circuit section 706 is one-third of the level difference between the signal level V(+1) of node N1b and the signal level V(-1) of node N2b.

[0109] Based on the comparison result signal of the comparison circuit 1001, the control circuit 704 controls the current of the variable current sources 941a to 944a and 941b to 944b by adjusting the code C1, so that the difference between the signal level V(+1 / 3) of node N1a and the signal level V(-1 / 3) of node N2a is close to the difference between the signal level V(+1 / 3) of node N3 and the signal level V(-1 / 3) of node N4.

[0110] When the comparison result signals from the comparator circuit 1001 are consistent, the control circuit 704 fixes the adjustment code C1 and outputs the adjustment code C2 corresponding to adjustment code C1 to the driver circuit 300a. The control circuit 704 controls the driver circuit 300a by adjusting code C2. Figure 6 The variable current sources 341 to 344 within the driver circuit 300a of (A) are adjusted to a current of 0.95 or higher.

[0111] If the common voltage of node N5 deviates from the common voltage of node N6, then Figure 9 The signal output circuit 112 may experience a decrease in the adjustment accuracy of the RLM. According to this embodiment, the comparator circuit 1001 compares the difference in signal levels between nodes N1a and N2a and the difference in signal levels between nodes N3 and N4, so the signal output circuit 112 can adjust the RLM with high accuracy even when the common voltage of node N5 deviates from the common voltage of node N6.

[0112] (Fourth Implementation)

[0113] Figure 11 This diagram illustrates a configuration example of the comparator circuit 1100 according to the fourth embodiment. The comparator circuit 1100 and... Figure 7 The comparator circuit 703 corresponds to this. In the third embodiment ( Figure 10In the signal output circuit 112, a comparison circuit 1100 is provided instead of a comparison circuit 1001. Hereinafter, the differences between the fourth embodiment and the third embodiment will be explained.

[0114] The comparator circuit 1100 includes resistors 1101 and 1102, n-channel field-effect transistors 1103–1106, a current source 1107, and a comparator 1108. Resistor 1101 is connected between the power supply potential node and node N7. The drain of n-channel field-effect transistor 1103 is connected to node N7, its gate is connected to node N1a, and its source is connected to node N9. The drain of n-channel field-effect transistor 1104 is connected to node N7, its gate is connected to node N4, and its source is connected to node N9.

[0115] Resistor 1102 is connected between the power supply potential node and node N8. The drain of n-channel MOSFET 1105 is connected to node N8, its gate to node N2a, and its source to node N9. The drain of n-channel MOSFET 1106 is connected to node N8, its gate to node N3, and its source to node N9. Current source 1107 is connected between node N9 and the reference potential node.

[0116] Node N1a is node N1a of the first replication circuit section 705, with an output signal level of V(+1 / 3). Node N2a is node N2a of the first replication circuit section 705, with an output signal level of V(-1 / 3). Node N3 is node N3 of the second replication circuit section 706, with an output signal level of V(+1 / 3). Node N4 is node N4 of the second replication circuit section 706, with an output signal level of V(-1 / 3).

[0117] Node N7 outputs the sum of the signal levels V(+1 / 3) of node N1a and V(-1 / 3) of node N4. Node N8 outputs the sum of the signal levels V(-1 / 3) of node N2a and V(+1 / 3) of node N3.

[0118] Comparator 1108 compares the signal level of node N7 with the signal level of node N8, and outputs the comparison result signal to Figure 10 The control circuit 704. Based on the comparison result signal of comparator 1108, the control circuit 704 controls the current of variable current sources 941a to 944a and 941b to 944b by adjusting code C1, so that the signal level of node N7 is close to the signal level of node N8.

[0119] When the comparison result signals from comparator 1108 are consistent, control circuit 704 fixes adjustment code C1 and outputs adjustment code C2 corresponding to adjustment code C1 to driver circuit 300a. Control circuit 704 controls the driver circuit 300a by adjusting code C2. Figure 6 The variable current sources 341 to 344 within the driver circuit 300a of (A) are adjusted to a current of 0.95 or higher.

[0120] (Fifth Implementation)

[0121] Figure 12 This diagram illustrates an example configuration of the first replication circuit section 705, the second replication circuit section 706, resistors 1201-1204, comparator 1205, and control circuit 704 according to the fifth embodiment. Resistors 1201-1204 and comparator 1205 are... Figure 7 The comparator circuit 703 corresponds to this. Figure 12 Compared to Figure 10 Instead of the comparator circuit 1001, resistors 1201 to 1204 and comparator 1205 are provided. The differences between the fifth embodiment and the third embodiment will be explained below.

[0122] Resistors 1201 through 1204 are extremely large resistors relative to 50Ω, for example, 1kΩ. Resistor 1201 is connected between node N1a and node N10. Resistor 1202 is connected between node N10 and node N4. Resistor 1203 is connected between node N3 and node N11. Resistor 1204 is connected between node N11 and node N2a.

[0123] Node N10 outputs the average signal level of node N1a (+1 / 3) and node N4 (-1 / 3). Node N11 outputs the average signal level of node N3 (+1 / 3) and node N2a (-1 / 3).

[0124] Comparator 1205 compares the signal levels of node N10 and node N11, and outputs the comparison result signal to control circuit 704. Based on the comparison result signal from comparator 1205, control circuit 704 adjusts code C1 to control the current of variable current sources 941a-944a and 941b-944b, so that the signal level of node N10 is close to the signal level of node N11.

[0125] When the comparison result signals from comparator 1205 are consistent, control circuit 704 fixes adjustment code C1 and outputs adjustment code C2 corresponding to adjustment code C1 to driver circuit 300a. Control circuit 704 controls the driver circuit 300a by adjusting code C2. Figure 6 The variable current sources 341 to 344 within the driver circuit 300a of (A) are adjusted to a current of 0.95 or higher.

[0126] exist Figure 11 In the signal output circuit 112, due to the nonlinear characteristics of the n-channel field-effect transistors 1103-1106, errors occur in the signal levels of nodes N7 and N8. According to this embodiment, since no field-effect transistors are connected to the input nodes of comparator 1205, the errors in the signal levels of nodes N10 and N11 can be reduced, allowing for high-precision adjustment of the RLM. Furthermore, comparator 1205 compares the average signal levels of nodes N1a and N4 with the average signal levels of nodes N3 and N2a, so even if the common voltage at node N5 deviates from the common voltage at node N6, the RLM can still be adjusted with high precision in the signal output circuit 112. Additionally, deviation can be eliminated by swapping the two input nodes of comparator 1205.

[0127] (Sixth Implementation Method)

[0128] Figure 13 This is a diagram showing an example of the configuration of the signal output circuit 112 according to the sixth embodiment. Figure 13 The signal output circuit 112 is relative to Figure 7 The signal output circuit 112 has had its copying circuit 702, comparator circuit 703, and control circuit 704 removed, and switches 1301 and 1302, voltage holding circuits 1303 and 1304, resistors 1305 to 1308, and comparator circuit 1309 added. For example... Figure 6 As shown in (A), the driver circuit 300a has variable current sources 341-344, and nodes N1 and N2 of the driver circuit 300a are connected to DFE151. The control circuit 701 is based on... Figure 1 The two parallel data bits D1 and D2 input to the multiplexer 111 are as follows: Figure 3 (A), (B) and Figure 4 As shown in (A) and (B), the field-effect transistors 311-314 and 321-324 within the driver circuit 300a are controlled. The driver circuit 300a has... Figure 6The driver circuit 300a shown in (A) outputs signal levels V(-1), V(-1 / 3), V(+1 / 3), or V(+1) corresponding to the four-valued signals from nodes N1 and N2. Switch 1301 and voltage holding circuit 1303 function as, for example, a first detection circuit for detecting signal levels V(-1) and V(+1) among the signal levels corresponding to the four-valued signals. Switch 1302 and voltage holding circuit 1304 function as, for example, a second detection circuit for detecting signal levels V(-1 / 3) and V(+1 / 3) among the signal levels corresponding to the four-valued signals.

[0129] Next, the method for determining the adjustment codes of the variable current sources 341 to 344 within the driver circuit 300a will be explained. First, the control circuit 701 sets the adjustment codes of the variable current sources 341 to 344 to initial values. Next, the control circuit 701... Figure 3 As shown in (A), the field-effect transistors 311-314 and 321-324, corresponding to the two parallel data bits "11", are controlled to turn on switch 1301 and turn off switch 1302. This causes the driver circuit 300a to output a signal level V(+1) from node N1 and a signal level V(-1) from node N2. The voltage holding circuit 1303 holds the signal level V(+1) at node N1 and the signal level V(-1) at node N2. Then, the control circuit 701 turns off switch 1301.

[0130] Next, the control circuit 701 as follows Figure 3 As shown in (B), the state of field-effect transistors 311-314 and 321-324, corresponding to the two parallel data bits "10," is controlled to open switch 1301 and close switch 1302. This causes driver circuit 300a to output a signal level V(+1 / 3) from node N1 and a signal level V(-1 / 3) from node N2. Voltage holding circuit 1304 holds the signal level V(+1 / 3) at node N1 and the signal level V(-1 / 3) at node N2. Subsequently, control circuit 701 opens switch 1302.

[0131] Voltage holding circuit 1303 outputs held signal levels V(+1) and V(-1). Voltage holding circuit 1304 outputs held signal levels V(+1 / 3) and V(-1 / 3).

[0132] Resistor 1305 is connected between node N12 of voltage holding circuit 1303 at signal level V(-1). Resistor 1306 is connected between node N12 of voltage holding circuit 1304 at signal level V(+1 / 3). The ratio of the resistance value of resistor 1305 to the resistance value of resistor 1306 is 3:1. Resistors 1305 and 1306 are extremely large resistors relative to 50Ω. For example, resistor 1305 is 3kΩ and resistor 1306 is 1kΩ. The signal level V1 of node N12 is expressed by the following formula. Signal level V1 is the intermediate signal level between signal level V(-1) and signal level V(+1 / 3), as shown below. Figure 2 As shown in (A), it corresponds to the average signal level of signal level V(+1 / 3) and signal level V(-1 / 3).

[0133] V1=(V(+1 / 3)-V(-1))×3 / 4+V(-1)

[0134] Resistor 1307 is connected between node N13 of voltage holding circuit 1303 at signal level V(+1). Resistor 1308 is connected between node N13 of voltage holding circuit 1304 at signal level V(-1 / 3). The ratio of the resistance value of resistor 1307 to the resistance value of resistor 1308 is 3:1. Resistors 1307 and 1308 are extremely large resistors relative to 50Ω. For example, resistor 1307 is 3kΩ and resistor 1308 is 1kΩ. The signal level V2 of node N13 is expressed by the following formula. Signal level V2 is the intermediate signal level between signal level V(-1 / 3) and signal level V(+1), as shown below. Figure 2 As shown in (A), it corresponds to the average signal level of signal level V(+1 / 3) and signal level V(-1 / 3).

[0135] V2=(V(+1)-V(-1 / 3))×1 / 4+V(-1 / 3)

[0136] Comparator circuit 1309 compares signal level V1 and signal level V2 and outputs the comparison result signal. Control circuit 701, based on the comparison result signal from comparator circuit 1309, controls the current of variable current sources 341-344 within driver circuit 300a by adjusting a code to bring signal level V1 close to signal level V2. If signal level V1 and signal level V2 are the same, control circuit 701 fixes the adjustment code. The variable current sources 341-344 within driver circuit 300a control the current according to the adjustment code. Thus, the RLM of the four-valued signal output by driver circuit 300a is adjusted to above 0.95.

[0137] Figure 14 Yes Figure 13The diagram shows an example configuration of the voltage holding circuit 1303. The voltage holding circuit 1303 includes resistors 1401 and 1403 and capacitors 1402 and 1404, holding the signal level V(+1) at node N1 and the signal level V(-1) at node N2, and outputting signal levels V(+1) and V(-1). For example, resistors 1401 and 1403 are each 20kΩ, and capacitors 1402 and 1404 are each 50pF. Resistors 1401 and 1403 can also be the cutoff resistors of a field-effect transistor. Figure 13 The voltage holding circuit 1304 has the same configuration as the voltage holding circuit 1303.

[0138] Figure 15 This is a flowchart illustrating the control method of the integrated circuit 100 according to this embodiment. In step S1501, the integrated circuit 100 performs a test mode preparation process. The integrated circuit 100 activates the driver circuit 300a. The control circuit 701 resets the adjustment code to an initial value and outputs the adjustment code of the initial value to the variable current sources 341 to 344. For example, the initial value of the adjustment code is a minimum value. The variable current sources 341 to 344 cause current to flow based on the adjustment code.

[0139] Next, in step S1502, the control circuit 701 increments the adjustment code by 1 and outputs the calculated adjustment code to the variable current sources 341-344. The variable current sources 341-344 then cause current to flow based on the adjustment code.

[0140] Next, in step S1503, the control circuit 701 as follows: Figure 3 As shown in (A), the state of field-effect transistors 311-314 and 321-324, corresponding to the two parallel data bits "11," is controlled to turn on switch 1301 and turn off switch 1302. This causes driver circuit 300a to output a signal level V(+1) from node N1 and a signal level V(-1) from node N2. Voltage holding circuit 1303 holds the signal level V(+1) at node N1 and the signal level V(-1) at node N2. Subsequently, control circuit 701 turns off switch 1301. Voltage holding circuit 1303 outputs the held signal level V(+1) and signal level V(-1). Node N12 outputs the aforementioned signal level V1.

[0141] Next, in step S1504, the control circuit 701 as follows: Figure 3As shown in (B), the state of field-effect transistors 311-314 and 321-324, corresponding to the two parallel data bits "10," is controlled to open switch 1301 and close switch 1302. This causes driver circuit 300a to output a signal level V(+1 / 3) from node N1 and a signal level V(-1 / 3) from node N2. Voltage holding circuit 1304 holds the signal level V(+1 / 3) at node N1 and the signal level V(-1 / 3) at node N2. Subsequently, control circuit 701 opens switch 1302. Voltage holding circuit 1304 outputs the held signal levels V(+1 / 3) and V(-1 / 3). Node N13 outputs the aforementioned signal level V2.

[0142] Next, in step S1505, the control circuit 701 determines whether signal level V1 and signal level V2 are the same based on the comparison result signal from the comparison circuit 1309. If signal level V1 is not the same as signal level V2, the control circuit 701 returns to step S1502 and repeats the above process. As the adjustment code increases, signal level V1 approaches signal level V2. If the control circuit 701 determines that signal level V1 and signal level V2 are the same, it proceeds to step S1506.

[0143] In step S1506, the control circuit 701 determines the current adjustment code as the adjustment code for normal mode, outputs the normal mode adjustment code to the variable current sources 341-344 in the driver circuit 300a, causes switches 1301 and 1302 to open, and ends the test mode processing. Subsequently, the integrated circuit 100 performs normal mode processing. The variable current sources 341-344 in the driver circuit 300a respectively cause current to flow based on the normal mode adjustment code.

[0144] The driver circuit 300a can output equally spaced signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) based on an adjustment code in a normal mode. This improves the Regeneration Memory Level (RLM) of the quaternary signal output by the driver circuit 300a. By increasing the RLM, the quality of the quaternary signal is improved, and the receiving circuit 133 can reduce the regeneration error of the quaternary signal.

[0145] Furthermore, in step S1506, the control circuit 701 can also swap the + and - input terminals of the comparator circuit 1309, reset the adjustment code to its maximum value, and repeatedly subtract 1 from the adjustment code until the signal levels V1 and V2 are the same, thus determining the adjustment code for the normal mode. Then, the control circuit 701 determines the final adjustment code for the normal mode by averaging the normal mode adjustment code obtained by increasing the adjustment code from the minimum value and the normal mode adjustment code obtained by decreasing the adjustment code from the maximum value. This reduces the error caused by the offset of the comparator circuit 1309. This process can also be applied to... Figure 8 The processing.

[0146] exist Figure 7 In some cases, errors may occur in the transistor characteristics of the driver circuit 300a and the replication circuit 702. When this error occurs, the RLM of the four-valued signal output by the driver circuit 300a decreases. According to this embodiment, since the replication circuit 702 is not used, it is possible to prevent the decrease in the RLM of the four-valued signal output by the driver circuit 300a based on the replication circuit 702.

[0147] (Seventh Implementation)

[0148] Figure 16 This is a diagram showing an example of the configuration of the signal output circuit 112 according to the seventh embodiment. Figure 16 The signal output circuit 112 is relative to Figure 13 The signal output circuit 112 has been modified by removing switches 1301 and 1302, voltage holding circuits 1303 and 1304, resistors 1305 to 1308, and comparator circuit 1309, and adding switch 1601 and analog-to-digital converter (ADC) 1602. Switch 1601 and ADC 1602 function as a first detection circuit, for example, to detect signal levels V(-1) and V(+1) among the signal levels corresponding to the four-valued signals. Furthermore, switch 1601 and ADC 1602 function as a second detection circuit, for example, to detect signal levels V(-1 / 3) and V(+1 / 3) among the signal levels corresponding to the four-valued signals.

[0149] Next, the method for determining the adjustment codes of the variable current sources 341 to 344 within the driver circuit 300a will be explained. First, the control circuit 701 sets the adjustment codes of the variable current sources 341 to 344 to initial values. Next, the control circuit 701... Figure 3As shown in (A), the field-effect transistors 311-314 and 321-324 are controlled to correspond to the two parallel data bits "11", and switch 1601 is turned on. This causes driver circuit 300a to output a signal level V(+1) from node N1 and a signal level V(-1) from node N2. Analog-to-digital converter 1602 converts the signal levels V(+1) at node N1 and V(-1) at node N2 from analog values ​​to digital values, respectively. Control circuit 701 maintains the signal levels V(+1) and V(-1) of the digital values ​​output by analog-to-digital converter 1602. Subsequently, control circuit 701 turns off switch 1601.

[0150] Next, the control circuit 701 as follows Figure 3 As shown in (B), the field-effect transistors 311-314 and 321-324 are controlled to correspond to the two parallel data bits "10", and switch 1601 is turned on. This causes driver circuit 300a to output a signal level V(+1 / 3) from node N1 and a signal level V(-1 / 3) from node N2. Analog-to-digital converter 1602 converts the signal levels V(+1 / 3) at node N1 and V(-1 / 3) at node N2 from analog values ​​to digital values, respectively. Control circuit 701 maintains the signal levels V(+1 / 3) and V(-1 / 3) of the digital values ​​output by analog-to-digital converter 1602. Subsequently, control circuit 701 turns off switch 1601.

[0151] Next, the control circuit 701 performs operations based on the signal levels V(+1), V(-1), V(+1 / 3), and V(-1 / 3) of the digital values. Figure 13 The digital processing corresponding to resistors 1305-1308 and comparator circuit 1309 compares signal levels V1 and V2. Afterwards, control circuit 701 performs the same processing as in the sixth embodiment.

[0152] Figure 17 This is a flowchart illustrating the control method of the integrated circuit 100 according to this embodiment. In step S1701, the integrated circuit 100 performs a test mode preparation process. The integrated circuit 100 activates the driver circuit 300a. The control circuit 701 resets the adjustment code to an initial value and outputs the adjustment code of the initial value to the variable current sources 341 to 344. For example, the initial value of the adjustment code is a minimum value. The variable current sources 341 to 344 cause current to flow based on the adjustment code.

[0153] Next, in step S1702, the control circuit 701 increments the adjustment code by 1 and outputs the calculated adjustment code to the variable current sources 341-344. The variable current sources 341-344 then cause current to flow based on the adjustment code.

[0154] Next, in step S1703, the control circuit 701 as follows: Figure 3 As shown in (A), the field-effect transistors 311-314 and 321-324 are controlled to correspond to the two parallel data bits "11", and switch 1601 is turned on. This causes driver circuit 300a to output a signal level V(+1) from node N1 and a signal level V(-1) from node N2. Analog-to-digital converter 1602 converts the signal levels V(+1) at node N1 and V(-1) at node N2 from analog values ​​to digital values, respectively. Control circuit 701 maintains the signal levels V(+1) and V(-1) of the digital values ​​output by analog-to-digital converter 1602. Subsequently, control circuit 701 turns off switch 1601.

[0155] Next, in step S1704, the control circuit 701 as follows: Figure 3 As shown in (B), the field-effect transistors 311-314 and 321-324 are controlled to correspond to the two parallel data bits "10", and switch 1601 is turned on. This causes driver circuit 300a to output a signal level V(+1 / 3) from node N1 and a signal level V(-1 / 3) from node N2. Analog-to-digital converter 1602 converts the signal levels V(+1 / 3) at node N1 and V(-1 / 3) at node N2 from analog values ​​to digital values, respectively. Control circuit 701 maintains the signal levels V(+1 / 3) and V(-1 / 3) of the digital values ​​output by analog-to-digital converter 1602. Subsequently, control circuit 701 turns off switch 1601.

[0156] Next, in step S1705, the control circuit 701 and Figure 13 Similarly, signal level V1 is calculated based on the digital signal levels V(+1 / 3) and V(-1), and signal level V2 is calculated based on the digital signal levels V(+1) and V(-1 / 3). Next, control circuit 701 determines whether signal level V1 and signal level V2 are the same. If signal level V1 and signal level V2 are not the same, control circuit 701 returns to step S1702 and repeats the above process. As the adjustment code increases, signal level V1 gradually approaches signal level V2. If control circuit 701 determines that signal level V1 and signal level V2 are the same, it proceeds to step S1706.

[0157] In step S1706, the control circuit 701 determines the current adjustment code as the adjustment code for normal mode, outputs the normal mode adjustment code to the variable current sources 341-344 in the driver circuit 300a, causes the switch 1601 to open, and ends the test mode processing. Subsequently, the integrated circuit 100 performs normal mode processing. The variable current sources 341-344 in the driver circuit 300a respectively cause current to flow based on the normal mode adjustment code.

[0158] The driver circuit 300a can output equally spaced signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) based on an adjustment code in a normal mode. This improves the Regeneration Memory Level (RLM) of the quaternary signal output by the driver circuit 300a. By increasing the RLM, the quality of the quaternary signal is improved, and the receiving circuit 133 can reduce the regeneration error of the quaternary signal.

[0159] (Eighth Implementation Method)

[0160] Figure 18 This is a diagram showing an example of the configuration of the signal output circuit 112 according to the eighth embodiment. Figure 18 The signal output circuit 112 is relative to Figure 13 The signal output circuit 112 omits voltage holding circuits 1303 and 1304, resistors 1305 to 1308, and comparator circuit 1309, and adds operational amplifiers 1803 and 1804, resistors 1805 to 1808, and analog-to-digital converters (ADCs) 1809 and 1810. Switch 1301, operational amplifier 1803, and resistors 1805 and 1807 function as a first detection circuit, for example, to detect signal levels V(-1) and V(+1) among the four-valued signal levels, outputting the difference between signal levels V(+1) and V(-1). Furthermore, switch 1302, operational amplifier 1804, and resistors 1806 and 1808 function as a second detection circuit, for example, to detect signal levels V(-1 / 3) and V(+1 / 3) among the four-valued signal levels, outputting the difference between signal levels V(+1 / 3) and V(-1 / 3).

[0161] Next, the method for determining the adjustment codes of the variable current sources 341 to 344 within the driver circuit 300a will be explained. First, the control circuit 701 sets the adjustment codes of the variable current sources 341 to 344 to initial values. Next, the control circuit 701... Figure 3As shown in (A), the state of field-effect transistors 311-314 and 321-324, corresponding to the two parallel data "11", is controlled to turn on switch 1301 and turn off switch 1302. In this way, driver circuit 300a outputs signal level V(+1) from node N1 and signal level V(-1) from node N2.

[0162] Resistor 1805 is connected between the + input terminal and the output terminal of operational amplifier 1803. Resistor 1807 is connected between the - input terminal and the reference potential node of operational amplifier 1803. Operational amplifier 1803 receives the signal level V(+1) at node N1 and the signal level V(-1) at node N2, and outputs the signal level V(+1) and the difference V(-1). Analog-to-digital converter 1809 converts the differential V(+1)-V(-1) output from operational amplifier 1803 from analog to digital. Control circuit 701 holds the digital value V(+1)-V(-1) output from analog-to-digital converter 1809.

[0163] Next, the control circuit 701 as follows Figure 3 As shown in (B), the state of field-effect transistors 311-314 and 321-324, corresponding to the two parallel data "10", is controlled to open switch 1301 and close switch 1302. In this way, driver circuit 300a outputs signal level V(+1 / 3) from node N1 and signal level V(-1 / 3) from node N2.

[0164] Resistor 1806 is connected between the + input terminal and the output terminal of operational amplifier 1804. Resistor 1808 is connected between the - input terminal and the reference potential node of operational amplifier 1804. Operational amplifier 1804 receives the signal level V(+1 / 3) at node N1 and the signal level V(-1 / 3) at node N2, and outputs the signal level V(+1 / 3) and the difference V(-1 / 3) - V(-1 / 3). Analog-to-digital converter 1810 converts the differential V(+1 / 3) - V(-1 / 3) output from operational amplifier 1804 from analog to digital. Control circuit 701 holds the digital value V(+1 / 3) - V(-1 / 3) output from analog-to-digital converter 1810.

[0165] Next, control circuit 701 multiplies the digital value V(+1 / 3) - V(-1 / 3) by three, resulting in the digital value {V(+1 / 3) - V(-1 / 3)} × 3. For example... Figure 2 As shown in (A), the numerical value {V(+1 / 3)-V(-1 / 3)}×3 corresponds to the difference V(+1)-V(-1).

[0166] Control circuit 701 compares the aforementioned digital value V(+1) - V(-1) with the digital value {V(+1 / 3) - V(-1 / 3)} × 3. Then, control circuit 701 controls the current of variable current sources 341 to 344 within driver circuit 300a by adjusting a code to bring the digital value V(+1) - V(-1) close to the digital value {V(+1 / 3) - V(-1 / 3)} × 3. If the digital value V(+1) - V(-1) is the same as the digital value {V(+1 / 3) - V(-1 / 3)} × 3, control circuit 701 fixes the adjustment code. The variable current sources 341 to 344 within driver circuit 300a control the current according to the adjustment code. As a result, the RLM of the four-value signal output by driver circuit 300a is adjusted to above 0.95.

[0167] Figure 19 This is a flowchart illustrating the control method of the integrated circuit 100 according to this embodiment. In step S1901, the integrated circuit 100 performs a test mode preparation process. The integrated circuit 100 activates the driver circuit 300a. The control circuit 701 resets the adjustment code to an initial value and outputs the adjustment code of the initial value to the variable current sources 341 to 344. For example, the initial value of the adjustment code is a minimum value. The variable current sources 341 to 344 cause current to flow based on the adjustment code.

[0168] Next, in step S1902, the control circuit 701 increments the adjustment code by 1 and outputs the calculated adjustment code to the variable current sources 341-344. The variable current sources 341-344 then cause current to flow based on the adjustment code.

[0169] Next, in step S1903, the control circuit 701 as follows: Figure 3 As shown in (A), the state of field-effect transistors 311-314 and 321-324, corresponding to the two parallel data bits "11," is controlled to turn on switch 1301 and turn off switch 1302. This causes driver circuit 300a to output a signal level V(+1) from node N1 and a signal level V(-1) from node N2. Operational amplifier 1803 receives the signal levels V(+1) from node N1 and V(-1) from node N2 and outputs the signal levels V(+1) and the difference V(-1) between V(-1). Analog-to-digital converter 1809 converts the differential V(+1)-V(-1) output from operational amplifier 1803 from analog to digital. Control circuit 701 holds the digital value V(+1)-V(-1) output from analog-to-digital converter 1809 as the digital value V1. Then, control circuit 701 turns off switch 1301.

[0170] Next, in step S1904, the control circuit 701 as follows: Figure 3As shown in (B), the state of field-effect transistors 311-314 and 321-324, corresponding to the two parallel data bits "10," is controlled to open switch 1301 and close switch 1302. This causes driver circuit 300a to output a signal level V(+1 / 3) from node N1 and a signal level V(-1 / 3) from node N2. Operational amplifier 1804 receives the signal levels V(+1 / 3) from node N1 and V(-1 / 3) from node N2 and outputs the signal levels V(+1 / 3) and the difference between V(-1 / 3) and V(+1 / 3). Analog-to-digital converter 1810 converts the differential V(+1 / 3)-V(-1 / 3) output from operational amplifier 1804 from analog to digital. Control circuit 701 maintains the digital value V(+1 / 3)-V(-1 / 3) output from analog-to-digital converter 1810. Then, control circuit 701 triples the digital value V(+1 / 3) - V(-1 / 3) and holds the digital value {V(+1 / 3) - V(-1 / 3)} × 3 as the digital value V2. Afterwards, control circuit 701 opens switch 1302.

[0171] Next, in step S1905, the control circuit 701 determines whether the digital value V1 and the digital value V2 are the same. If the digital values ​​V1 and V2 are not the same, the control circuit 701 returns to step S1902 and repeats the above process. As the adjustment code increases, the digital value V1 gradually approaches the digital value V2. If the control circuit 701 determines that the digital values ​​V1 and V2 are the same, it proceeds to step S1906.

[0172] In step S1906, the control circuit 701 determines the current adjustment code as the normal mode adjustment code and outputs the normal mode adjustment code to the variable current sources 341-344 in the driver circuit 300a, causing switches 1301 and 1302 to open and ending the test mode processing. Subsequently, the integrated circuit 100 performs normal mode processing. The variable current sources 341-344 in the driver circuit 300a respectively cause current to flow based on the normal mode adjustment code.

[0173] The driver circuit 300a can output equally spaced signal levels V(-1), V(-1 / 3), V(+1 / 3), and V(+1) based on an adjustment code in a normal mode. This improves the Regeneration Memory Level (RLM) of the quaternary signal output by the driver circuit 300a. By increasing the RLM, the quality of the quaternary signal is improved, and the receiving circuit 133 can reduce the regeneration error of the quaternary signal.

[0174] Furthermore, the above embodiments are merely illustrative examples of implementing the present invention and are not intended to limit the scope of the invention. That is, the present invention can be implemented in various ways without departing from its technical concept or its main features.

[0175]

[0176] 112…Signal output circuit, 330a…Driver circuit, 701…Control circuit, 702…Copy circuit, 703…Comparison circuit, 704…Control circuit, 705…First copy circuit section, 706…Second copy circuit section, 707, 708…Variable current source, 1301, 1302…Switch, 1303, 1304…Voltage holding circuit, 1305~1308…Resistors, 1309…Comparison circuit.

Claims

1. A signal output circuit, wherein, have: A driver circuit that has a variable current source and outputs a multi-value signal; The first detection circuit detects the signal level of a first subset of the multiple signal levels corresponding to the multi-value signal output from the driver circuit. The second detection circuit detects the signal level of a second subset of the multiple signal levels corresponding to the multi-value signal output from the driver circuit. as well as The control circuit controls the characteristics of the driver circuit based on the signal levels of the first subset and the second subset. The control circuit described above controls the characteristics of the variable current source based on the signal levels of the first subset and the second subset.

2. The signal output circuit according to claim 1, wherein, The above driver circuit outputs a four-value signal. The first detection circuit described above detects the signal level of a first subset of the first to fourth signal levels corresponding to the four-valued signals. The second detection circuit detects the signal level of the second subset of the first to fourth signal levels corresponding to the four-valued signals.

3. The signal output circuit according to claim 2, wherein, The first detection circuit detects and holds the first signal level and the fourth signal level, which is lower than the first signal level. The second detection circuit detects and holds the second signal level, which is lower than the first signal level and higher than the fourth signal level, and the third signal level, which is lower than the second signal level and higher than the fourth signal level. The control circuit described above controls the current of the variable current source based on the first to fourth signal levels.

4. The signal output circuit according to claim 3, wherein, A first intermediate voltage level is generated based on the fourth signal level held by the first detection circuit and the second signal level held by the second detection circuit. A second intermediate voltage level is generated based on the first signal level held by the first detection circuit and the third signal level held by the second detection circuit. The control circuit controls the current of the variable current source in such a way that the first intermediate voltage level is close to the second intermediate voltage level.

5. The signal output circuit according to claim 2, wherein, The first detection circuit described above converts the first signal level and the fourth signal level from analog values ​​to digital values. The second detection circuit described above converts the second signal level and the third signal level from analog values ​​to digital values. The control circuit controls the current of the variable current source based on the first signal level and the fourth signal level of the digital value converted by the first detection circuit, and the second signal level and the third signal level of the digital value converted by the second detection circuit.

6. The signal output circuit according to claim 2, wherein, The first detection circuit outputs the difference between the first signal level and the fourth signal level. The second detection circuit outputs the difference between the second signal level and the third signal level. The control circuit controls the current of the variable current source based on the difference between the first signal level and the fourth signal level, and the difference between the second signal level and the third signal level.

7. A transmitting circuit, wherein, have: A multiplexer that multiplexes the first number of parallel data into a second number of parallel data that is fewer than the first number; and The signal output circuit receives the parallel data of the second bit mentioned above. The above signal output circuit has: The driver circuit has a variable current source and outputs a multi-value signal; The first detection circuit detects the signal level of a first subset of the multiple signal levels corresponding to the multi-value signal output from the driver circuit. The second detection circuit detects the signal level of a second subset of the multiple signal levels corresponding to the multi-value signal output from the driver circuit. as well as The control circuit controls the characteristics of the driver circuit based on the signal levels of the first subset and the second subset. The control circuit described above controls the characteristics of the variable current source based on the signal levels of the first subset and the second subset.

8. The transmitting circuit according to claim 7, wherein, The above driver circuit outputs a four-value signal. The first detection circuit described above detects the signal level of a first subset of the first to fourth signal levels corresponding to the four-valued signals. The second detection circuit detects the signal level of the second subset of the first to fourth signal levels corresponding to the four-valued signals.

9. The transmitting circuit according to claim 8, wherein, The first detection circuit detects and holds the first signal level and the fourth signal level, which is lower than the first signal level. The second detection circuit detects and holds the second signal level, which is lower than the first signal level and higher than the fourth signal level, and the third signal level, which is lower than the second signal level and higher than the fourth signal level. The control circuit described above controls the current of the variable current source based on the first to fourth signal levels.

10. The transmitting circuit according to claim 9, wherein, A first intermediate voltage level is generated based on the fourth signal level held by the first detection circuit and the second signal level held by the second detection circuit. A second intermediate voltage level is generated based on the first signal level held by the first detection circuit and the third signal level held by the second detection circuit. The control circuit controls the current of the variable current source in such a way that the first intermediate voltage level is close to the second intermediate voltage level.

11. The transmitting circuit according to claim 8, wherein, The first detection circuit described above converts the first signal level and the fourth signal level from analog values ​​to digital values. The second detection circuit described above converts the second signal level and the third signal level from analog values ​​to digital values. The control circuit controls the current of the variable current source based on the first signal level and the fourth signal level of the digital value converted by the first detection circuit, and the second signal level and the third signal level of the digital value converted by the second detection circuit.

12. The transmitting circuit according to claim 8, wherein, The first detection circuit outputs the difference between the first signal level and the fourth signal level. The second detection circuit outputs the difference between the second signal level and the third signal level. The control circuit controls the current of the variable current source based on the difference between the first signal level and the fourth signal level, and the difference between the second signal level and the third signal level.

13. An integrated circuit, wherein, have: Internal circuitry that generates parallel data for the first digit; and The transmitting circuit receives the parallel data of the first digit mentioned above. The above-mentioned transmitting circuit has: A multiplexer that multiplexes the first number of parallel data into a second number of parallel data that is fewer than the first number; and The signal output circuit receives the parallel data of the second bit mentioned above. The above signal output circuit has: The driver circuit has a variable current source and outputs a multi-value signal; The first detection circuit detects the signal level of a first subset of the multiple signal levels corresponding to the multi-value signal output from the driver circuit. The second detection circuit detects the signal level of a second subset of the multiple signal levels corresponding to the multi-value signal output from the driver circuit. as well as The control circuit controls the characteristics of the driver circuit based on the signal levels of the first subset and the second subset. The control circuit described above controls the characteristics of the variable current source based on the signal levels of the first subset and the second subset.

14. The integrated circuit according to claim 13, wherein, The above driver circuit outputs a four-value signal. The first detection circuit described above detects the signal level of a first subset of the first to fourth signal levels corresponding to the four-valued signals. The second detection circuit detects the signal level of the second subset of the first to fourth signal levels corresponding to the four-valued signals.

15. The integrated circuit according to claim 14, wherein, The first detection circuit detects and maintains the first signal level and the fourth signal level. The second detection circuit detects and maintains the second signal level and the third signal level. The control circuit described above controls the current of the variable current source based on the first to fourth signal levels.

16. The integrated circuit according to claim 15, wherein, A first intermediate voltage level is generated based on the fourth signal level held by the first detection circuit and the second signal level held by the second detection circuit. A second intermediate voltage level is generated based on the first signal level held by the first detection circuit and the third signal level held by the second detection circuit. The control circuit controls the current of the variable current source in such a way that the first intermediate voltage level is close to the second intermediate voltage level.

17. The integrated circuit according to claim 14, wherein, The first detection circuit described above converts the first signal level and the fourth signal level from analog values ​​to digital values. The second detection circuit described above converts the second signal level and the third signal level from analog values ​​to digital values. The control circuit controls the current of the variable current source based on the first signal level and the fourth signal level of the digital value converted by the first detection circuit, and the second signal level and the third signal level of the digital value converted by the second detection circuit.

18. The integrated circuit according to claim 14, wherein, The first detection circuit outputs the difference between the first signal level and the fourth signal level. The second detection circuit outputs the difference between the second signal level and the third signal level. The control circuit controls the current of the variable current source based on the difference between the first signal level and the fourth signal level, and the difference between the second signal level and the third signal level.

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