A chip attack detection circuit

Abstract

This application relates to a chip attack detection circuit, which includes an attack detection module and a calibration module connected together. The attack detection module includes a first delay chain and an alarm unit. The first delay chain is connected to a clock port and is used to receive a clock signal output from the clock port. When the clock signal changes, the first propagation time of the first delay chain changes, triggering the alarm unit to output an alarm signal. The calibration module is used to calibrate the first delay chain so that the first propagation time tends to the initial propagation time of the first delay chain. This solves the problem of low detection accuracy in detection circuits used for detecting voltage / clock fault injection attacks on chips, and improves the detection accuracy of the chip attack detection circuit.

Description

Technical Field

[0001] This application relates to the field of electronics, and in particular to a chip attack detection circuit. Background Technology

[0002] With the continuous upgrading of electronic devices, most devices employ cryptographic protection measures to ensure their secure and reliable operation. Fault injection attacks are a common method to compromise cryptographic security measures. These attacks bypass / disrupt secure operations, modify registers, and execute illegal operations by forcibly implementing faulty behaviors within the attacked device.

[0003] Voltage / clock fault injection attacks are non-intrusive fault injection attacks that do not require damage to the attacked device. They can be achieved by altering the device's power / clock input, thus offering excellent stealth. Once a successful attack is launched, the attacker can obtain the user's private data or perform illegal operations.

[0004] Currently, most related electronic devices use analog sensors, employing phase-locked loop (PLL) based sensors to detect voltage and compare thresholds to determine if the operating conditions of the chip attack detection circuit are abnormal. Alternatively, they utilize digital sensors based on configurable delay blocks (CDBs) to detect the presence of voltage / clock fault injection. However, the chip attack detection circuits for voltage / clock fault injection attacks in these technologies suffer from low detection accuracy due to component aging.

[0005] There is currently no effective solution to the problem of low detection accuracy of chip attack detection circuits for voltage / clock fault injection attacks in related technologies. Summary of the Invention

[0006] This embodiment provides a chip attack detection circuit to solve the problem of low detection accuracy of chip attack detection circuits for voltage / clock fault injection attacks in related technologies.

[0007] Firstly, this embodiment provides a chip attack detection circuit, including: an attack detection module and a calibration module, wherein the attack detection module is connected to the calibration module; wherein,

[0008] The attack detection module includes a first delay chain and an alarm unit. The first delay chain is connected to a clock port and is used to receive the clock signal output by the clock port. When the clock signal changes, the signal output by the first delay chain changes, triggering the alarm unit to output an alarm signal.

[0009] The calibration module is used to calibrate the first delay chain so that the first propagation time of the signal output by the first delay chain tends to the initial propagation time.

[0010] In some embodiments, the signal changes output by the first delay chain include:

[0011] The first propagation time variation, and / or the period variation of the signal output by the first delay chain.

[0012] In some embodiments, the calibration module includes a first calibration unit connected to the first delay chain, used to calibrate the first propagation time based on a received calibration signal; or,

[0013] The calibration module includes a first calibration unit and a second calibration unit. The first calibration unit is connected to the first delay chain and the second calibration unit, respectively. The first calibration unit is used to calibrate the first propagation time according to the received calibration signal. The second calibration unit is used to calibrate the second propagation time of the second calibration unit. The sum of the second propagation time and the first propagation time is the period of the clock signal.

[0014] In some embodiments, the first calibration unit includes: a second delay chain, a first flip-flop, a second flip-flop, and a multiplexer; wherein,

[0015] The first flip-flop is connected to the clock port and the second delay chain respectively. The second delay chain is connected to the first delay chain and the second flip-flop. The second flip-flop is connected to the first delay chain. The first delay chain and the second delay chain each include at least one delay unit. The delay unit includes a buffer and a multiplexer.

[0016] The control terminal of the multiplexer is used to receive the calibration signal. The input terminal of the multiplexer is connected to the clock port and the second delay chain, respectively. The output terminal of the multiplexer is connected to the first delay chain and the second trigger, respectively.

[0017] In some embodiments, the first delay chain and the second delay chain each include at least one delay unit, the delay unit including a buffer and a multiplexer.

[0018] In some embodiments, the first flip-flop includes a clock input, a data input, a main output, and a secondary output; the second flip-flop includes a clock input, a data input, a main output, and a secondary output; and the third flip-flop includes a clock input, a data input, and a main output.

[0019] The clock input terminal of the first flip-flop is connected to the clock port, the data input terminal of the first flip-flop is connected to the secondary output terminal of the first flip-flop, and the main output terminal of the first flip-flop is connected to the input terminal of the second delay chain.

[0020] The clock input of the second flip-flop is connected to the output of the buffer, the data input of the second flip-flop is connected to the input of the first delay chain, and the main output of the second flip-flop is connected to the control terminal of the multiplexer.

[0021] In some embodiments, the first calibration unit calibrates the first propagation time, including:

[0022] When the calibration signal is a first preset signal, the second trigger outputs a selection signal according to the second propagation time of the second delay chain, and the first delay chain modifies the first propagation time according to the selection signal, wherein the sum of the second propagation time and the first propagation time is the period of the clock signal.

[0023] In some embodiments, the first calibration unit further includes a first transistor, a second transistor, and a first logic gate; wherein the first transistor and the second transistor are respectively connected to the second delay chain, the output terminal of the first logic gate is connected to the second transistor, and the input terminal of the first logic gate is connected to the input terminal of the first transistor, for receiving calibration signals;

[0024] When the calibration signal is the second preset signal, the first calibration unit does not perform calibration operation and controls the power supply terminal and ground terminal of the second delay chain to be disconnected through the first transistor, the second transistor, and the first logic gate.

[0025] In some embodiments, the second calibration unit includes a decoder that is correspondingly connected to a delay unit in the second delay chain.

[0026] In some embodiments, the alarm unit includes: a third flip-flop, a fourth flip-flop, and a second logic gate; wherein,

[0027] The input terminal of the third flip-flop is connected to the output terminal of the first delay chain and the clock port, respectively. The input terminal of the fourth flip-flop is connected to the output terminal of the first delay chain and the clock port, respectively. The output terminals of the third flip-flop and the fourth flip-flop are connected to the input terminal of the second logic gate, respectively.

[0028] In some embodiments, the third and fourth flip-flops each include a clock input, a data input, a main output, and a secondary output, wherein the signals output by the main output and the secondary output are complementary; wherein,

[0029] The clock input of the third flip-flop is connected to the output of the first delay chain, the data input of the third flip-flop is connected to the clock port, and the main output of the third flip-flop is connected to the input of the second logic gate.

[0030] The clock input terminal of the fourth flip-flop is connected to the clock port, the data input terminal of the fourth flip-flop is connected to the output terminal of the first delay chain, and the secondary output terminal of the fourth flip-flop is connected to the input terminal of the second logic gate.

[0031] Compared with related technologies, the chip attack detection circuit provided in this embodiment includes an attack detection module and a calibration module, with the attack detection module connected to the calibration module. The attack detection module includes a first delay chain and an alarm unit. The first delay chain is connected to a clock port and is used to receive a clock signal output from the clock port. When the clock signal changes, the first propagation time of the first delay chain changes, triggering the alarm unit to output an alarm signal. The calibration module is used to calibrate the first delay chain, making the first propagation time approach the initial propagation time of the first delay chain. This solves the problem of low detection accuracy in chip attack detection circuits used for detecting voltage / clock fault injection attacks, and improves the detection accuracy of the chip attack detection circuit.

[0032] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0033] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0034] Figure 1 This is a schematic diagram of the internal operation of the chip in the related technology;

[0035] Figure 2 This is a schematic diagram of a chip attack detection circuit according to an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the attack detection module and the first detection unit in one embodiment of this application;

[0037] Figure 4 This is a schematic diagram of the structure of the first calibration unit in one embodiment of this application;

[0038] Figure 5 This is a schematic diagram of the structure of the second calibration unit in one embodiment of this application;

[0039] Figure 6 This is a schematic diagram of the attack detection module in one embodiment of this application;

[0040] Figure 7 This is a block diagram of a chip attack detection circuit according to an embodiment of this application;

[0041] Figure 8 This is a preferred schematic diagram of a chip attack detection circuit according to one embodiment of this application;

[0042] Figure 9 This is a schematic diagram of the attack detection module when the target chip is working normally according to one embodiment of this application;

[0043] Figure 10 This is the principle of the attack detection module when the target chip is attacked, according to one embodiment of this application. Figure 1 ;

[0044] Figure 11 This is the principle of the attack detection module when the target chip is attacked, according to one embodiment of this application. Figure 2 ;

[0045] Figure 12 This is a schematic diagram of the first calibration unit in one embodiment of this application. Detailed Implementation

[0046] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0047] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning as understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these,” used in this application, do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to such processes, methods, products, or devices. The terms “connected,” “linked,” and “coupled,” used in this application, are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. The term “multiple” used in this application refers to two or more. The "and / or" operator describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: A alone, A and B simultaneously, and B alone. Typically, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," and "third," etc., used in this application are merely for distinguishing similar objects and do not represent a specific ordering of the objects.

[0048] In related technologies, chips typically use a common clock signal (clk) to synchronize their internal operations. Figure 1 This is a schematic diagram illustrating the internal operation of a chip in related technologies. For example... Figure 1 As shown, the cloud-like pattern represents certain combinational logic within the chip. This combinational logic can perform certain functions, including addition, subtraction, multiplication, and division. Electrical signals require a certain amount of time to pass through the combinational logic within the chip. Therefore, in the first approximation, the clock period (T) clk The time must be longer than the maximum data propagation time of the electrical signal through the combinational logic (D). pMax To ensure correct operation within the chip, the combinational logic is connected to two D flip-flops (DFFs) upstream and downstream. The upstream DFF provides the data to be processed, and the downstream DFF stores the processing result. At the rising edge of each clock signal, the DFF latches the current input signal and remains unchanged until the next rising edge of the clock. Therefore, to ensure normal operation of the chip, it needs to satisfy the timing constraint equation: T clk >D pMax +D clk2q +T setup -T skew Among them, D clk2q T represents the delay elapsed between the rising edge of the clock and the actual update of the register output;skew This refers to the possible skew or slight phase difference between the clock signals at the clock inputs of two different registers; T setup Setup time is the amount of time that the inputs to a D flip-flop must remain stable before the clock edge to ensure reliable operation.

[0049] Voltage / clock fault injection attacks target chips by violating timing constraints. Specifically, voltage fault injection attacks reduce the chip's supply voltage, slowing down its processing speed and increasing the target chip's maximum data propagation time (D). pMax Maximum data propagation time D pMax The increase in T leads to the original timing constraint equation T clk >D pMax +D clk2q +T setup -T skew When the right side of the inequality sign increases, the inequality sign inverts. Clock fault injection attacks modify the target chip's clock source, artificially adding a very short clock cycle, increasing the clock signal period T. clk Reduce the original timing constraint equation T clk >D pMax +D clk2q +T setup -T skew When the left side of the inequality sign becomes smaller, the inequality sign is reversed.

[0050] This embodiment provides a chip attack detection circuit. Figure 2 This is a schematic diagram of the chip attack detection circuit in this embodiment, as shown below. Figure 2 As shown, the chip attack detection circuit includes an attack detection module and a calibration module, with the attack detection module connected to the calibration module. The attack detection module includes a first delay chain and an alarm unit. The first delay chain is connected to a clock port and is used to receive the clock signal output by the clock port. When the clock signal changes, the signal output by the first delay chain changes, triggering the alarm unit to output an alarm signal.

[0051] This chip attack detection circuit is used to detect whether a target chip is subjected to a fault injection attack. The first delay chain in the attack detection module includes at least one delay unit composed of a buffer and a multiplexer. The first delay chain is equivalent to the combinational logic in the target chip; the clock signal level does not change after passing through the delay unit, but the clock signal requires a certain propagation time. The first propagation time is the propagation time required for the clock signal to pass through the first delay chain. This first propagation time is greater than the maximum data propagation time required for the electrical signal to pass through the combinational logic in the target chip. This ensures that when the target chip is subjected to a voltage / clock fault injection attack, the attack detection module will violate timing constraints before the target chip, thus achieving the effect of detecting the fault injection attack.

[0052] The alarm unit simultaneously receives the clock signal and the signal output from the first delay chain. When the target chip is subjected to a voltage fault injection attack, its supply voltage decreases, and the first propagation time increases. When subjected to a clock fault injection attack, a shorter clock cycle is introduced into the clock signal, and the period of the signal output from the first delay chain also changes accordingly. The alarm unit outputs an alarm signal based on the level changes of the clock signal and the signal output from the first delay chain.

[0053] The calibration module is used to calibrate the first delay chain, ensuring that the first propagation time of the signal output by the first delay chain approaches its initial propagation time. During use, the first delay chain may experience aging; after prolonged use, its first propagation time will gradually increase, causing it to violate timing constraints. Therefore, the calibration module is needed to correct the increased first propagation time due to aging, restoring it to its initial propagation time.

[0054] The aforementioned chip attack detection circuit detects the presence of fault injection attacks by detecting changes in the clock signal caused by voltage / clock fault injection attacks. A calibration module calibrates the first propagation time, preventing false alarm triggers due to aging of the attack detection module and its resulting increased first propagation time. This solves the problem of inaccurate detection of fault injection attacks by the chip attack detection circuit, increasing the accuracy of its detection results.

[0055] In some embodiments, the signal variation at the output of the first delay chain includes: a change in the first propagation time, and / or a change in the period of the signal at the output of the first delay chain.

[0056] When the target chip under test is subjected to a voltage fault injection attack, its supply voltage drops, slowing down its processing speed and increasing the first propagation time of the first delay chain. When the target chip under test is subjected to a clock fault injection attack, a shorter clock cycle is introduced into the clock signal. Because the first delay chain receives the clock signal, the period of the output signal also changes. Therefore, when the target chip is subjected to both voltage and clock fault injection attacks, the supply voltage drops, a shorter clock cycle is introduced into the clock signal, and the first propagation time and period of the output signal change.

[0057] In some embodiments, the calibration module includes a first calibration unit connected to a first delay chain, used to calibrate a first propagation time based on a received calibration signal; or, the calibration module includes a first calibration unit and a second calibration unit, the first calibration unit being connected to both the first delay chain and the second calibration unit, the first calibration unit being used to calibrate the first propagation time based on a received calibration signal, and the second calibration unit being used to calibrate a second propagation time of the second calibration unit, wherein the sum of the second propagation time and the first propagation time is the period of a clock signal.

[0058] The first calibration unit is used to calibrate the first propagation time that has increased due to long-term use in the first delay chain. Optionally, the first delay chain includes at least one delay unit consisting of a buffer and a two-way selector, and the first calibration unit is connected to the first delay chain and the two-way selector in each delay unit. The first calibration unit includes a second delay chain, which includes at least one delay unit consisting of a buffer and a two-way selector. By correcting the first propagation time that has increased due to aging through the first calibration unit, it maintains the initial propagation time set for the first delay chain, thereby improving the accuracy of the attack detection unit in detecting chip attacks.

[0059] The second calibration unit is used to configure the second propagation time of the first calibration unit. Optionally, the second calibration unit is connected to each delay unit in the second delay chain. The maximum data propagation time of the combinational logic of the target chip with different dynamic voltages and frequencies will change. In order to ensure that the attack detection module can meet the voltage and frequency adjustment requirements of the target chip, the first propagation time also needs to change with the maximum data propagation time. By connecting the second calibration unit with the first calibration unit, the second propagation time is configured, and the first propagation time is further calibrated by the first calibration unit, so that the attack detection unit can meet the detection requirements of the target chip under dynamic voltages and different frequencies.

[0060] In some embodiments, the first calibration unit includes a second delay chain, a first flip-flop, and a second flip-flop. The first flip-flop is connected to a clock port and the second delay chain, respectively. The second delay chain is connected to the first delay chain and the second flip-flop, and the second flip-flop is connected to the first delay chain. Each of the first and second delay chains includes at least one delay unit, which includes a buffer and a multiplexer. Optionally, in the delay unit, the input of the buffer and one input of the multiplexer are used to receive a clock signal, and the output of the buffer is connected to the other input of the multiplexer, which outputs the delayed signal. When the first and second delay chains include more than one delay unit, the multiple delay units are connected in series to form a delay chain, and the signal output by the previous delay unit is used as the input signal of the next delay unit.

[0061] The first flip-flop includes a clock input, a data input, a main output, and a secondary output. The clock input of the first flip-flop is connected to a clock port, the data input of the first flip-flop is connected to the secondary output of the first flip-flop, and the main output of the first flip-flop is connected to the input of the second delay chain.

[0062] Optionally, the first and second flip-flops are D flip-flops. The first flip-flop receives the clock signal and divides the clock signal clk, that is, it changes the period of the clock signal to twice its original value. The main output Q of the first flip-flop is connected to the input of the second delay chain, so that the divided clock signal is input to the second delay chain.

[0063] The second flip-flop includes a clock input, a data input, a main output, and a secondary output. The clock input of the second flip-flop is connected to the output of the buffer, the data input is connected to the input of the first delay chain, and the main output is connected to the control terminal of the multiplexer. The data input of the second flip-flop receives the signal output from the second delay chain. Each second flip-flop corresponds one-to-one with a delay unit in the first delay chain. The second flip-flop selects and corrects the delay unit connected to it based on the signal output from the second delay chain. By using multiple second flip-flops, the first propagation time of the first delay chain is corrected.

[0064] In some embodiments, the first calibration unit further includes a multiplexer, the control terminal of which is used to receive a calibration signal, the input terminal of which is connected to a clock port and a second delay chain, and the output terminal of which is connected to the first delay chain and the second trigger.

[0065] For example, Figure 3This is a schematic diagram of the attack detection module and the first detection unit in one embodiment of this application, as shown below. Figure 3 As shown, the multiplexer is a two-way selector. When the calibration signal is the first preset signal, the two-way selector connects to the output of the second delay chain, disconnects from the clock port, and outputs the signal output by the second delay chain. The first delay chain and the second flip-flop receive the signal output after frequency division by the first flip-flop and delay by the second delay chain. When the calibration signal is the second preset signal, the two-way selector connects to the clock port, disconnects from the output of the second delay chain, and outputs the clock signal output by the clock port.

[0066] In some embodiments, the first calibration unit calibrates the first propagation time by: when the calibration signal is a first preset signal, the second trigger outputs a selection signal according to the second propagation time of the second delay chain, and the first delay chain modifies the first propagation time according to the selection signal, wherein the sum of the second propagation time and the first propagation time is the period of the clock signal.

[0067] For example, the first flip-flop and the second flip-flop are D flip-flops, and the first propagation time is D. pMax* The second propagation time is D. pMax** The propagation time D of the second delay chain pMax** Satisfy: D pMax* +D pMax** =T clk , among which, T clk The clock signal period of the target chip is defined as follows: When the calibration signal is set to 1, the calibration signal is the first preset signal. The first flip-flop divides the clock signal, doubling the clock signal period. The divided clock signal passes through the second delay chain, which outputs the divided and delayed signal. The second flip-flop outputs a selection signal based on the signal from the second delay chain, selecting and modifying the connected delay unit, thereby controlling the first propagation time D. pMax* The calibration signal is set to 0. When the calibration signal is set to 0, the calibration signal is the second preset signal. The second trigger will not select the delay unit connected to it, and the first calibration unit will not perform calibration on the first propagation time.

[0068] In some embodiments, the first calibration unit further includes a first transistor, a second transistor, and a first logic gate; wherein the first transistor and the second transistor are respectively connected to a second delay chain, the output terminal of the first logic gate is connected to the second transistor, and the input terminal of the first logic gate is connected to the input terminal of the first transistor, for receiving a calibration signal. Where the calibration signal is a second preset signal, the first calibration unit does not perform a calibration operation and controls the power supply and ground terminals of the second delay chain to disconnect via the first transistor, the second transistor, and the first logic gate.

[0069] Figure 4 This is a schematic diagram of the structure of the first calibration unit in one embodiment of this application. The first transistor is an NMOS transistor, the second transistor is a PMOS transistor, and the first logic gate is a NOT gate. The NMOS transistor connects the delay unit of the second delay chain to the power supply terminal corresponding to that delay unit, and the PMOS transistor connects the delay unit of the second delay chain to the ground terminal corresponding to that delay unit. The calibration signal is input to the gate of the NMOS transistor and input to the gate of the PMOS transistor through the NOT gate. When the calibration signal is set to 0, the calibration signal is a second preset signal, and the first calibration unit does not perform a calibration operation. Simultaneously, according to the second preset signal, the NMOS transistor disconnects the connection between the delay unit of the second delay chain and the power supply terminal, and the PMOS transistor disconnects the connection between the delay unit of the second delay chain and the ground terminal, thereby ensuring that the calibration module's delay chain is not affected by aging issues when the detection module ages.

[0070] In some embodiments, the second calibration unit includes a decoder, which is correspondingly connected to the delay unit in the second delay chain.

[0071] Figure 5 This is a schematic diagram of the structure of the second calibration unit in one embodiment of this application, as shown below. Figure 5 As shown, the decoder includes input ports S1, S2, ..., Sn, and corresponding output ports D1, D2, ..., Dn. The decoder's output ports are connected to the control terminals of the two-way selectors in the second delay chain. When the target chip requires dynamic voltage and frequency adjustment, an adjustment signal is input through the decoder's input ports as needed, causing the decoder's output signal to select the corresponding delay unit and change the second propagation time D. pMax** Subsequently, the first propagation time D of the first delay chain is calibrated using the first calibration unit. pMax* Perform a calibration operation so that D pMax* +D pMax** =T clk This allows for modification of the first propagation time. It enables the target chip to perform dynamic voltage and frequency adjustment, i.e., the maximum data propagation time D. pMax Even under changing circumstances, the chip attack detection circuit remains applicable, meeting the dynamic voltage and frequency adjustment requirements of the target chip and expanding its application range.

[0072] In some embodiments, the alarm unit includes a third flip-flop, a fourth flip-flop, and a second logic gate. The input of the third flip-flop is connected to the output of a first delay chain and a clock port, respectively. The input of the fourth flip-flop is also connected to the output of the first delay chain and a clock port, respectively. The outputs of the third and fourth flip-flops are connected to the input of the second logic gate, respectively. The third and fourth flip-flops each include a clock input, a data input, a main output, and a secondary output, with the signals output by the main and secondary outputs being complementary. The clock input of the third flip-flop is connected to the output of the first delay chain, the data input of the third flip-flop is connected to the clock port, and the main output of the third flip-flop is connected to the input of the second logic gate. The clock input of the fourth flip-flop is connected to the clock port, the data input of the fourth flip-flop is connected to the output of the first delay chain, and the secondary output of the fourth flip-flop is connected to the input of the second logic gate.

[0073] For example, Figure 6 This is a schematic diagram of the attack detection module in one embodiment of this application, as shown below. Figure 6 As shown, the third and fourth flip-flops are D flip-flops, and the second logic gate is an OR gate. The third and fourth flip-flops are complementary. The clock signal output from the clock port serves as the input signal for both the third and fourth flip-flops, and the signal output from the first delay chain serves as both the clock signal for the third and fourth flip-flops. The third flip-flop outputs signal Q, and the fourth flip-flop outputs the inverted signal —Q—. The OR gate outputs an alarm signal based on the input signal Q and the signal —Q—. By using two complementary D flip-flops, the detection blind zone caused by the input signal output time not meeting the flip-flop setup time is effectively avoided. The attack detection module reduces the detection blind zone of the chip attack detection circuit, further improving the detection accuracy of the chip attack detection circuit.

[0074] In some of these embodiments, Figure 7 This is a block diagram of the chip attack detection circuit structure in this embodiment. The chip attack detection circuit consists of an attack detection module and a calibration module. The calibration module includes a first calibration unit and a second calibration unit. The second calibration unit is connected to the first calibration unit, and the first calibration unit is connected to the attack detection module. The second calibration unit is used to configure the second propagation time of the first calibration unit, and the first calibration module is used to calibrate the first propagation time of the attack detection module.

[0075] Figure 8 This is a preferred schematic diagram of the chip attack detection circuit in this embodiment, as shown below. Figure 8As shown, the attack detection unit includes a first delay chain, D flip-flops 1 and 2, and an OR gate. A delay unit is constructed from a buffer and a two-way selector; multiple delay units are connected in series to form the first delay chain. The clock signal serves as the input signal to D flip-flops 1 and the clock signal to D flip-flops 2. The output signal of the first delay chain serves as the clock signal to D flip-flops 1 and the input signal to D flip-flops 2. The Q output of D flip-flops 1 outputs signal Q1, and the Q output of D flip-flops 2... Output signal at the output terminal Signals Q1 and Q2 pass through an OR gate to generate a warning signal.

[0076] Figure 9 This is a schematic diagram of the attack detection module when the target chip is working normally in this embodiment, as shown below. Figure 9 As shown, clk is the clock signal, D_clk is the clock signal output from the first delay chain, and Q1 is the output signal of D flip-flop 1. This is the output signal of D flip-flop 2. Initially, the first propagation time D... pMax* =delay>D pMax D pMax `delay` represents the maximum data propagation time of the electrical signal through the combinational logic in the target chip, and `delay` represents the delay time generated after the clock signal passes through the first propagation chain. When the target chip is operating normally, the output signals of flip-flop 1 and flip-flop 2 are both low, and no warning signal is generated at this time.

[0077] When the target chip is subjected to a voltage fault injection attack, the attack detection module generates a warning signal. Figure 10 This describes the principle of the attack detection module when the target chip is attacked in this embodiment. Figure 1 .like Figure 10 As shown, upon receiving a voltage fault injection attack, the first propagation time of the first delay chain increases, and the first propagation time changes to... Figure 10 The part indicated by 'delay' means that when the rising edge of the clk signal arrives, flip-flop 2 of the D flip-flop latches the signal to a low level. When the D_clk rises to a high level, the attack detection module issues a warning signal. When the rising edge of D_clk arrives, D flip-flop 1 latches to a high level, and Q1 is at a high level.

[0078] When the target chip is subjected to a clock fault injection attack, the attack detection module generates a warning signal. Figure 11 This describes the principle of the attack detection module when the target chip is attacked in this embodiment. Figure 2 .like Figure 11 As shown, under a clock fault injection attack, the attacker artificially introduces a small clock cycle into the clock signal. When the rising edge of the clk signal arrives, D flip-flop 2 latches low. When the D_clk signal is high, a warning signal can be issued. When the rising edge of the D_clk signal arrives, D flip-flop 1 latches to a high level, and Q1 is high.

[0079] The first calibration unit includes a D flip-flop 3, a second delay chain, and multiple D flip-flops 4. Each delay unit consists of a buffer and a two-way selector, and the second delay chain is formed by cascading multiple delay units. In the initial configuration, the sum of the first propagation time of the attack detection module and the second propagation time of the first calibration unit is one clock cycle of the clock signal. The D flip-flops 4 and the delay units in the first delay chain are connected in a one-to-one correspondence. The first calibration module is connected to the attack detection module via a two-way selector, where the control terminal of the two-way selector 1 is used to receive the calibration signal.

[0080] When calibration of the attack detection module is required, the calibration signal is set to 1. The two-way selector 1 controls the connection between the first and second delay chains and disconnects from the clock port. The D flip-flop 3 receives the clock signal and divides it, doubling the period. The divided clock signal passes through the second delay chain and outputs a delayed signal. The delayed signal serves as the input signal for the first delay chain and multiple D flip-flops 4. The output of the buffer in the first delay chain is the clock signal for the corresponding connected D flip-flop 4. The output signal Q of the D flip-flop 4 serves as the selection signal for the corresponding two-way selector, thereby selecting the corresponding delay unit through the D flip-flop 4 and correcting the first propagation time of the first delay chain, thus achieving the calibration function of the attack detection module. After calibration, the aging calibration signal should be set to 0. The two-way selector 1 controls the disconnection between the first and second delay chains and connects to the clock port. The D flip-flop 4 does not select the corresponding delay unit, and the calibration function is not implemented.

[0081] Figure 12 This is a schematic diagram of the first calibration unit in this embodiment, as shown below. Figure 12 As shown. After prolonged use, the propagation time of combinational logic will gradually increase, that is, the first propagation time D of the first delay chain. pMax* It will gradually increase, potentially causing the detection module to falsely trigger warning signals. Therefore, it is necessary to correct the D value that increases due to aging. pMax* This keeps it at the initial propagation time. The second propagation time of the second delay chain is D. pMax** And satisfy D pMax* +D pMax** =T clk That is, the sum of the first propagation time and the second propagation time is one clock cycle of the clock signal. clk is the basic clock signal, and clk' is the clock signal after frequency division. When D... pMax** +D pMax** ≤T clkAt this time, the data input signal of D flip-flop 4 is clk', and the clock input signal of D flip-flop 4 is D_clk'. When the rising edge of D_clk' arrives, D flip-flop 4 latches to a high level, thus selecting the delay unit corresponding to D flip-flop 4; when D... pMax* +D pMax** >T clk At this time, the data input signal of D flip-flop 4 is clk', and the clock input signal is D_clk". When the rising edge of D_clk arrives, D flip-flop 4 latches to a low level, and the corresponding delay unit is not selected.

[0082] The second calibration module includes a decoder, with its output port connected one-to-one with the delay units in the second delay chain. The user selects the adjustment signal input to the decoder based on the dynamic voltage and frequency adjustment requirements of the target chip, and then selects the delay unit in the second delay chain through the decoder's output signal to adjust the second propagation time D of the second delay chain. pMax** After adjusting the second propagation time, the first propagation time D is adjusted using the first calibration unit. pMax* Perform calibration so that D pMax* +D pMax** =T clk This allows for modification of the first propagation time of the detection module, enabling the target chip to continue operating normally even under dynamic voltage and frequency adjustments.

[0083] In this embodiment, the attack detection module utilizes two D flip-flops working in a complementary manner, reducing the detection blind zone caused by the input signal duration not meeting the flip-flop setup time when the chip attack detection circuit detects fault injection attacks. The first calibration unit calibrates the first delay chain of the attack detection module, thereby solving the problem of false triggering of the warning signal due to changes in the first propagation time caused by the aging of the first delay chain. The second calibration unit dynamically adjusts the second propagation time, meeting the requirements of dynamic voltage and frequency adjustment of the chip and expanding the detection range.

[0084] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can reside in the same processor; or the above modules can be located in different processors in any combination.

[0085] It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. All other embodiments derived by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0086] Obviously, the accompanying drawings are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar situations based on these drawings without any creative effort. Furthermore, it is understood that although the work done in this development process may be complex and lengthy, for those skilled in the art, certain design, manufacturing, or production modifications made based on the technical content disclosed in this application are merely conventional technical means and should not be considered as insufficient disclosure of this application.

[0087] The term "embodiment" in this application refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply that it is mutually exclusive with or independent of other embodiments. It will be clearly or implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0088] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A chip attack detection circuit, characterized in that, include: The system includes an attack detection module and a calibration module, with the attack detection module connected to the calibration module; wherein... The attack detection module includes a first delay chain and an alarm unit. The first delay chain is connected to a clock port and is used to receive the clock signal output by the clock port. When the clock signal changes, the signal output by the first delay chain changes, triggering the alarm unit to output an alarm signal. The calibration module is used to calibrate the first delay chain so that the first propagation time of the signal output by the first delay chain tends to the initial propagation time. The calibration module includes a first calibration unit and a second calibration unit. The first calibration unit is connected to the first delay chain and the second calibration unit, respectively. The first calibration unit is used to calibrate the first propagation time according to the received calibration signal. The second calibration unit is used to calibrate the second propagation time of the second calibration unit. The sum of the second propagation time and the first propagation time is the period of the clock signal. The first calibration unit includes: a second delay chain, a first flip-flop, a second flip-flop, and a multiplexer; wherein the first flip-flop is connected to the clock port and the second delay chain, the second delay chain is connected to the first delay chain and the second flip-flop, and the second flip-flop is connected to the first delay chain; wherein the first delay chain and the second delay chain each include at least one delay unit, and the delay unit includes a buffer and a multiplexer; the control terminal of the multiplexer is used to receive the calibration signal, the input terminal of the multiplexer is connected to the clock port and the second delay chain, and the output terminal of the multiplexer is connected to the first delay chain and the second flip-flop; The second calibration unit includes a decoder, which is connected to a corresponding delay unit in the second delay chain.

2. The chip attack detection circuit according to claim 1, characterized in that, The signal changes output by the first delay chain include: The first propagation time variation, and / or the period variation of the signal output by the first delay chain.

3. The chip attack detection circuit according to claim 1, characterized in that, The first flip-flop includes a clock input, a data input, a main output, and a secondary output; the second flip-flop includes a clock input, a data input, a main output, and a secondary output; the second flip-flop includes a clock input, a data input, and a main output; wherein, The clock input terminal of the first flip-flop is connected to the clock port, the data input terminal of the first flip-flop is connected to the secondary output terminal of the first flip-flop, and the main output terminal of the first flip-flop is connected to the input terminal of the second delay chain. The clock input of the second flip-flop is connected to the output of the buffer, the data input of the second flip-flop is connected to the input of the first delay chain, and the main output of the second flip-flop is connected to the control terminal of the multiplexer.

4. The chip attack detection circuit according to claim 1, characterized in that, The first calibration unit calibrates the first propagation time, including: When the calibration signal is a first preset signal, the second trigger outputs a selection signal according to the second propagation time of the second delay chain, and the first delay chain modifies the first propagation time according to the selection signal.

5. The chip attack detection circuit according to claim 1, characterized in that, The first calibration unit further includes a first transistor, a second transistor, and a first logic gate; wherein the first transistor and the second transistor are respectively connected to the second delay chain, the output terminal of the first logic gate is connected to the second transistor, and the input terminal of the first logic gate is connected to the input terminal of the first transistor, for receiving calibration signals; When the calibration signal is the second preset signal, the first calibration unit does not perform calibration operation and controls the power supply terminal and ground terminal of the second delay chain to be disconnected through the first transistor, the second transistor, and the first logic gate.

6. The chip attack detection circuit according to claim 1, characterized in that, The alarm unit includes: a third flip-flop, a fourth flip-flop, and a second logic gate; wherein... The input terminal of the third flip-flop is connected to the output terminal of the first delay chain and the clock port, respectively. The input terminal of the fourth flip-flop is connected to the output terminal of the first delay chain and the clock port, respectively. The output terminals of the third flip-flop and the fourth flip-flop are connected to the input terminal of the second logic gate, respectively.

7. The chip attack detection circuit according to claim 6, characterized in that, The third and fourth flip-flops each include a clock input, a data input, a main output, and a secondary output, wherein the signals output by the main output and the secondary output are complementary; wherein... The clock input of the third flip-flop is connected to the output of the first delay chain, the data input of the third flip-flop is connected to the clock port, and the main output of the third flip-flop is connected to the input of the second logic gate. The clock input terminal of the fourth flip-flop is connected to the clock port, the data input terminal of the fourth flip-flop is connected to the output terminal of the first delay chain, and the secondary output terminal of the fourth flip-flop is connected to the input terminal of the second logic gate.

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