FPGA implementation method of a spectrum

Abstract

The present application provides a kind of FPGA implementation method of spectrum, including using multiple filter channelization technology, wideband signal becomes multiple narrowband signal, narrowband signal is operated FFT, and each narrowband spectrum is spliced out wideband spectrum.The purpose of the present application is to optimize spectrum algorithm using digital signal processing technology, reduce the use of FPGA resources when realizing large bandwidth high resolution spectrum, thereby reducing equipment cost.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic equipment, and particularly relates to a spectrum FPGA implementation method. BACKGROUND

[0002] The receiver is the most commonly used receiving equipment in the field of radio electromagnetic spectrum monitoring. It can express the electrical signal received by the antenna in the form of spectrum through amplification, filtering, frequency conversion, sampling, signal processing and other circuits, and can monitor the activity of radio signals in the sky through spectrum monitoring.

[0003] In modern society, communication is becoming more and more developed, and the types and quantities of communication signals are increasing, and the signal bandwidth ranges from several kilohertz to several hundred megahertz. This requires the receiver to have a wider receiving bandwidth of several hundred megahertz. The receiver calculates the data of several hundred megahertz bandwidth through FFT transformation to obtain the spectrum. The resolution of the spectrum is an important indicator of the ability to observe the spectrum. The higher the resolution, the more details of the signal or the smaller bandwidth of the signal can be observed, and adjacent narrowband signals can be distinguished.

[0004] The higher the resolution of the spectrum, the more data needs to be processed by FFT transformation, which means that the amount of computation is larger and the space for storing data is larger.

[0005] FPGA can be used for FFT calculation as an embedded signal processor, but the storage space and calculation unit are limited, and it is difficult to implement on a low-cost and low-power FPGA.

[0006] At present, the methods for implementing the wideband spectrum of the receiver include computer processing, DSP processing, FPGA processing and GPU processing. The computer processing is easy to implement, but requires a high-speed data transmission interface that can ensure several Gbit / s of data flow transmission. A general gigabit network or terabit network cannot meet the requirements. Only a high-speed interface such as PCIE is used, which makes the processing device large in size and power consumption, and cannot be realized in a portable and small size. At the same time, the CPU calculation speed cannot meet the requirements of real-time spectrum processing. GUP can be processed in parallel, and through distributed software processing design, real-time processing of wideband spectrum can be realized. However, GUP relies on a computer platform for work, and also has the inherent defects of computer processing. DSP is an integrated circuit with a high-speed data transmission interface and a high-speed processing calculation unit, supports C voice programming and floating point operation, and is easy to program. It can be used for digital signal processors and belongs to embedded processors. However, the processing speed cannot meet the requirements of real-time spectrum processing. FPGA has a rich high-speed interface, storage unit and calculation unit. Through programming using existing IP cores, parallel processing can be realized, and the requirements of real-time spectrum processing and small size and portability can be met. However, with the increase of the bandwidth and resolution of the spectrum to be processed, the required storage unit and calculation unit increase exponentially, which causes a bottleneck and cannot be realized.

[0007] The spectrum calculation is implemented by using the FFT processing IP core provided by XINLINX, and the main resources required by the IP core include logic units, DSP calculation units and BRAM storage units, and according to the resource consumption of the 24-bit pipeline FFT provided by XINLINX, the following table is obtained:

[0008] FFT point number DSPs BRAM 8 14 2 16 16 2 32 26 2 64 30 2 128 42 2 256 46 4 512 58 8 1024 62 11 2048 74 19 4096 78 30 8129 90 56 16384 94 103 32768 106 201 65536 110 393

[0009] If 200MHz bandwidth resolution 3.125kHz is to be implemented, generally, the complex sampling rate required by 200MHz bandwidth is 256Ms / s, at this time, the FFT point number required is 256000 / 3.125=81920, according to the data in the above table, the required DSPs resource is greater than 110, and the BRAM resource is greater than 393.

[0010] According to the resource data of the Zynq-7000 series FPGA chip provided by XILINX:

[0011]

[0012]

[0013] To implement a large bandwidth high resolution spectrum, a high performance chip is required, and the price is high and the cost is increased. SUMMARY

[0014] The purpose of the present application is to solve the defects of the prior art, and provide a frequency FPGA implementation method, which reduces the operation amount and the storage unit by using a digital signal processing method, and realizes a large bandwidth high resolution spectrum on an FPGA.

[0015] The application adopts the following technical scheme:

[0016] A spectrum FPGA implementation method, which adopts an efficient polynomial filtering technology to change a wideband signal into a plurality of narrowband signals, an FFT channelized DDC algorithm to realize DDC operation, and an FFT operation on the narrowband signals to splice the wideband spectrum from the narrowband spectrums:

[0017] The FFT channelized DDC is composed of a polyphase filtering module, an FFT module and a DDC module;

[0018] The polyphase filtering module includes a shift register array, a data latch, filter coefficients, a multiplier accumulator group, a BRAM1 and a polyphase filtering control module. The shift register array stores the bandwidth input data according to the principle of first-in-first-out, saves the latest wideband IQ data, controls the data required by a certain phase filtering to be pushed to the data latch through the polyphase filtering control module, at the same time, the corresponding filter coefficients are put in, and the filtering result is calculated by the multiplier group once and put into the BRAM1.

[0019] The FFT module includes FFT, FFT control module, BRAM2. The FFT performs FFT calculation on the filtering result of BRAM1 and outputs channelization result into BRAM2. The FFT control module controls the FFT processing process in cooperation with the polyphase filtering module.

[0020] The DDC module includes data decomposition, DDS, complex multiplication, DDC control module. The center frequency of the multi-path DDC data obtained by data decomposition is deviated. The DDS outputs sine and cosine according to the frequency deviation of each DDC, and the final result is output through the complex multiplier. The DDC control module controls the DDS frequency according to the number of processing paths.

[0021] When the 200MHz wideband sampling rate is 256M / s, the wideband signal is to realize the resolution of 3.125KHz spectrum, the input signal is filtered through the polyphase filtering module first. The module processes once for every 10 input data, and outputs 13-phase FFT data. In this way, the input rate of 256M / s (Din_iq) is divided by 10, and the output rate conversion of 25.6M / s is realized. At the same time, the polyphase filtering module determines the selectivity of the output DDC.

[0022] The 13-phase data output by the polyphase filtering module is processed by the FFT module. Since the data of each channel output by the FFT channelization operation has a frequency offset problem, the role of the DDC module is to compensate for the frequency offset of each channel, move the center frequency of the channelization data output by the FFT module to zero frequency output, complete 13-channel DDC, and the sampling rate of each sub-channel is 25.6M / s, the bandwidth is 20MHz, and the overlap between each sub-channel is 5MHz bandwidth, which covers the 200MHz bandwidth.

[0023] Further, the sampling rate of each sub-channel is 25.6M / s, and to achieve a frequency resolution of 3.125KHz, the FFT point number is 25.6 / 0.003125=8192. At this time, 8192-point FFT consumes less resources, and DSP uses 90 and BRAM uses 56.

[0024] Further, since the sampling rate of each data is 25.6M / s, the rate is low, and the 13-way FFT adopts time division multiplexing to realize each 7-way multiplexing of an FFT calculation IP core.

[0025] When the wideband signal of 240MHz wideband sampling rate 307.2M / s is to realize the spectrum of resolution 3.125KHz, the input signal is filtered through the polyphase filtering module first, the module processes once for every 12 input data, and outputs 16-phase FFT data, so that the input rate of 307.2M / s (Din_iq) is divided by 12, and the rate conversion of 25.6M / s is output, and the polyphase filtering module determines the selectivity of the output DDC;

[0026] The 16-phase data output by the polyphase filtering module passes through the FFT module, and since the data of each channel output by the FFT channelization operation has a frequency offset problem, the role of the DDC module is to compensate for the frequency offset of each channel, move the center frequency of the channelization data output by the FFT module to zero frequency output, complete 16-way channelization DDC, and the sampling rate of each sub-channel is 25.6M / s, the bandwidth is 18.75MHz, and each sub-channel overlaps 4MHz bandwidth, which covers the 240MHz bandwidth.

[0027] The sampling rate of each sub-channel is 25.6M / s, and to achieve a frequency resolution of 3.125KHz, the FFT point number is 25.6 / 0.003125=8192, at this time, 8192-point FFT consumes less resources, DSP uses 90, and BRAM uses 56. Since the sampling rate of each channel is 25.6M / s, the rate is low, and 16-way FFT adopts a time division multiplexing mode to realize, and an FFT calculation IP core is multiplexed every 8 ways.

[0028] The present application has the following advantages:

[0029] The present application reduces the difficulty of implementing a large bandwidth and high resolution spectrum, reduces the use of FPGA resources, and reduces the cost.

[0030] The present application realizes a 200MHz bandwidth spectrum with a resolution of 3.125KHz, and the wideband IQ data sampling rate is 256M / s. The direct FFT method needs to perform 89120-point FFT operation. Since 89120 is not a power of 2, the FFT IP core cannot be directly called, and a complex custom programming method must be used. The required DSPs resource is much larger than 110, and the BRAM resource is much larger than 393. The present application can call the FFT IP core, greatly reducing the implementation difficulty, reducing the resources used, requiring less than 880 DSPs resources and less than 400 BRAM resources, and reducing the processing clock of FPGA, which is easier to meet the timing requirements and more stable in software running.

[0031] To achieve a 240MHz bandwidth resolution of 3.125kHz spectrum with a broadband IQ data sampling rate of 307.2M / s, the direct FFT method requires a 98304-point FFT operation. Since 98304 is not a power of 2, the FFT IP core cannot be directly called, requiring complex custom programming methods. Furthermore, the required DSP resources are far greater than 110 and BRAM resources far greater than 393. This invention, however, can call the FFT IP core, significantly reducing implementation difficulty. It also reduces resource usage, requiring less than 998 DSP resources and less than 600 BRAM resources. Simultaneously, the FPGA processing clock speed is reduced, making it easier to meet timing requirements and resulting in more stable software operation. Attached Figure Description

[0032] Figure 1 This is a block diagram illustrating the principle of FFT-channelized DDC.

[0033] Figure 2 This is a flowchart of the steps of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described clearly and completely below. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0035] A receiver is an electronic device that can receive wireless signals and can be used for electromagnetic spectrum monitoring.

[0036] The spectrum is the frequency domain representation of a radio signal. By converting the time domain signal to the frequency domain using FFT (Fourier Transform), the frequency and amplitude of the radio signal can be represented.

[0037] FPGA is a type of digital integrated circuit chip. Its full name is Field Programmable Gate Array. A key characteristic of FPGA is its programmability, meaning that users can program the FPGA to implement a specific digital circuit.

[0038] Example 1

[0039] like Figure 2 As shown, an FGPA implementation method for spectrum utilizes multiple filtering channelization technology to first convert a broadband signal into multiple narrowband signals, then perform FFT operations on the narrowband signals, and finally stitch the narrowband spectra together to form a broadband spectrum. Through this optimized algorithm, the resources used to implement a large bandwidth, high-resolution spectrum on an FPGA are reduced by half compared to directly using IP cores for computation.

[0040] For a wideband signal with a wideband sampling rate of 256M / s, to achieve a resolution of 3.125KHz spectrum, a hierarchical signalization processing technology is used, 200MHz wideband data is channelized by using high-efficiency multi-path DDC implementation technology, then 13 channels are calculated by time-sharing FFT, and finally the spectrum of the 13 channels is spliced to obtain the spectrum of 200MHz bandwidth.

[0041] Since the input signal bandwidth is 200MHz, if 13 independent DDCs are used to channelize such a high bandwidth, a considerable amount of resources will be used. In order to reduce the resources for implementing multi-path DDC, an efficient polynomial filtering technology is used to implement DDC operation by FFT channelization DDC algorithm, and the principle of FFT channelization DDC is as shown in Figure 1 .

[0042] The FFT channelization DDC is composed of a polyphase filtering module, an FFT module and a DDC module.

[0043] The polyphase filtering module includes a shift register array, a data latch, a filter coefficient, a multiplier group, a BRAM1 and a polyphase filtering control module. The polyphase filtering module completes 13-phase filtering by time sharing. Since the sampling rate is high, parallel calculation is used for each phase filtering. The length of the shift register array is the order of the polyphase filtering module. The lengths of the data storage, the filter coefficient and the multiplier group are the length of each phase filtering module. The BRAM1 saves the output result of each phase, and the length is 13.

[0044] The shift register array stores the input data with a bandwidth of 200MHz according to the principle of first-in-first-out, saves the latest wideband IQ data, and pushes the data required by a certain phase filtering to the data latch through the polyphase filtering control module. At the same time, the corresponding filter coefficient is put in, and the filtering result is calculated by the multiplier group once and put into the BRAM1.

[0045] The FFT module includes FFT, FFT control module and BRAM2. The FFT calculation is performed on the filtering result of the BRAM1, the channelization result is output and put into the BRAM2, and the FFT control module controls the FFT processing process with the polyphase filtering module.

[0046] The DDC module includes data decomposition, DDS, complex multiplication and DDC control module. The center frequency of the multi-path DDC data obtained by data decomposition has a deviation. The DDS outputs sine and cosine according to the frequency deviation of each DDC, and the final result is output by the complex multiplier. The DDC control module controls the DDS frequency according to the number of processed paths.

[0047] The input signal is filtered by a polyphase filter module, which processes 10 input data at a time and outputs 13-phase FFT data (the internal data of the filter overlaps), so as to realize 10 frequency division of the input 256M / s (Din_iq) rate, output 25.6M / s rate conversion, and simultaneously determine the selectivity of the output DDC.

[0048] The 13-phase data output by the polyphase filter module is processed by an FFT module. Since the data of each channel output by the FFT channelization operation has a frequency offset problem, the role of the DDC module is to compensate for the frequency offset of each channel, move the center frequency of the channelization data output by the FFT module to zero frequency output, complete 13-channel DDC, and the sampling rate of each sub-channel is 25.6M / S, the bandwidth is 20MHz, and the overlap between each sub-channel is 5MHz bandwidth, which covers the 200MHz bandwidth.

[0049] Compared with the conventional 13-channel independent DDC algorithm, the DSP slice consumption is greatly reduced.

[0050] The sampling rate of each sub-channel is 25.6M / s, and to achieve a frequency resolution of 3.125KHz, the FFT point number is 25.6 / 0.003125=8192. At this time, the 8192-point FFT consumes fewer resources, and 90 DSPs and 56 BRAMs are used.

[0051] Since the sampling rate of each channel is 25.6M / s, which is relatively low, 13-channel FFT adopts time division multiplexing to realize each 7-channel multiplexing of an FFT calculation IP core.

[0052] Embodiment 2

[0053] Similarly, a 240MHz wideband signal with a sampling rate of 307.2M / s can be processed. To achieve a frequency spectrum resolution of 3.125KHz, the 240MHz wideband data is channelized into 16 channels, and then the 16 channels are processed by time-sharing FFT calculation. Finally, the 16-channel frequency spectrum is spliced to obtain a 240MHz bandwidth frequency spectrum.

[0054] The input signal is filtered by a polyphase filter module, which processes 10 input data at a time and outputs 13-phase FFT data (the internal data of the filter overlaps), so as to realize 10 frequency division of the input 256M / s (Din_iq) rate, output 25.6M / s rate conversion, and simultaneously determine the selectivity of the output DDC.

[0055] The 16-phase data outputted by the polyphase filtering module passes through the FFT module, and since the data of each channel outputted by the FFT channelization operation has a frequency offset problem, the role of the DDC module is to compensate for the frequency offset of each channel, to move the center frequency of the channelization data outputted by the FFT module to zero frequency output, to complete 16-way channelization DDC, and each sub-channel sampling rate is 25.6M / S, the bandwidth is 18.75MHz, and each sub-channel overlaps 4MHz bandwidth, which just covers the 240MHz bandwidth.

[0056] Compared with the conventional 16-way independent DDC algorithm, the DSP slice consumption is greatly reduced.

[0057] The sampling rate of each sub-channel is 25.6M / s, to achieve 3.125KHz frequency resolution, the FFT point number is 25.6 / 0.003125=8192, at this time, the 8192-point FFT consumes less resources, 90 DSPs and 56 BRAMs are used. Since the sampling rate of each channel is 25.6M / s, the rate is low, and the 16-way FFT adopts a time division multiplexing mode to be realized, and each 8-way is multiplexed to an FFT calculation IP core.

[0058] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for implementing FGPA in the spectrum, characterized in that, Multi-pass filtering is used to convert a broadband signal into multiple narrowband signals. The FFT channelized DDC algorithm is used to perform DDC operations on the narrowband signals, and the spectrum of each narrowband signal is stitched together to form the broadband spectrum. The FFT-channelized DDC consists of a polyphase filtering module, an FFT module, and a DDC module. The multiphase filtering module includes a shift register array, a data latch, filter coefficients, a multiply-accumulator group, BRAM1, and a multiphase filtering control module. The shift register array stores the bandwidth input data according to the first-in-first-out principle and saves the latest broadband IQ data. The multiphase filtering control module controls the data required for filtering a certain phase to be pushed to the data latch and the corresponding filter coefficients to be put in. The multiplyer group calculates the filtering result in one go and puts it into BRAM1. The FFT module includes FFT, FFT control module, and BRAM2. FFT performs FFT calculation on the filtering result of BRAM1 and outputs the channelized result into BRAM2. The FFT control module and the polyphase filtering module handshake to control the FFT processing. The DDC module includes a data decomposition module, a DDS module, a complex multiplication module, and a DDC control module. The center frequencies of the multiple DDC data obtained by data decomposition have deviations. The DDS outputs sine and cosines based on the frequency deviation of each DDC channel. The complex multiplier performs mixing operations to output the final result. The DDC control module controls the DDS frequency according to the number of channels being processed. To achieve a spectrum resolution of 3.125kHz for a 200MHz wideband signal with a sampling rate of 256M / s: The input signal is first filtered by a multiphase filter module. This module processes every 10 input data points and outputs 13-phase FFT data, which realizes the conversion of the input rate of 256M / s to 25.6M / s by dividing the frequency by 10. At the same time, the multiphase filter module determines the selectivity of the output DDC. The 13-phase data output from the multiphase filtering module is processed by the FFT module. Since the data of each channel output by the FFT channelization operation has a frequency offset problem, the role of the DDC module is to compensate for the frequency offset of each channel, shifting the center frequency of the channelized data output by the FFT module to the zero-frequency output, thus completing the 13-channel channelized DDC. The sampling rate of each sub-channel is 25.6M / s, the bandwidth is 20MHz, and the bandwidth between each sub-channel overlaps by 5MHz, which just covers the 200MHz bandwidth.

2. The FGPA implementation method for the spectrum according to claim 1, characterized in that, The sampling rate of each sub-channel is 25.6M / s. To achieve a frequency resolution of 3.125KHz, the number of FFT points is 25.6 / 0.003125=8192. At this point, the 8192-point FFT does not consume many resources. The DSP uses 90 points and the BRAM uses 56 points.

3. The FGPA implementation method for the spectrum according to claim 1, characterized in that, Since the data sampling rate of each channel is 25.6M / s, which is relatively low, the 13-channel FFT is implemented using time-division multiplexing, with each 7 channels multiplexing one FFT calculation IP core.

4. The FGPA implementation method for the spectrum according to claim 1, characterized in that, When a broadband signal with a sampling rate of 307.2M / s and a bandwidth of 240MHz is to be processed to achieve a spectrum resolution of 3.125KHz, the input signal is first filtered by a multiphase filter module. This module processes every 12 input data points and outputs 16-phase FFT data. This achieves a 12-fold frequency division of the input rate of 307.2M / s, resulting in a rate conversion of 25.6M / s. At the same time, the multiphase filter module determines the selectivity of the output DDC. The 16-phase data output from the multiphase filtering module is processed by the FFT module. Since the data of each channel output by the FFT channelization operation has a frequency offset problem, the role of the DDC module is to compensate for the frequency offset of each channel, shifting the center frequency of the channelized data output by the FFT module to the zero-frequency output, thus completing the 16-channel channelized DDC. The sampling rate of each sub-channel is 25.6M / s, the bandwidth is 18.75MHz, and the bandwidth between each sub-channel overlaps by 4MHz, which just covers the 240MHz bandwidth.

5. The FGPA implementation method for the spectrum according to claim 4, characterized in that, The sampling rate of each sub-channel is 25.6M / s. To achieve a frequency resolution of 3.125KHz, the number of FFT points is 25.6 / 0.003125=8192. At this point, the 8192-point FFT does not consume many resources. The DSP uses 90 points and the BRAM uses 56 points.

6. The FGPA implementation method for the spectrum according to claim 4, characterized in that, Since the data sampling rate of each channel is 25.6M / s, which is relatively low, the 16-channel FFT is implemented using time-division multiplexing, with each 8 channels multiplexing one FFT calculation IP core.

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