I2C link balanced allocation method, system, terminal and storage medium for BMC

Abstract

The present invention belongs to the technical field of servers, and specifically provides a method, system, terminal and storage medium for balancing the I2C link of a BMC, including: a CPLD monitors the time when the BMC accesses a device and the information of calling an I2C port, the CPLD includes a first port group and a second port group, each port in the first port group is respectively connected to the I2C port of the BMC, and each port in the second port group is respectively connected to an I2C link of different devices; the CPLD selects the I2C port of the BMC that has not been called recently as an idle port based on the monitoring result, and binds the first subpath where the idle port is located and the second subpath where the target device accessed by the BMC is located in a routing table as an access path of the target device, the first subpath is formed by connecting the idle port and the corresponding port in the first port group, and the second subpath is formed by connecting the target device and the corresponding port in the second port group. The present invention improves the monitoring efficiency and performance of the BMC.

Description

Technical Field

[0001] The present invention belongs to the technical field of servers, and in particular relates to a BMC I2C link balanced allocation method, system, terminal and storage medium. Background Art

[0002] As the amount of social data increases and data processing becomes more complex, the server equipment requirements are getting higher and higher. For server management, there are more and more devices that need to be managed. At present, the server uses a baseboard management controller (BMC) to manage various devices. Various devices are connected to the BMC through an I2C link. The BMC can perform firmware upgrades, view machine equipment, and other operations on the machine when the machine is not turned on.

[0003] Since BMC has different monitoring principles for different types of devices, the information required is also different, and the number of interactions is also different, so it is often the case that I2C devices on some links are frequently accessed, while I2C devices on other links are rarely accessed. The I2C links of the BMC chip itself are limited, so it is necessary to plan and allocate the devices connected by the I2C links reasonably.

[0004] However, since the I2C links between various devices and BMC are fixed in hardware structure, resources cannot be shared between different links. This leads to a waste of BMC's I2C communication resources. In addition, the BMC's management load is too heavy, resulting in frequent problems with BMC monitoring. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a method, system, terminal and storage medium for balancing I2C link allocation of a BMC to solve the above-mentioned technical problems.

[0006] In a first aspect, the present invention provides a method for balancing I2C links of a BMC, comprising:

[0007] The CPLD monitors the time when the BMC accesses the device and the information of calling the I2C port, wherein the CPLD includes a first port group and a second port group, each port in the first port group is respectively connected to the I2C port of the BMC, and each port in the second port group is respectively connected to an I2C link with a different device;

[0008] Based on the monitoring result, the CPLD selects the I2C port of the BMC that has not been called recently as the idle port, and binds the first subpath where the idle port is located and the second subpath where the target device accessed by the BMC is located as the access path of the target device in the routing table, wherein the first subpath is formed by connecting the idle port and the corresponding port in the first port group, and the second subpath is formed by connecting the target device and the corresponding port in the second port group.

[0009] Furthermore, the CPLD monitors the time when the BMC accesses the device and the information of calling the I2C port, including:

[0010] In response to a device access request sent by the BMC through the SPI link, the CPLD records the idle port number and timestamp when allocating an idle port to the BMC;

[0011] The recorded I2C port numbers and timestamps are summarized into the historical access list.

[0012] Furthermore, based on the monitoring results, the CPLD selects the I2C ports of the BMC that have not been called recently as idle ports, including:

[0013] The CPLD selects unused ports that are not recorded in the historical access list from all I2C ports of the BMC, and randomly selects an unused port as an idle port;

[0014] If there is no unused port, the target port number with the earliest corresponding timestamp is searched from the historical access list as the free port.

[0015] Furthermore, the CPLD selects the I2C port of the BMC that has not been called recently as an idle port based on the monitoring result, and binds the first subpath where the idle port is located and the second subpath where the target device accessed by the BMC is located in the routing table as an access path of the target device, including:

[0016] The CPLD sends the information of the idle port to the BMC through the SPI link, so that the BMC sends a series of access instructions for the target device through the first subpath where the idle port is located;

[0017] The CPLD determines the target device according to the received access instruction, and searches the register slave address of the target device from the pre-stored register slave addresses of each device as the target address;

[0018] The CPLD binds the second subpath indicated by the target address and the first subpath as an access path of the target device, and forwards data between the first subpath and the second subpath when the BMC interacts with the target device based on the binding relationship.

[0019] In a second aspect, the present invention provides an I2C link balanced distribution system for a BMC, comprising:

[0020] An access monitoring unit, used for CPLD to monitor the time when BMC accesses the device and the information of calling the I2C port, wherein the CPLD includes a first port group and a second port group, each port in the first port group is respectively connected to the I2C port of the BMC, and each port in the second port group is respectively connected to an I2C link with different devices;

[0021] The path allocation unit is used for the CPLD to filter out the I2C ports of the BMC that have not been called recently as idle ports based on the monitoring results, and bind the first sub-path where the idle port is located and the second sub-path where the target device accessed by the BMC is located as the access path of the target device in the routing table, wherein the first sub-path is formed by connecting the idle port and the corresponding port in the first port group, and the second sub-path is formed by connecting the target device and the corresponding port in the second port group.

[0022] Furthermore, the access monitoring unit includes:

[0023] An information recording module, used for responding to a device access request sent by the BMC through the SPI link, and for recording the idle port number and timestamp when the CPLD allocates an idle port to the BMC;

[0024] The information summary module is used to summarize the recorded I2C port number and timestamp into the historical access list.

[0025] Furthermore, the path allocation unit includes:

[0026] A first screening module, used for the CPLD to screen out unused ports that are not recorded in the historical access list from all I2C ports of the BMC, and randomly select an unused port as an idle port;

[0027] The second screening module is used to search the target port number with the earliest corresponding timestamp from the historical access list as the free port if there is no unused port.

[0028] Furthermore, the path allocation unit includes:

[0029] A path sending module, used for the CPLD to send the information of the idle port to the BMC through the SPI link, so that the BMC sends a series of access instructions for the target device through the first sub-path where the idle port is located;

[0030] The address query module is used for the CPLD to determine the target device according to the received access instruction, and to query the register slave address of the target device from the pre-stored register slave addresses of each device as the target address;

[0031] The path binding module is used for the CPLD to bind the second sub-path indicated by the target address and the first sub-path as the access path of the target device, and forward data between the first sub-path and the second sub-path when the BMC and the target device interact with each other based on the binding relationship.

[0032] In a third aspect, a terminal is provided, including:

[0033] processor, memory, wherein:

[0034] The memory is used to store computer programs.

[0035] The processor is used to call and run the computer program from the memory, so that the terminal executes the above-mentioned terminal method.

[0036] According to a fourth aspect, a computer storage medium is provided, wherein the computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the computer executes the methods described in the above aspects.

[0037] The beneficial effects of the present invention are:

[0038] The I2C link balanced allocation method, system, terminal and storage medium of the BMC provided by the present invention, by adding a CPLD, the CPLD monitors the access status of each I2C link of the BMC, and allocates tasks to the I2C links of the BMC based on the monitoring results, thereby realizing the reasonable allocation and optimization of the I2C communication resources of the BMC, and improving the monitoring efficiency and performance of the BMC.

[0039] In addition, the invention has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention.

[0042] Figure 2 It is a CPLD connection structure diagram of a method according to an embodiment of the present invention.

[0043] Figure 3 is a schematic block diagram of a system according to an embodiment of the present invention.

[0044] Figure 4A schematic diagram of the structure of a terminal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] The key terms appearing in the present invention are explained below.

[0047] BMC, the server remote management controller, is called Baseboard Management Controller in English. It can perform firmware upgrades, check machine equipment, and other operations on the machine when the machine is not turned on. Fully implementing IPMI functions in BMC requires a powerful 16-bit or 32-bit microcontroller, RAM for data storage, flash memory for non-volatile data storage, and firmware, which can provide basic remote manageability in terms of safe remote restart, safe power-on, LAN warning, and system health monitoring. In addition to basic IPMI functions and system operation monitoring functions, mBMC can also implement BIOS fast element selection and protection by using one of the two flash memories to store the previous BIOS. For example, when the system cannot start after a remote BIOS upgrade, the remote administrator can switch back to the previously working BIOS image to start the system. Once the BIOS is upgraded, the BIOS image can also be locked to effectively prevent viruses from invading it.

[0048] The I2C bus is a simple, bidirectional, two-wire synchronous serial bus. It only requires two wires to transmit information between devices connected to the bus. The master device is used to start the bus to transmit data and generate a clock to open the transmitting device. At this time, any addressed device is considered a slave device. The relationship between the master and slave, send and receive on the bus is not constant, but depends on the direction of data transmission at this time. If the host wants to send data to the slave device, the host first addresses the slave device, then actively sends data to the slave device, and finally the host terminates the data transmission; if the host wants to receive data from the slave device, the master device first addresses the slave device. Then the host receives the data sent by the slave device, and finally the host terminates the receiving process. In this case. The host is responsible for generating a timing clock and terminating data transmission.

[0049] BIOS is the abbreviation of "Basic Input Output System". The Chinese name is "Basic Input Output System". On IBM PC compatible systems, it is an industry-standard firmware interface. It is a set of programs fixed to a ROM chip on the motherboard of the computer. It stores the most important basic input and output programs of the computer, the self-test program after power-on, and the system self-starting program. It can read and write specific information of system settings from CMOS. Its main function is to provide the lowest-level and most direct hardware settings and control for the computer. In addition, BIOS also provides some system parameters to the operating system. Changes in system hardware are hidden by BIOS, and programs use BIOS functions instead of directly controlling hardware. Modern operating systems ignore the abstraction layer provided by BIOS and directly control hardware components.

[0050] Complex programmable logic devices (CPLDs) use programming technologies such as CMOS EPROM, EEPROM, flash memory, and SRAM to form high-density, high-speed, and low-power programmable logic devices. The logic block in a PLD is similar to a small-scale PLD. Usually, a logic block contains 4 to 20 macro cells, and each macro cell is generally composed of a product term array, product term allocation, and a programmable register. Each macro cell has multiple configuration methods, and each macro cell can also be used in cascade, so more complex combinational logic and sequential logic functions can be realized. For CPLDs with higher integration, embedded array blocks with on-chip RAM / ROM are usually provided. The programmable interconnect channel mainly provides an interconnection network between logic blocks, macro cells, and input / output pins. The input / output block (I / O block) provides an interface between the internal logic and the device I / O pins. CPLDs with larger logic scales generally also have JTAG boundary scan test circuits, which can perform comprehensive and thorough system testing on programmed high-density programmable logic devices. In addition, in-system programming can also be performed through the JTAG interface. Due to differences in integration technology, integration scale and manufacturer, the partition structures, logic units, etc. of various CPLDs also have significant differences.

[0051] SPI is the abbreviation of Serial Peripheral Interface, which is a synchronous serial interface technology and a high-speed, full-duplex, synchronous communication bus.

[0052] Figure 1 is a schematic flow chart of a method according to an embodiment of the present invention. Figure 1 The execution subject may be an I2C link balancing distribution system of a BMC.

[0053] like Figure 1 As shown, the method includes:

[0054] Step 110, the CPLD monitors the time when the BMC accesses the device and the information of calling the I2C port, the CPLD includes a first port group and a second port group, each port in the first port group is respectively connected to the I2C port of the BMC, and each port in the second port group is respectively connected to a different device. I2C link connection;

[0055] Step 120: Based on the monitoring result, the CPLD selects the I2C port of the BMC that has not been called recently as an idle port, and binds the first subpath where the idle port is located and the second subpath where the target device accessed by the BMC is located as an access path of the target device in the routing table, wherein the first subpath is formed by connecting the idle port and the corresponding port in the first port group, and the second subpath is formed by connecting the target device and the corresponding port in the second port group.

[0056] By adding a CPLD, the CPLD monitors the access status of each I2C link of the BMC and allocates tasks to the I2C link of the BMC based on the monitoring results, thereby achieving reasonable allocation and optimization of the I2C communication resources of the BMC and improving the monitoring efficiency and performance of the BMC.

[0057] To facilitate understanding of the present invention, the following further describes the I2C link balanced allocation method for BMC provided by the present invention based on the principle of the I2C link balanced allocation method for BMC of the present invention and the process of balanced allocation of the I2C link of BMC in the embodiment.

[0058] The connection relationship between CPLD, BMC and other devices is as follows Figure 2 As shown, the BMC has only 14 I2C links (BUS0-BUS13). All I2C links of the BMC are connected to the CPLD, and the CPLD connects to each device via the I2C link in a one-to-one manner. The CPLD is also connected to the BMC through the SPI link.

[0059] The BMC I2C link balanced distribution method executed by the CPLD includes the following steps:

[0060] S1. CPLD monitors the time when BMC accesses the device and the information of calling the I2C port. The CPLD includes a first port group and a second port group. Each port in the first port group is connected to the I2C port of the BMC respectively, and each port in the second port group establishes an I2C link connection with different devices respectively.

[0061] In response to the device access request of the BMC, the CPLD records the first sub-path number and timestamp to which the idle port belongs when allocating an idle port to the BMC; and summarizes the recorded sub-path number and timestamp into a historical access list.

[0062] In this hardware structure, the interaction between BMC and any device must be forwarded through CPLD, which is similar to a switch. Therefore, when BMC exchanges information with a device, it needs to go through CPLD.

[0063] CPLD maintains the linked list of current I2C access information. For example, if the AST2600 has 14 buses, it maintains 14 bus linked lists, which contain the register slave address of the access device and the access timestamp. When accessing a device, BMC first interacts with CPLD via SPI and sends a device access request to CPLD. Based on the request, CPLD allocates an idle port to BMC via SPI path and records the idle port number and timestamp when allocating an idle port (idle bus) to BMC. BMC obtains the currently idlest bus number and then sends the next command to access the device via this bus number.

[0064] S2. Filter out idle links from all I2C links of the BMC based on the access situation.

[0065] The CPLD selects unused ports that are not recorded in the historical access list from all I2C ports of the BMC, and randomly selects an unused port as an idle port; if there is no unused port, the historical access list is searched for a target port number with the earliest corresponding timestamp as an idle port.

[0066] Specifically, the CPLD searches for idle links based on the historical access list, and preferentially searches for unallocated I2C links. If no I2C links are found, the CPLD searches for the earliest allocated link from the allocated links.

[0067] For example, when booting up the computer, the BMC first accesses the first device, and the CPLD selects Bus0 and records the timestamp of the Bus0 access. The BMC then accesses the second device, and the CPLD selects Bus1 and records the timestamp of the Bus1 access, and so on. When the BMC accesses the 14th device (assuming that the BMC has only 14 Buses), the timestamp of the Bus13 access is recorded. When accessing the 15th device, the CPLD searches the Bus in the linked list, selects the timestamp of the current access, and finds the timestamp of the Bus that was accessed the farthest, and considers that the Bus is relatively idle.

[0068] The CPLD sends the information of the idle port to the BMC through the SPI link, so that the BMC sends a series of access instructions for the target device through the first sub-path where the idle port is located; the CPLD determines the target device according to the received access instruction, and queries the register slave address of the target device from the pre-stored register slave addresses of each device as the target address; the CPLD binds the second sub-path indicated by the target address and the first sub-path as the access path of the target device, and forwards data between the first sub-path and the second sub-path when the BMC interacts with the target device based on the binding relationship.

[0069] Specifically, the CPLD sends the bus number to the BMC, and the BMC sends the access instruction to the CPLD through the idle I2C link corresponding to the bus number. The CPLD forwards the access instruction to the register address of the target device according to the target device in the access instruction. The target device feeds back the corresponding data to the CPLD based on the received access instruction, and the CPLD forwards the data to the BMC through the idle I2C link.

[0070] In the improved link scheme, the device is not connected to a specific bus, but the CPLD intelligently selects which bus to connect to based on the current access status of each Bus. By adding a CPLD, the CPLD monitors the access status of each I2C link of the BMC, and assigns tasks to the I2C link of the BMC based on the monitoring results, thereby achieving reasonable allocation and optimization of the I2C communication resources of the BMC and improving the monitoring efficiency and performance of the BMC.

[0071] like Figure 3 As shown, the system 300 includes:

[0072] An access monitoring unit 310 is used for CPLD to monitor the time when the BMC accesses the device and the information of calling the I2C port, wherein the CPLD includes a first port group and a second port group, each port in the first port group is respectively connected to the I2C port of the BMC, and each port in the second port group is respectively connected to an I2C link connection with different devices;

[0073] The path allocation unit 320 is used for the CPLD to filter out the I2C ports of the BMC that have not been called recently as idle ports based on the monitoring results, and bind the first sub-path where the idle port is located and the second sub-path where the target device accessed by the BMC is located as the access path of the target device in the routing table, wherein the first sub-path is formed by connecting the idle port and the corresponding port in the first port group, and the second sub-path is formed by connecting the target device and the corresponding port in the second port group.

[0074] Optionally, as an embodiment of the present invention, the access monitoring unit includes:

[0075] An information recording module, used for responding to a device access request sent by the BMC through the SPI link, and for recording the idle port number and timestamp when the CPLD allocates an idle port to the BMC;

[0076] The information summary module is used to summarize the recorded I2C port number and timestamp into the historical access list.

[0077] The access record module of CPLD maintains the linked list of current I2C access information. For example, if there are 14 buses in ast2600, 14 bus linked lists are maintained, which contain the register slave address of the accessed device and the access timestamp. The record summary module summarizes the recorded results. When accessing a device, BMC first interacts with CPLD in SPI to obtain the currently idle bus number, and then BMC sends the next command to access the device through the bus number.

[0078] Optionally, as an embodiment of the present invention, the path allocation unit includes:

[0079] A first screening module, used for the CPLD to screen out unused ports that are not recorded in the historical access list from all I2C ports of the BMC, and randomly select an unused port as an idle port;

[0080] The second screening module is used to search the target port number with the earliest corresponding timestamp from the historical access list as the free port if there is no unused port.

[0081] Specifically, the CPLD searches for idle links based on the historical access list, and the primary screening module preferentially searches for unallocated I2C links. If no I2C links are found, the secondary screening module searches for the earliest allocated link from the allocated links.

[0082] For example, when booting up the computer, the BMC first accesses the first device, and the CPLD selects Bus0 and records the timestamp of the Bus0 access. The BMC then accesses the second device, and the CPLD selects Bus1 and records the timestamp of the Bus1 access, and so on. When the BMC accesses the 14th device (assuming that the BMC has only 14 Buses), the timestamp of the Bus13 access is recorded. When accessing the 15th device, the CPLD searches the Bus in the linked list, selects the timestamp of the current access, and finds the timestamp of the Bus that was accessed the farthest, and considers that the Bus is relatively idle.

[0083] Optionally, as an embodiment of the present invention, the path allocation unit includes:

[0084] A path sending module, used for the CPLD to send the information of the idle port to the BMC through the SPI link, so that the BMC sends a series of access instructions for the target device through the first sub-path where the idle port is located;

[0085] The address query module is used for the CPLD to determine the target device according to the received access instruction, and to query the register slave address of the target device from the pre-stored register slave addresses of each device as the target address;

[0086] The path binding module is used for the CPLD to bind the second sub-path indicated by the target address and the first sub-path as the access path of the target device, and forward data between the first sub-path and the second sub-path when the BMC and the target device interact with each other based on the binding relationship.

[0087] Specifically, the upload notification module of the CPLD sends the number of the idle link to the BMC, and the BMC sends the access instruction to the CPLD through the idle I2C link corresponding to the number, and the address query module of the CPLD forwards the access instruction to the corresponding device according to the address in the access instruction. The device feeds back the corresponding data to the CPLD based on the received access instruction, and the data forwarding module of the CPLD forwards the data to the idle I2C link, and the BMC receives the data via the idle I2C link.

[0088] In the improved link scheme, the device is not connected to a specific bus, but the CPLD intelligently selects which bus to connect to based on the current access status of each Bus. By adding a CPLD, the CPLD monitors the access status of each I2C link of the BMC, and assigns tasks to the I2C link of the BMC based on the monitoring results, thereby achieving reasonable allocation and optimization of the I2C communication resources of the BMC and improving the monitoring efficiency and performance of the BMC.

[0089] The specific implementation method of the system is as follows:

[0090] When the computer is powered on, the BMC first accesses the first device, and the CPLD selects Bus0 and records the timestamp of Bus0 access. The BMC then accesses the second device, and the CPLD selects Bus1 and records the timestamp of Bus1 access, and so on. When the BMC accesses the 14th device (assuming that the BMC has only 14 Buses), the timestamp of Bus13 access is recorded. When the 15th device is accessed, the CPLD searches the Bus in the linked list, selects the timestamp of the current access, and finds the timestamp of the farthest accessed Bus, and then considers that the Bus is relatively idle. The CPLD will access the device through this Bus.

[0091] Figure 4The present invention provides a schematic diagram of the structure of a terminal 400 provided in an embodiment of the present invention. The terminal 400 can be used to execute the BMC I2C link balanced allocation method provided in an embodiment of the present invention.

[0092] The terminal 400 may include: a processor 410, a memory 420 and a communication unit 430. These components communicate via one or more buses. Those skilled in the art will appreciate that the server structure shown in the figure does not limit the present invention, and it may be a bus structure or a star structure, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0093] The memory 420 can be used to store the execution instructions of the processor 410, and the memory 420 can be implemented by any type of volatile or non-volatile storage terminal or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. When the execution instructions in the memory 420 are executed by the processor 410, the terminal 400 can perform some or all of the steps in the following method embodiments.

[0094] The processor 410 is the control center of the storage terminal, and uses various interfaces and lines to connect various parts of the entire electronic terminal. It runs or executes software programs and / or modules stored in the memory 420, and calls data stored in the memory to perform various functions of the electronic terminal and / or process data. The processor can be composed of an integrated circuit (IC), for example, it can be composed of a single packaged IC, or it can be composed of multiple packaged ICs with the same or different functions. For example, the processor 410 can include only a central processing unit (CPU). In the embodiment of the present invention, the CPU can be a single computing core or multiple computing cores.

[0095] The communication unit 430 is used to establish a communication channel so that the storage terminal can communicate with other terminals, receive user data sent by other terminals or send user data to other terminals.

[0096] The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and when the program is executed, the program may include some or all of the steps in each embodiment provided by the present invention. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM).

[0097] Therefore, the present invention adds a CPLD, which monitors the access status of each I2C link of the BMC and assigns tasks to the I2C link of the BMC based on the monitoring results, thereby achieving reasonable allocation and optimization of the I2C communication resources of the BMC and improving the monitoring efficiency and performance of the BMC. The technical effects that can be achieved by this embodiment can be found in the description above and will not be repeated here.

[0098] Those skilled in the art can clearly understand that the technology in the embodiments of the present invention can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution in the embodiments of the present invention, in essence or in other words, the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes, including several instructions for enabling a computer terminal (which can be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention.

[0099] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

[0100] In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0101] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0102] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0103] Although the present invention has been described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, and all of these shall be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A BMC I2C link balanced allocation method, characterized in that: include: The CPLD monitors the time when the BMC accesses the device and the information of calling the I2C port, wherein the CPLD includes a first port group and a second port group, each port in the first port group is respectively connected to the I2C port of the BMC, and each port in the second port group is respectively connected to an I2C link with a different device; Based on the monitoring result, the CPLD selects the I2C port of the BMC that has not been called recently as the idle port, and binds the first subpath where the idle port is located and the second subpath where the target device accessed by the BMC is located as the access path of the target device in the routing table, wherein the first subpath is formed by connecting the idle port and the corresponding port in the first port group, and the second subpath is formed by connecting the target device and the corresponding port in the second port group.

2. The method according to claim 1, characterized in that The CPLD monitors the time when the BMC accesses the device and the information of calling the I2C port, including: In response to a device access request sent by the BMC through the SPI link, the CPLD records the idle port number and timestamp when allocating an idle port to the BMC; The recorded I2C port numbers and timestamps are summarized into the historical access list.

3. The method according to claim 2, characterized in that Based on the monitoring results, the CPLD selects the I2C ports of the BMC that have not been called recently as idle ports, including: The CPLD selects unused ports that are not recorded in the historical access list from all I2C ports of the BMC, and randomly selects an unused port as an idle port; If there is no unused port, the target port number with the earliest corresponding timestamp is searched from the historical access list as the free port.

4. The method according to claim 1, characterized in that: Based on the monitoring result, the CPLD selects the I2C ports of the BMC that have not been called recently as idle ports, and binds the first sub-path where the idle port is located and the second sub-path where the target device accessed by the BMC is located in the routing table as the access path of the target device, including: The CPLD sends the information of the idle port to the BMC through the SPI link, so that the BMC sends a series of access instructions for the target device through the first subpath where the idle port is located; The CPLD determines the target device according to the received access instruction, and searches the register slave address of the target device from the pre-stored register slave addresses of each device as the target address; The CPLD binds the second subpath indicated by the target address and the first subpath as an access path of the target device, and forwards data between the first subpath and the second subpath when the BMC interacts with the target device based on the binding relationship.

5. A BMC I2C link balanced distribution system, characterized in that: include: An access monitoring unit, used for CPLD to monitor the time when BMC accesses the device and the information of calling the I2C port, wherein the CPLD includes a first port group and a second port group, each port in the first port group is respectively connected to the I2C port of the BMC, and each port in the second port group is respectively connected to an I2C link with different devices; The path allocation unit is used for the CPLD to filter out the I2C ports of the BMC that have not been called recently as idle ports based on the monitoring results, and bind the first sub-path where the idle port is located and the second sub-path where the target device accessed by the BMC is located as the access path of the target device in the routing table, wherein the first sub-path is formed by connecting the idle port and the corresponding port in the first port group, and the second sub-path is formed by connecting the target device and the corresponding port in the second port group.

6. The system according to claim 5, characterized in that The access monitoring unit comprises: An information recording module, used for responding to a device access request sent by the BMC through the SPI link, and for recording the idle port number and timestamp when the CPLD allocates an idle port to the BMC; The information summary module is used to summarize the recorded I2C port number and timestamp into the historical access list.

7. The system according to claim 6, characterized in that The path allocation unit comprises: A first screening module, used for the CPLD to screen out unused ports that are not recorded in the historical access list from all I2C ports of the BMC, and randomly select an unused port as an idle port; The second screening module is used to search the target port number with the earliest corresponding timestamp from the historical access list as the free port if there is no unused port.

8. The system according to claim 5, characterized in that The path allocation unit comprises: A path sending module, used for the CPLD to send the information of the idle port to the BMC through the SPI link, so that the BMC sends a series of access instructions for the target device through the first sub-path where the idle port is located; The address query module is used for the CPLD to determine the target device according to the received access instruction, and to query the register slave address of the target device from the pre-stored register slave addresses of each device as the target address; The path binding module is used for the CPLD to bind the second sub-path indicated by the target address and the first sub-path as the access path of the target device, and forward data between the first sub-path and the second sub-path when the BMC and the target device interact with each other based on the binding relationship.

9. A terminal, characterized in that: include: processor; A memory for storing execution instructions of the processor; The processor is configured to execute the method according to any one of claims 1 to 4.

10. A computer-readable storage medium storing a computer program, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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