Test data interaction method, test data interaction device and electronic equipment

Abstract

Embodiments of the present application disclose a test data interaction method, a test data interaction device and an electronic device. After receiving a first control signal sent by an application side at a processing side, a target test data collection channel is determined from a plurality of candidate test data collection channels set in a communication link according to the first control signal, then first target test data is acquired from a corresponding test data collection node in the communication link through the target test data collection channel, and then the first target test data is sent to the application side in a burst transmission mode. Thus, real-time, timing and fixed-point test data interaction can be realized, various test data interaction requirements can be met, and test data interaction efficiency and universality can be improved.

Description

Technical Field

[0001] This invention relates to the field of data interaction technology, and in particular to a test data interaction method, a test data interaction device, and an electronic device. Background Technology

[0002] With the rapid development of mobile communication technology, the data transmission rate has been continuously increasing from 1G (1st generation mobile networks) to 5G (5th generation mobile networks), with the transmission volume increasing from kbps to Gbps. This has placed higher demands on data transmission. Therefore, the 5G radio access network has evolved from the two-level structure of 4G / LTE (Long Term Evolution) BBU (Baseband Unit) - RRU (Remote Radio Unit) to a three-level structure of CU (Centralized Unit), DU (Distributed Unit), and RU (Radio Unit). During the development of RU functionality, various complex tests and verifications are required. These tests and verifications involve data collection, data injection, data stimulation, data monitoring, and data analysis to debug the RU functionality software based on the test data. Therefore, high requirements are placed on the efficiency and universality of test data interaction during the testing and verification process.

[0003] In existing technologies, test data can be exchanged through tester simulation. Alternatively, it can be done via JTAG (Joint Test Action Group) debugging (i.e., JTAG debug). Specifically, each node under test defines a TAP (Test Access Port) within the communication link, and these nodes are connected in series via the JTAG interface to form a JTAG chain. Test data is then collected and injected into each node under test through the JTAG chain.

[0004] On the one hand, the existing technology of testing personnel using simulation or JTAG debugging methods cannot fully cover the scenarios of RU functional testing and verification; on the other hand, if a large amount of test data needs to be comprehensively processed and analyzed, the existing technology of defining a TAP inside each node to be tested requires a lot of resources, resulting in resource waste and significant limitations. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a test data interaction method, a test data interaction device, and an electronic device, which can realize real-time, timed, and fixed-point test data interaction, thereby meeting various test data interaction needs and improving the efficiency and universality of test data interaction.

[0006] In a first aspect, embodiments of the present invention provide a test data interaction method, the method comprising:

[0007] Receive the first control signal sent by the application side;

[0008] Determine the target test data acquisition channel corresponding to the first control signal;

[0009] The first target test data is acquired from the corresponding test data acquisition node in the communication link through the target test data acquisition channel; and

[0010] The first target test data is sent to the application side via burst transmission.

[0011] In some embodiments, the method further includes:

[0012] Multiple candidate test data acquisition channels are set according to the multiple test data acquisition nodes in the communication link;

[0013] The step of determining the target test data acquisition channel corresponding to the first control signal includes:

[0014] The target test data acquisition channel is determined from the plurality of candidate test data acquisition channels based on the first control signal.

[0015] In some embodiments, the method further includes:

[0016] Determine the current test data acquisition channel; and

[0017] Switch the current test data acquisition channel to the target test data acquisition channel.

[0018] In some embodiments, sending the first target test data to the application side via burst transmission includes:

[0019] Based on the first target test data, determine one or more first burst data segments; and

[0020] Send the one or more first burst data segments to the application side.

[0021] In some embodiments, sending the one or more first burst data segments to the application side includes:

[0022] The one or more first burst data segments are sent to the application side via direct storage access.

[0023] In some embodiments, the method further includes:

[0024] Received the second control signal sent by the application side;

[0025] Determine the target test data injection channel corresponding to the second control signal; and

[0026] In response to receiving the second target test data sent by the application side, the second target test data is sent to the test data injection node corresponding to the communication link of the target test data injection channel via burst transmission.

[0027] In some embodiments, the method further includes:

[0028] Multiple candidate test data injection channels are set according to multiple test data injection nodes in the communication link;

[0029] The step of determining the target test data injection channel corresponding to the second control signal includes:

[0030] The target test data injection channel is determined from the plurality of candidate test data injection channels according to the second control signal.

[0031] In some embodiments, sending the second target test data to the test data injection node corresponding to the communication link via burst transmission includes:

[0032] Based on the second target test data, determine one or more second burst data segments;

[0033] The one or more second burst data segments are sent to the target test data injection channel at the test data injection node corresponding to the communication link.

[0034] In a second aspect, embodiments of the present invention provide a communication device, the device comprising:

[0035] The first control signal receiving unit is used to receive the first control signal sent by the application side;

[0036] The target test data acquisition channel determination unit is used to determine the target test data acquisition channel corresponding to the first control signal;

[0037] The first target test data acquisition unit is used to acquire the first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel;

[0038] The first target test data sending unit is used to send the first target test data to the application side via burst transmission.

[0039] Thirdly, embodiments of the present invention provide an electronic device, the device comprising:

[0040] Memory is used to store one or more computer program instructions;

[0041] A processor, wherein the one or more computer program instructions are executed by the processor to implement the method as described in the first aspect.

[0042] This invention, upon receiving a first control signal from the application side, determines a target test data acquisition channel from among multiple candidate test data acquisition channels set in the communication link based on the first control signal. Then, it acquires first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel, and subsequently sends the first target test data to the application side via burst transmission. This enables real-time, timed, and location-based test data interaction, meeting various test data interaction needs and improving the efficiency and versatility of test data interaction. Attached Figure Description

[0043] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0044] Figure 1 This is a flowchart of the test data interaction method according to an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of an electronic device in an embodiment of the present invention;

[0046] Figure 3 This is a flowchart of the test data interaction method according to an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of the communication link in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of the FPGA chip architecture in an embodiment of the present invention;

[0049] Figure 6 This is a flowchart illustrating how the first target test data is sent to the application side via burst transmission in an embodiment of the present invention.

[0050] Figure 7 This is a flowchart of the test data interaction method according to an embodiment of the present invention;

[0051] Figure 8This is a schematic diagram of the FPGA chip architecture in an embodiment of the present invention;

[0052] Figure 9 This is a flowchart illustrating how, in this embodiment of the invention, the second target test data is sent to the test data injection node corresponding to the target test data injection channel in the communication link via burst transmission.

[0053] Figure 10 This is a flowchart of the test data interaction device according to an embodiment of the present invention. Detailed Implementation

[0054] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0055] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0056] Unless the context explicitly requires it, words such as "including" or "contains" in the instruction manual should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0057] In the description of this invention, it should be understood that the terms "first," "second," etc., are configured for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0058] The following description uses test data interaction during the development of the Low PHY (Physical) + DEF (Digital Front End) unit in the radio frequency unit (RU) of a macro site (MS) under the 5G standard as an example. The Low PHY, belonging to the baseband processing part of the RU, is used for encoding communication data, physical layer HARQ (Hybrid Automatic Repeat Request) processing, modulation, multi-antenna processing, and signal mapping on corresponding time-frequency resources. The DEF is used for DC signal cancellation, IQ imbalance cancellation, out-of-band noise filtering, and frame detection. Furthermore, the macro site can adopt a RAN (Radio Access Network) architecture, and the macro site can include a DU, CU, and RU. DU, CU, and RU are used to implement some functions of a macro base station. For example, the CU can implement Radio Resource Control (RRC) and Packet Data Convergence Protocol (PDCP) layer functions. The DU can implement Radio Link Control (RLC) and Media Access Control (MAC) functions. The RU is used for transmitting and receiving communication signals. It should be understood that the test data interaction method of this embodiment can also be applied to various scenarios and network devices that require data interaction. Data interaction scenarios include data interaction during the development of DU and CU functions. Network devices include Radio Network Controllers (RNCs), home base stations (e.g., Home Evolved NodeB, HomeNodeB), Micro Stations (MS), and Pico Sites (PS).

[0059] Figure 1 This is a flowchart of the test data interaction method according to an embodiment of the present invention. Figure 1 As shown, the test data interaction process in this embodiment includes the following steps:

[0060] Step S100: Receive the first control signal sent by the application side and determine the target test data acquisition channel corresponding to the first control signal.

[0061] In this embodiment, multiple candidate test data acquisition channels can be pre-set according to the test data acquisition nodes in the communication link. Then, after the processing side receives the first control signal sent by the application side, it can determine the target test data acquisition channel from the multiple candidate test data acquisition channels based on the first control signal. The macro base station can be configured with a controller, which is an electronic device with functions such as data transmission, data processing, and information storage to realize test data interaction. Specifically, refer to... Figure 2 .

[0062] Figure 2 This is a schematic diagram of an electronic device in an embodiment of the present invention. Figure 2 The illustrated electronic device can be a general-purpose data processing chip or device, which can be implemented using MCU (Microcontroller Unit), PLC (Programmable Logic Controller), FPGA (Field-Programmable Gate Array), microcontroller, DSP (Digital Signal Processor), or ASIC (Application-Specific Integrated Circuit), etc. The data processing chip or device includes a general-purpose computer hardware architecture, comprising at least a processor 421 and a memory 422. The processor 421 and memory 422 are connected via a bus 423. The memory 422 is adapted to store instructions or programs executable by the processor 421. The processor 421 can be a standalone microprocessor or a collection of one or more microprocessors. Thus, the processor 421 executes the instructions stored in the memory 422, thereby performing the method flow of the embodiments of the present invention as described above to process data and control other devices. Bus 423 connects the aforementioned components together, and also connects these components to display controller 424, display device, and input / output (I / O) device 425. Input / output (I / O) device 425 may be a mouse, keyboard, modem, network interface, touch input device, motion-sensing input device, printer, and other devices known in the art. Typically, input / output device 425 is connected to the system via input / output (I / O) controller 426.

[0063] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, electronic devices, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can be implemented as a computer program product on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0064] This invention is described with reference to flowchart illustrations of methods, electronic devices, and computer program products according to embodiments of this application. It should be understood that each step in the flowchart can be implemented by computer program instructions.

[0065] These computer program instructions may be stored in a computer-readable storage medium that can direct a computer or other programmable data processing chip or device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including an instruction means, the implementation process of which is described in the instruction means. Figure 1 The function specified in one or more processes.

[0066] These computer program instructions may also be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing chip or device to produce a machine, such that the instructions, which are executed by the processor of the computer or other programmable data processing chip or device, are configured to implement in a process Figure 1 A device for a function specified in one or more processes.

[0067] In this embodiment, the controller includes a processing side and an application side. The processing side and application side are used to implement different functions; they can be processing units deployed on different hardware computing platforms, or multiple software programs or interfaces providing services deployed on a unified hardware platform or cloud platform. In the following description, the controller is an FPGA chip, and the processing side and application side are software programs deployed on a unified hardware platform (i.e., the FPGA chip) based on the test data interaction process described below. The FPGA chip can be a Xilinx multi-core heterogeneous SoC (System on Chip), such as a Zynq SoC.

[0068] Step 200: Obtain the first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel.

[0069] In this embodiment, after determining the corresponding target test data acquisition channel based on the first control signal, the processing side of the FPGA chip can obtain the first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel. In other words, the first target test data stream is acquired from the test data acquisition node through the target test data acquisition channel.

[0070] Step 300: Send the first target test data to the application side via burst transmission.

[0071] In this embodiment, the burst transfer method, also known as a burst transfer, is a method of continuous data transfer between adjacent memories. Because burst transfer is universal and only requires sending the address once during test data transmission—avoiding sending the address for each piece of test data—it improves the efficiency of test data interaction. In other words, the FPGA chip's processing side transmits the first target test data collected by the test data acquisition node to the application side via burst transfer. The memory can be a register, cache, or main memory. This enables test data interaction, improving both efficiency and universality.

[0072] This invention, upon receiving a first control signal from the application side at the processing side, determines a target test data acquisition channel from among multiple candidate test data acquisition channels set in the communication link based on the first control signal. Then, it acquires first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel, and subsequently sends the first target test data to the application side via burst transmission. This enables real-time, timed, and location-based test data interaction, meeting various test data interaction needs and improving the efficiency and versatility of test data interaction.

[0073] Figure 3 This is a flowchart of the test data interaction method according to an embodiment of the present invention. Figure 3 As shown, the test data interaction process in this embodiment includes the following steps:

[0074] Step S110: Set up multiple candidate test data acquisition channels according to multiple test data acquisition nodes in the communication link.

[0075] In this embodiment, since existing technologies using simulation or JTAG debugging by testers cannot fully cover the scenarios of RU functional testing and verification, this invention addresses this by pre-setting multiple candidate test data acquisition channels at multiple test data acquisition nodes in the communication link. Then, based on testing requirements, a target test data acquisition channel is selected from these candidate channels, and test data acquisition is performed. This enables real-time, timed, and location-specific test data interaction, meeting various test data interaction needs without being limited by the resources within the FPGA chip.

[0076] In this embodiment, the communication link is located within the FPGA chip. That is, the communication link can be a circuit pre-configured within the FPGA chip by the tester according to their needs. Specifically, a schematic diagram of the communication link can be found here. Figure 4 .

[0077] Figure 4 This is a schematic diagram of the communication link in an embodiment of the present invention. For example... Figure 4 As shown, the communication link in this embodiment includes a data transmission link a, a data reception link b, and an eCPRI (Enhanced Common Public Radio Interface) interface c. The eCPRI interface c is an evolution of the CPRI (Common Public Radio Interface) protocol, defining the specifications for connections between nodes via a fronthaul network (FTN). These nodes include, for example, eREC nodes and eRE nodes. Furthermore, the eCPRI interface c supports 5G communication, enabling efficient and flexible radio data transmission based on a packet-based frontend transmission network (such as IP or Ethernet).

[0078] In this embodiment, the data transmission link a includes an IFFT (Inverse Fast Fourier Transform) a1, a DUC (Digital Up Converter) a2, a CFR (Crest Factor Reduction) a3, a DPD (Digital Pre-Distortion) a4, a VCA (Voltage Controlled Gain Amplifier) ​​a5, an RF Soc TX (Radio Frequency Soc Transport) a6, and an RF Soc TOR (Radio Frequency Soc TOR) a7. The IFFT a1 is used to convert the communication signal from the frequency domain to the time domain. Specifically, the frequency domain communication data can be processed by taking the conjugate complex number (i.e., inverting the imaginary part), and then the communication data after the conjugate complex number processing can be subjected to an FFT transform to obtain the time domain signal. DUCa2 is used to convert digital signals to analog signals in the data transmission link a, then mixes the analog signals to obtain a desired RF center frequency higher than the original signal, and then amplifies the mixed analog signal (i.e., amplifies the mixed analog signal to an appropriate power level), and then limits the bandwidth of the amplified analog signal before transmitting it through the antenna. CRFa3 is used for peak clipping, that is, to eliminate communication signals exceeding the peak clipping threshold to achieve dynamic peak clipping, thereby avoiding spectral overflow caused by peak-to-average power ratio and improving channel quality. DPDa4 is used to pre-distort the communication signal in the baseband, and then amplifies the pre-distorted communication signal to ensure linear signal output. VCAa5 is used for regulating the communication signal. RF SoC TXa6 is used to transmit communication signals. RF SoC TORa7 is used as a relay node in the communication signal transmission process.

[0079] In this embodiment, the data receiving link b includes an FFT (Fast Fourier Transform) b1, a DDC (Digital Down Converter) b2, and an RF Soc RX (Radio Frequency Soc Receiver) b3. The FFT b1 converts the communication signal from a time-domain signal to a frequency-domain signal. The DDC b2 downconverts the intermediate frequency (IF) digital signal to a baseband signal through digital mixing, followed by filtering to recover the original signal. The downconversion process can be implemented using digital signal processing techniques, including algorithms such as digital filtering, quadrature transformation, sampling, and decimation. The RF Soc RX b3 receives the communication signal.

[0080] In this embodiment, to enable real-time, timed, and location-specific test data interaction to meet various test data interaction requirements, a probe approach is used during the development of the Low PHY+DEF unit of the RF terminal RU to embed test data interaction into the Low PHY+DEF unit of the RF terminal RU. The probe includes a Test Access Point (TAP) and an Injected Point (INP). The TAP corresponds to a candidate test data acquisition channel (e.g., 9b1 in data receiving link b), and the INP corresponds to a candidate test data injection channel (e.g., 5b1 in data receiving link b). Specifically, multiple test data acquisition nodes (e.g., area 9b2 in data receiving link b) and test data injection nodes (e.g., area 5b2 in data receiving link b) are pre-set in the communication link. Then, based on the multiple test data acquisition nodes and test data injection nodes, multiple TAPs and INPs are correspondingly set up through data bypass. Therefore, test data can be acquired through the candidate test data acquisition channel corresponding to the test data acquisition probe TAP, and test data can be injected through the candidate test data injection channel corresponding to the test data injection probe INP. Thus, multiple candidate test data acquisition channels and multiple candidate test data injection channels can be set according to multiple test data acquisition nodes in the communication link.

[0081] In this embodiment, multiple test data acquisition probes (TAPs) include TAP1, TAP2, TAP3, TAP4, TAP5, TAP6, TAP7, TAP8, and TAP9, and multiple test data injection probes (INPs) include INP0, INP1, INP2, INP3, INP4, and INP5. Specifically, for data transmission link a, test data acquisition probe TAP1 and test data injection probe INP0 can be set between eCPRI interface c and IF FFTa1. Test data acquisition probe TAP2 and test data injection probe INP1 can be set between IF FFTa1 and DUCa2. Test data acquisition probe TAP3 and test data injection probe INP2 can be set between DUCa2 and CRFa3. Test data acquisition probe TAP4 can be set between CRFa3 and DPDa4. Test data acquisition probe TAP5 and test data injection probe INP3 can be set between VCAa5 and RF SocTXa6. Set up test data acquisition probe TAP6 between DPDa4 and RF SoC TORa7. For data receiving link b, set up test data acquisition probe TAP7 between eCPRI interface c and FFTb1. Set up test data acquisition probe TAP8 and test data injection probe INP4 between FFTb1 and DDCb2. Set up test data acquisition probe TAP9 and test data injection probe INP5 between DDCb2 and RF SoC RXb3. This enables real-time, timed, and location-specific test data exchange.

[0082] In this embodiment, multiple test data acquisition probes (TAPs) including TAP1, TAP2, TAP3, TAP4, TAP5, TAP6, TAP7, TAP8, and TAP9, and multiple test data injection probes (INPs) including INP0, INP1, INP2, INP3, INP4, and INP5 are used as examples for illustration. It should be understood that this embodiment of the invention does not limit the number of test data acquisition probes (TAPs) and test data injection probes (INPs) set. Testers can set different numbers of test data acquisition probes (TAPs) and test data injection probes (INPs) according to test requirements. Correspondingly, testers can also set different numbers of test data acquisition nodes and test data injection nodes according to test requirements.

[0083] Step S120: Receive the first control signal sent by the application side and determine the target test data acquisition channel corresponding to the first control signal.

[0084] In this embodiment, the first control signal can be a test data acquisition command. Specifically, the processing side receives the test data acquisition command sent by the application side and determines the corresponding target test data acquisition channel based on the test data acquisition command. Further, a schematic diagram of the FPGA chip architecture in this embodiment can be found by referring to... Figure 5 .

[0085] Figure 5 This is a schematic diagram of the FPGA chip architecture in an embodiment of the present invention. Figure 5 As shown, the FPGA chip in this embodiment includes a processing side 1, an application side 2, and a memory 3. The processing side 1 includes a first channel controller 11 and a first test data transmitter 12. The first data transmitter 12 includes a first cache 121, a first burst transmission controller 122, and an FB DMA (Free Burst Direct Memory Access) interface 123.

[0086] In this embodiment, processing side 1 can be PL (Programmable Logic), which is the part related to the FPGA. Application side 2 can be PS (Processing System), which is the part of the ARM (Advanced RISC Machines) SoC that is independent of the FPGA.

[0087] Optionally, application side 2 can also be an APP (Application), such as a browser or various other types of applications.

[0088] In this embodiment, since existing technologies using simulation or JTAG debugging by testers cannot fully cover the scenarios of RU functional testing and verification, this embodiment addresses this issue by pre-setting multiple test data acquisition nodes and test data injection nodes in the FPGA chip communication link. Then, based on these multiple test data acquisition nodes and test data injection nodes, multiple test data acquisition probes (TAPs) and multiple test data injection probes (INPs) are correspondingly set up through data bypass. This allows testers to control the processing side (PL) via the application side 2 (PS) to select the corresponding test data acquisition channel and test data injection channel based on the set test data acquisition probes (TAPs) and test data injection probes (INPs), thereby achieving test data interaction in the communication link. In other words, the PL is treated as a part related to the FPGA, and test data interaction is performed through probes within the FPGA chip circuitry via the PL. This enables real-time, timed, and location-specific test data interaction, without being limited by the resources within the FPGA chip.

[0089] In this embodiment, the form of test data interaction, including test data acquisition and test data injection, is used as an example for explanation. It should be understood that this embodiment of the invention does not limit the form of test data interaction; other forms of test data interaction may include test data stimulation, test data monitoring, and test data analysis.

[0090] Optionally, communication between processing side 1 and application side 2 (i.e., PL and PS) can be implemented through bus interfaces such as AXI4 (Advanced Dexterity Interface), AXI-Lite, and AXI-Stream. AXI4 is used for high-performance address-mapped communication and is an address-mapped interface that allows for a maximum of 256 burst data transfers. AXI4-Lite is a lightweight address-mapped single-transmission interface, characterized by its smaller logic unit footprint, making it suitable for address-mapped communication buses with lower throughput. AXI-Stream is used for high-speed streaming data transfer, allowing for unlimited burst data transfer sizes.

[0091] In this embodiment, the first channel controller 11 can be a MUX controller, which belongs to the custom test data acquisition channel control logic and is used for channel switching. The first channel controller 11 can be located outside the first test data transmitter 12.

[0092] Optionally, the first channel controller 11 can also be located within the first test data transmitter 12. Alternatively, the first channel controller 11 can be located in the Low PHY+DEF unit of the RF terminal RU. That is, by setting the first channel controller 11 in the functional software developed for the RF terminal RU, channel switching can be directly performed to obtain the required test data from the communication link. This improves the versatility of test data interaction.

[0093] In this embodiment, the first test data transmitter 12 can be an RTS (Request To Send) for transmitting the first target test data.

[0094] In this embodiment, the first cache 121 can be FB DMA wF I FO (Free Burst Direct Memory Access w ite First Input First Output) to cache the collected test data.

[0095] In this embodiment, the first burst transmission controller 122 can be wBurst Controller, which belongs to custom burst data control logic.

[0096] In this embodiment, the FB DMA interface 123 is used for test data transmission via direct memory access.

[0097] Optionally, memory 3 can be DDR memory (Double Data Rate, Synchronous Dynamic Random Access Memory).

[0098] In the following description, MUX Controller is also known as the first channel controller 11, RTS is also known as the first data transmitter 12, FB DMA wFIFO is also known as the first buffer 121, and wBurst Controller is also known as the first burst transmission controller 122.

[0099] In this embodiment, the tester can send a first control signal from the application side 2 to the MUX Control in the processing side 1. The MUX Control can then determine the target test data acquisition channel from the multiple test data acquisition channels corresponding to the multiple test data acquisition probes (TAPs) based on the first control signal.

[0100] In an optional implementation, the first control signal may include a target test data acquisition channel number and / or a test data acquisition probe (TAP) identifier. Then, the MUX Control can determine a target test data acquisition channel from multiple candidate test data acquisition channels corresponding to multiple test data acquisition probes (TAPs) based on the first control signal.

[0101] In another alternative implementation, the first control signal may also include multiple target test data acquisition channel numbers and / or multiple test data acquisition probe (TAP) identifiers. Then, the MUX Control can determine multiple target test data acquisition channels from multiple candidate test data acquisition channels corresponding to the multiple test data acquisition probes (TAPs) based on the first control signal.

[0102] Step S130: Determine the current test data acquisition channel.

[0103] In this embodiment, after receiving the first control signal sent by the application side 1, the MUX Control determines one or more current test data acquisition channels.

[0104] In this embodiment, steps S120 and S130 can be executed in the current order. Steps S120 and S130 can also be executed simultaneously. Step S130 can also be executed before step S120.

[0105] Step S140: Switch the current test data acquisition channel to the target test data acquisition channel.

[0106] In an optional implementation, if the current test data acquisition channel is different from the target test data acquisition channel, the MUX Control switches the current test data acquisition channel to the target test data acquisition channel. For example, if the current test data acquisition channel is the test data acquisition channel corresponding to test data acquisition probe TAP0, and the target test data acquisition channel is the test data acquisition channel corresponding to test data acquisition probe TAP1, then the MUX Control switches the test data acquisition channel corresponding to test data acquisition probe TAP0 to the test data acquisition channel corresponding to test data acquisition probe TAP1.

[0107] In another alternative implementation, if the current test data acquisition channel is the same as the target test data acquisition channel, the MUX Control does not need to switch the data acquisition channel.

[0108] Step S150: Obtain the first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel.

[0109] Optionally, the first control signal may also include the length of the first target test data. The tester can set the length of the first target test data to be collected via the application side 2, and the MUX Controller can then acquire the corresponding length of the first target test data based on the first control signal. For example, in time units, test data for one wireless frame, i.e., 10ms of test data, can be acquired.

[0110] In an optional implementation, the MUX Controller acquires target test data from a corresponding test data acquisition node in the communication link based on the test data acquisition probe (TAP) corresponding to a target test data acquisition channel.

[0111] In another optional implementation, the MUX Controller acquires multiple first target test data from multiple test data acquisition probes (TAPs) corresponding to multiple target test data acquisition channels at multiple test data acquisition nodes in the communication link.

[0112] In this embodiment, after acquiring the first target test data, the MUX Control bypasses the first target test data to the FB DMA wF I FO in the RTS.

[0113] Step S160: Send the first target test data to the application side via burst transmission.

[0114] In this embodiment, step S160 includes steps S161-S163. Specifically, refer to... Figure 6 .

[0115] Figure 6 This is a flowchart illustrating how the first target test data is sent to the application side via burst transmission in an embodiment of the present invention. For example... Figure 6 As shown, the process of sending the first target test data to the application side via burst transmission in this embodiment includes the following steps:

[0116] Step S161: Determine one or more first burst data segments based on the first target test data.

[0117] In this embodiment, the tester can send a first communication signal to wBurst Control via processing side 1. This first communication signal includes a first target test data length to indicate the first target test data length to wBurst Control. wBurst Control then calculates the number of Burst transmissions based on the required first target test data length. If wBurst Control detects that the FB DMA wFIFO is not empty, i.e., the FB DMA wFIFO contains the first target test data, wBurst Control sends a request signal to FB DMA interface 123. This request signal can be an FB DMA WREQ pulse signal, used to request a Burst transmission from FB DMA interface 123. Further, after receiving the request signal, FB DMA interface 123 sets FB DMA WREADY to a high level to indicate that wBurst Control is currently idle and completes the handshake. Then, wBurst Control reads the first target test data from the FB DMA wFIFO and determines one or more first burst data segments based on the first target test data. In other words, wBurstControl converts the first target test data stored in the FB DMA wFIFO into one or more first burst data segments. Each burst data segment represents the bit width, or data length, of each transmitted data segment, such as 1 byte, 2 bytes, 4 bytes, and 8 bytes, with each byte ranging from 0 to 0xff (hexadecimal). The data length can be set by the tester or automatically by wBurstControl.

[0118] Optionally, a burst data segment may include multiple data segments with a set bit width.

[0119] Optionally, upon receiving a request signal from wBurst Controller, FB DMA interface 123 can set FB DMAWREADY low to indicate that wBurst Controller is currently busy. wBurst Controller can then poll the request signal sent to wBurst Controller, thus completing the handshake and initiating the first target test data transmission.

[0120] Optionally, the request signal may include the number of Burst transmissions, in which case the FB DMA interface 123 may determine the number of Burst transmissions (i.e., wBURST TI ME) based on the request signal.

[0121] Step S163: Send one or more first burst data segments to the application side.

[0122] In this embodiment, the FB DMA interface 123 can send one or more first burst data segments stored in the FB DMA wFIFO to the application side via the AXI bus interface through the wBurst Control via direct storage access.

[0123] In this embodiment, after the FB DMA interface 123 completes a BURST transmission (that is, the FB DMA interface 123 sends all the first burst data segments of this BURST transmission to the application side 2), it sets FB DMA wREADY to a low level and increments wBURST TIME by 1, waiting for the next send request signal of wBurst Control, and then performs another BURST transmission.

[0124] Optionally, after receiving one or more first burst data segments sent by the FB DMA interface 123, application side 2 writes one or more first burst data segments into memory 3. Further, application side 2 converts the one or more first burst data segments stored in memory 3 into test data of a predetermined format, and stores the test data of the predetermined format in a preset path of application side 2, awaiting subsequent processing by testers, thus completing the test data acquisition.

[0125] Optionally, after the handshake is completed at the FB DMA interface 123, wBurst Control can perform slice framing based on the first target test data stored in the FB DMA wF IFO. Then, the FB DMA interface 123 sends the sliced ​​and framed first target test data stored in the FB DMA wF IFO to the application side 2 via direct store access through wBurst Control. The application side 2 writes the sliced ​​and framed first target test data into memory 3, and then replaces the sliced ​​and framed first target test data stored in memory 3 with test data of a predetermined format. The test data of the predetermined format is stored in a preset path on the application side 2, waiting for the tester to call and process it later, and the test data acquisition is completed.

[0126] Optionally, the test data in the predetermined format can be in txt text format.

[0127] This invention, upon receiving a first control signal from the application side at the processing side, determines a target test data acquisition channel from among multiple candidate test data acquisition channels set in the communication link based on the first control signal. Then, it acquires first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel, and subsequently sends the first target test data to the application side via burst transmission. This enables real-time, timed, and location-based test data interaction, meeting various test data interaction needs and improving the efficiency and versatility of test data interaction.

[0128] Figure 7 This is a flowchart of the test data interaction method according to an embodiment of the present invention. Figure 7 As shown, the process of the test data interaction method in this embodiment includes the following steps:

[0129] Step S210: Set up multiple candidate test data injection channels according to multiple test data injection nodes in the communication link.

[0130] In this embodiment, since the existing technology's simulation or JTAG debugging methods cannot fully cover the scenarios of RU functional testing and verification, this embodiment of the invention can pre-set multiple candidate test data injection channels corresponding to multiple test data injection nodes in the communication link. Then, the processing side selects the target test data injection channel from the multiple candidate test data injection channels according to the test requirements, and then performs test data injection. This enables real-time, timed, and fixed-point test data interaction, thus meeting various test data interaction requirements. Specifically, multiple test data injection probes (INPs) can be embedded in the Low PHY+DEF unit of the RF RU to achieve test data interaction. That is, multiple test data injection nodes are pre-set in the communication link, and then multiple test data injection probes (INPs) are set accordingly through data bypass, with each test data injection probe (INP) corresponding to a candidate test data injection channel. The specific implementation method is similar to... Figure 4 The embodiments shown are similar, and the present invention will not be described in detail here.

[0131] Step S220: Receive the second control signal sent by the application side and determine the target test data injection channel corresponding to the second control signal.

[0132] In this embodiment, the second control signal can be a test data injection command. Specifically, the processing side receives the test data injection command sent by the application side and determines the corresponding target test data injection channel based on the test data injection command. Further, a schematic diagram of the FPGA chip architecture in this embodiment can be found by referring to... Figure 8 .

[0133] Figure 8 This is a schematic diagram of the FPGA chip architecture in an embodiment of the present invention. Figure 8 As shown, the FPGA chip in this embodiment includes a processing side 4, an application side 5, and memory 6. The processing side 4 includes a second test data transfer unit 41 and a Low PHY+DEF unit 42. The second test data transfer unit 41 includes an FB DMA interface 411, a second burst transfer controller 412, and a second buffer 413. The Low PHY+DEF unit 42 includes a second channel controller 421.

[0134] In this embodiment, the processing side 4 can be a PL (Processing Logic Provider), and the application side 5 can be a PS (Application Power Provider). Communication between the processing side 4 and the application side 5 can be achieved through bus interfaces such as AXI4, AXI-Lite, and AXI-Stream. The specific real-time method is... Figure 5 The embodiments shown are similar, and the present invention will not be described in detail here.

[0135] Optionally, application side 5 can also be an app.

[0136] In this embodiment, since existing technologies using simulation or JTAG debugging by testers cannot fully cover the scenarios of RU functional testing and verification, this embodiment addresses this issue by having the application side 5 (PS) control the processing side 4 (PL) to select the corresponding test data acquisition channel and test data injection channel based on the set test data acquisition probe TAP and test data injection probe INP, thereby achieving test data interaction in the communication link. In other words, the processing side 4 (PL) is treated as the FPGA-related part, and test data interaction is performed through probes within the FPGA chip circuitry via the processing side 4. This enables real-time, timed, and location-specific test data interaction, unrestricted by the resources within the FPGA chip. Furthermore, it allows for a cyclical test data injection and acquisition process.

[0137] In this embodiment, the second channel controller 421 is located in the Low PHY+DEF unit 42. That is, the second channel controller 421 is integrated into the functional software developed for the RF terminal RU, enabling direct channel switching to inject test data. This improves the versatility of test data interaction. The second channel controller 421 can be a SwitchController, belonging to the custom test data injection channel control logic, used for channel switching.

[0138] Optionally, the second channel controller 421 can also be located outside of the Low PHY+DEF unit 42 and the second test data transmitter 41. Alternatively, the second channel controller 421 can be located within the second test data transmitter 41.

[0139] In this embodiment, the second test data transmitter 41 can be an RTS for transmitting the second target test data.

[0140] In this embodiment, the FB DMA interface 411 is used for test data transmission via direct memory access.

[0141] In this embodiment, the second burst transmission controller 412 can be rBurst Controller, which belongs to custom burst data control logic.

[0142] In this embodiment, the second cache 413 can be an FB DMA rFI FO, and... Figure 5 The FB DMA wF I FO shown is similar and is used to cache the test data that needs to be injected.

[0143] Optionally, memory 6 can be DDR memory.

[0144] In the following description, Switch Controller is the second channel controller 421, rBurst Controller is the second burst transmission controller 412, and FB DMA rFI FO is the second buffer 413.

[0145] In this embodiment, the tester can send a second control signal to the Switch Control in the Low PHY+DEF unit 42 of the processing side 4 through the application side 5. Then, the Switch Control can determine the target test data injection channel from the multiple test data injection channels corresponding to the multiple test data injection probes I NP according to the second control signal.

[0146] In an optional implementation, the second control signal may include a target test data injection channel number and / or a test data injection probe I NP identifier, then the Switch Control can determine a target test data injection channel from multiple candidate test data injection channels corresponding to multiple test data injection probes I NP according to the second control signal.

[0147] In another alternative implementation, the second control signal may also include multiple target test data injection channel numbers and / or multiple test data injection probe I NP identifiers. Then, the Switch Control can determine multiple target test data injection channels from multiple candidate test data injection channels corresponding to the multiple test data injection probes I NPs based on the second control signal.

[0148] Step S230: Determine the current test data injection channel.

[0149] In this embodiment, after receiving the second control signal sent by the application side 5, the Switch Control determines one or more current test data injection channels.

[0150] In this embodiment, steps S220 and S230 can be executed in the current order. Steps S220 and S230 can also be executed simultaneously. Step S230 can also be executed before step S220.

[0151] Step S240: Switch the current test data injection channel to the target test data injection channel.

[0152] In an optional implementation, if the current test data injection channel is different from the target test data injection channel, the Switch Control switches the current test data injection channel to the target test data injection channel. For example, if the current test data injection channel is the test data injection channel corresponding to test data injection probe I NP1, and the target test data injection channel is the test data injection channel corresponding to test data injection probe I NP2, then the Switch Control switches the test data injection channel corresponding to test data injection probe I NP1 to the test data injection channel corresponding to test data injection probe I NP2.

[0153] In another alternative implementation, if the current test data injection channel is the same as the target test data injection channel, the Switch Controller does not need to switch the data injection channel.

[0154] Step S250: Receive the second target test data sent by the application side, and send the second target test data to the test data injection node corresponding to the target test data injection channel in the communication link through burst transmission.

[0155] In this embodiment, step S250 includes steps S251 and S252. Specifically, refer to... Figure 9 .

[0156] Figure 9 This is a flowchart illustrating how, in an embodiment of the present invention, the second target test data is sent to the test data injection node corresponding to the target test data injection channel on the communication link via burst transmission. For example... Figure 9 As shown, the process of sending the second target test data to the test data injection node corresponding to the target test data injection channel in the communication link via burst transmission in this embodiment includes the following steps:

[0157] Step S251: Determine one or more second burst data segments based on the second target test data.

[0158] In this embodiment, the tester can store the second target test data to be injected in a preset path on the application side 5 and write the second target test data to be injected into memory 6. Further, the application side 5 sends a second communication signal to the rBurst Control in the processing side 4. The second communication signal includes the length of the second target test data to indicate the length of the second target test data to the rBurst Control. Then, the rBurst Control calculates the number of Burst transmissions based on the length of the second target test data to be transmitted. Simultaneously, the rBurst Control sends a request signal to the FB DMA interface 411. The request signal can be an FB DMA RREQ pulse signal, which is used to request a Burst transmission from the FB DMA interface 411. Further, after receiving the request signal, the FB DMA interface 411 sets the FB DMA RBUSY to a high level to indicate that the rBurst Control is currently idle and completes the handshake. Then, the rBurst Control obtains the second target test data from the preset path on the application side 5 through the FB DMA interface 411 and determines one or more second burst data segments based on the second target test data.

[0159] In this embodiment, the FB DMA interface 411 can obtain the second target test data from the application side 5 through the AXI bus interface using direct storage access, and then send the second target test data to rBurstControl.

[0160] Optionally, upon receiving a request signal from rBurst Controller, FB DMA interface 411 can set FB DMARBUSY low to indicate that rBurst Controller is currently busy. Then, rBurst Controller can poll the request signal sent to rBurst Controller to complete the handshake and achieve the second target test data transmission.

[0161] Optionally, the request signal may include the number of Burst transmissions, in which case the FB DMA interface 411 may determine the number of Burst transmissions (i.e., rBURST TI ME) based on the request signal.

[0162] Step S252: Send one or more second burst data segments to the test data injection node corresponding to the target test data injection channel in the communication link.

[0163] In this embodiment, the rBurst Controller can store one or more second burst data segments into the FBDMA rFI FO. Further, the processing side 4 may also include a test data injection controller, which can be an Injected Controller, belonging to a type of test data injection logic. If the Injected Controller detects that the FBDMA rFI FO is not empty, the Injected Controller continuously reads one or more second burst data segments from the FBDMA rFI FO, and injects these one or more second burst data segments into the test data injection node corresponding to the target test data injection channel on the communication link via the Switch Controller, thus completing the test data injection.

[0164] In this embodiment, after the FB DMA interface 411 completes a BURST transmission, it sets the FB DMA RVALI D to a low level and increments rBURST TIME by 1, waiting for the next send request signal from rBurst Control before performing another BURST transmission.

[0165] This invention, upon receiving a second control signal from the application side at the processing side, determines a target test data injection channel from among multiple candidate test data injection channels set in the communication link based on the second control signal. After receiving the second target test data from the application side at the processing side, it transmits the second target test data to the corresponding test data injection node of the target test data injection channel in the communication link via burst transmission. This enables real-time, timed, and location-based test data interaction, meeting various test data interaction needs and improving the efficiency and versatility of test data interaction.

[0166] Figure 10 This is a flowchart of the test data interaction device according to an embodiment of the present invention. Figure 10 The illustrated embodiment's test data interaction device includes a first control signal receiving unit 411, a target test data acquisition channel determining unit 412, a first target test data acquisition unit 413, and a first target test data sending unit 414. The first control signal receiving unit 411 receives a first control signal sent by the application side. The target test data acquisition channel determining unit 412 determines the target test data acquisition channel corresponding to the first control signal. The first target test data acquisition unit 413 acquires first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel. The first target test data sending unit 414 sends the first target test data to the application side via burst transmission.

[0167] In some embodiments, the test data interaction device further includes:

[0168] A candidate test data acquisition channel setting unit is used to set multiple candidate test data acquisition channels according to multiple test data acquisition nodes in the communication link;

[0169] The target test data acquisition channel determination unit 412 is further configured to determine the target test data acquisition channel from among the plurality of candidate test data acquisition channels according to the first control signal.

[0170] In some embodiments, the test data interaction device further includes:

[0171] The current test data acquisition channel determination unit is used to determine the current test data acquisition channel; and

[0172] The channel switching unit is used to switch the current test data acquisition channel to the target test data acquisition channel.

[0173] In some embodiments, the first target test data sending unit 414 is further configured to:

[0174] Based on the first target test data, determine one or more first burst data segments; and

[0175] Send the one or more first burst data segments to the application side.

[0176] In some embodiments, the first target test data sending unit 414 is further configured to:

[0177] The one or more first burst data segments are sent to the application side via direct storage access.

[0178] In some embodiments, the test data interaction device further includes:

[0179] The second control signal receiving unit is used to receive the second control signal sent by the application side;

[0180] The target test data injection channel determination unit is used to determine the target test data injection channel corresponding to the second control signal; and

[0181] The second target test data sending unit is used to send the second target test data to the test data injection node corresponding to the communication link of the target test data injection channel in response to receiving the second target test data sent by the application side, through burst transmission.

[0182] In some embodiments, the test data interaction device further includes:

[0183] A candidate test data injection channel setting unit is used to set multiple candidate test data injection channels according to multiple test data injection nodes in the communication link;

[0184] The target test data injection channel determination unit is further configured to determine the target test data injection channel from among the plurality of candidate test data injection channels according to the second control signal.

[0185] In some embodiments, the second target test data sending unit is further configured to:

[0186] Based on the second target test data, determine one or more second burst data segments;

[0187] The one or more second burst data segments are sent to the target test data injection channel at the test data injection node corresponding to the communication link.

[0188] This invention, upon receiving a first control signal from the application side at the processing side, determines a target test data acquisition channel from among multiple candidate test data acquisition channels set in the communication link based on the first control signal. Then, it acquires first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel, and subsequently sends the first target test data to the application side via burst transmission. This enables real-time, timed, and location-based test data interaction, meeting various test data interaction needs and improving the efficiency and versatility of test data interaction.

[0189] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principle of the invention should be included within the scope of protection of the invention.

Claims

1. A test data interaction method, characterized in that, The method includes: Upon receiving a first control signal sent by the application side, the first control signal includes the test data acquisition probe identifier corresponding to the target test data acquisition channel and the length of the first target test data to be acquired. The test data acquisition probe is embedded in the test data acquisition node of the communication link through a data bypass method, and each test data acquisition probe corresponds to a candidate test data acquisition channel. Determine the target test data acquisition channel corresponding to the first control signal; The first target test data is acquired from the corresponding test data acquisition node in the communication link through the target test data acquisition channel; and The first target test data is sent to the application side via burst transmission. The method further includes: Multiple candidate test data acquisition channels are set according to the multiple test data acquisition nodes in the communication link; The step of determining the target test data acquisition channel corresponding to the first control signal includes: The target test data acquisition channel is determined from the plurality of candidate test data acquisition channels according to the first control signal; Determine the current test data acquisition channel; and Switch the current test data acquisition channel to the target test data acquisition channel; The step of sending the first target test data to the application side via burst transmission includes: Based on the first target test data, determine one or more first burst data segments; and Send the one or more first burst data segments to the application side.

2. The test data interaction method according to claim 1, characterized in that, Sending the one or more first burst data segments to the application side includes: The one or more first burst data segments are sent to the application side via direct storage access.

3. The test data interaction method according to claim 1, characterized in that, The method further includes: Received the second control signal sent by the application side; Determine the target test data injection channel corresponding to the second control signal; and In response to receiving the second target test data sent by the application side, the second target test data is sent to the test data injection node corresponding to the communication link of the target test data injection channel via burst transmission.

4. The test data interaction method according to claim 3, characterized in that, The method further includes: Multiple candidate test data injection channels are set according to multiple test data injection nodes in the communication link; The step of determining the target test data injection channel corresponding to the second control signal includes: The target test data injection channel is determined from the plurality of candidate test data injection channels according to the second control signal.

5. The test data interaction method according to claim 3, characterized in that, The step of sending the second target test data to the target test data injection channel at the test data injection node corresponding to the communication link via burst transmission includes: Based on the second target test data, determine one or more second burst data segments; The one or more second burst data segments are sent to the target test data injection channel at the test data injection node corresponding to the communication link.

6. A test data interaction device, characterized in that, The device includes: The first control signal receiving unit is used to receive the first control signal sent by the application side. The first control signal includes the test data acquisition probe identifier corresponding to the target test data acquisition channel and the length of the first target test data to be acquired. The test data acquisition probe is embedded in the test data acquisition node of the communication link through a data bypass method. Each test data acquisition probe corresponds to a candidate test data acquisition channel. The target test data acquisition channel determination unit is used to determine the target test data acquisition channel corresponding to the first control signal; The first target test data acquisition unit is used to acquire the first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel; The first target test data sending unit is used to send the first target test data to the application side via burst transmission. The device further includes: The candidate test data acquisition channel setting unit is used to set multiple candidate test data acquisition channels according to multiple test data acquisition nodes in the communication link. The target test data acquisition channel determination unit is also used for: The target test data acquisition channel is determined from the plurality of candidate test data acquisition channels according to the first control signal; Determine the current test data acquisition channel; Switch the current test data acquisition channel to the target test data acquisition channel; The first target test data sending unit is further configured to: Based on the first target test data, determine one or more first burst data segments; and Send the one or more first burst data segments to the application side.

7. An electronic device, characterized in that, The device includes: Memory is used to store one or more computer program instructions; A processor, wherein the one or more computer program instructions are executed by the processor to implement the method according to any one of claims 1-5.

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