Semiconductor structure and method for manufacturing semiconductor structure

Abstract

The embodiments of the present application belong to the field of semiconductor manufacturing technology, and specifically relate to a semiconductor structure and a method for manufacturing the semiconductor structure, which is used to solve the problem in related technologies that two types of storage units are usually stacked in a direction perpendicular to the substrate, making the process cumbersome and reducing production efficiency. It includes a substrate, the substrate includes a first array area and a second array area; a first storage array consisting of a plurality of first storage structures is provided on the first array area; and a second storage array consisting of a plurality of second storage structures is provided on the second array area. Compared to the related technology, in which different storage structures are stacked on the substrate, in this embodiment, the first storage structure and the second storage structure are arranged side by side on the substrate, which is conducive to simplifying the process and improving production efficiency.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) consists of a transistor structure and a capacitor structure. The transistors in the transistor structure are electrically connected to the capacitors in the capacitor structure, allowing the transistors to read data from the capacitors or write data to them. Magnetic Random Access Memory (MRAM) consists of a transistor structure and a magnetoresistive tunnel junction (MTJ) inserted between two metal wires. By controlling the transistors in the transistor structure and changing the resistance of the magnetoresistive tunnel junction, data can be read and written.

[0003] In related technologies, to meet the diverse needs of semiconductor memory, memory cells from magnetic random access memory (MRAM) and dynamic random access memory (DRAM) are integrated together. However, these two memory cells are typically stacked perpendicular to the substrate, making the manufacturing process complex and reducing production efficiency. Summary of the Invention

[0004] Embodiments of the present application provide a semiconductor structure and a method for manufacturing the semiconductor structure.

[0005] According to some embodiments, the first aspect of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a first array area and a second array area; a first storage array consisting of a plurality of first storage structures is provided on the first array area; and a second storage array consisting of a plurality of second storage structures is provided on the second array area.

[0006] In some disclosed embodiments, the first storage structure includes a first bit line structure, a first transistor structure and a capacitor structure, the first bit line structure is located below the first transistor, and the capacitor structure is arranged on the corresponding first transistor structure; the second storage structure includes a source line structure, a second bit line structure and a second transistor structure, the source line structure is located below the second transistor structure, and the second bit line structure is located above the second transistor structure; the first bit line structure and the source line structure are arranged on the same layer.

[0007] In some disclosed embodiments, the first bit line structure includes a plurality of first bit lines extending along a first direction and spaced apart in a second direction, the first transistor structure includes a plurality of first active pillars arranged on the first bit lines, the extension direction of the first active pillars is perpendicular to the substrate surface, the projection of the first active pillars on the substrate at least partially overlaps with the projection of the first bit lines on the substrate, and the first direction is perpendicular to the second direction; the source line structure includes a plurality of source lines extending along a first direction and spaced apart in a second direction, the second transistor structure includes a plurality of second active pillars arranged on the source lines, the extension direction of the second active pillars is perpendicular to the substrate surface, the projection of the second active pillars on the substrate at least partially overlaps with the projection of the source lines on the substrate; the first active pillars and the second active pillars are arranged in the same layer.

[0008] In some disclosed embodiments, the first transistor structure includes a plurality of first word lines extending along the second direction and spaced apart in the first direction, the first word lines being disposed around the middle sidewall of the first active pillar; the second transistor structure includes a plurality of second word lines extending along the second direction and spaced apart in the first direction, the second word lines being disposed around the middle sidewall of the second active pillar;

[0009] The first word line and the second word line are arranged in the same layer.

[0010] In some disclosed embodiments, the first storage structure further includes a first contact pad, which is arranged on the corresponding first active pillar; the second storage structure further includes a second contact pad, which is arranged on the corresponding second active pillar; the first contact pad and the second contact pad are arranged on the same layer.

[0011] In some disclosed embodiments, the capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric layer. The capacitor dielectric layer is located between the lower electrode and the upper electrode. The upper electrode is provided in the same layer as the second bit line structure.

[0012] In some disclosed embodiments, the second storage structure includes a contact structure and a magnetic storage structure, and the magnetic storage structure is disposed on a corresponding second contact pad; the magnetic storage structure is electrically connected to the second bit line via the contact structure.

[0013] In some disclosed embodiments, the magnetic storage structure includes a reference layer, a magnetic tunneling barrier layer, and a free layer, wherein the reference layer is disposed on the corresponding second contact pad, and the magnetic tunneling barrier layer is located between the reference layer and the free layer.

[0014] In some disclosed embodiments, the second bit line structure includes a plurality of second bit lines extending along the second direction and spaced apart in the first direction.

[0015] According to some embodiments, a second aspect of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0016] A substrate is provided, the substrate including a first array area and a second array area; a first storage array consisting of a plurality of first storage structures arranged in an array is formed on the first array area; a second storage array consisting of a plurality of second storage structures arranged in an array is formed on the second array area; the first storage array and the second storage array are formed synchronously.

[0017] In some disclosed embodiments, the first storage structure includes a first bit line structure, a first transistor structure and a capacitor structure, and the second storage structure includes a source line structure, a second bit line structure and a second transistor structure; the first bit line structure and the source line structure are formed synchronously on the first array area and the second array area; the first bit line structure is located below the first transistor, and the capacitor structure is arranged on the corresponding first transistor; the source line structure is located below the second transistor structure, and the second bit line structure is located above the second transistor structure.

[0018] In some disclosed embodiments, the first transistor structure includes a plurality of first active pillars, and the second transistor structure includes a plurality of second active pillars; the first active pillars and the second active pillars are formed synchronously; an extension direction of the first active pillar is perpendicular to the substrate surface, and a projection of the first active pillar on the substrate at least partially overlaps with a projection of the first bit line on the substrate; an extension direction of the second active pillar is perpendicular to the substrate surface, and a projection of the second active pillar on the substrate at least partially overlaps with a projection of the source line on the substrate.

[0019] In some disclosed embodiments, the first transistor structure further includes a plurality of first word lines, and the second transistor structure further includes a plurality of second word lines; the first word lines and the second word lines are synchronously formed on the first bit line structure and the source line structure; the plurality of first word lines extend along the second direction and are spaced apart in the first direction, and the first word lines are arranged around the middle side wall of the first active pillar; the plurality of second word lines extend along the second direction and are spaced apart in the first direction, and the second word lines are arranged around the middle side wall of the second active pillar.

[0020] In some disclosed embodiments, the first storage structure further includes a first contact pad disposed on the corresponding first active pillar, and the second storage structure further includes a second contact pad disposed on the corresponding second active pillar; the first contact pad and the second contact pad are formed synchronously on the first active pillar and the second active pillar.

[0021] In some disclosed embodiments, a dielectric layer is formed on the first contact pad and the second contact pad, the dielectric layer having a plurality of capacitor holes, wherein projections of the capacitor holes on the substrate are located in the first array region and at least partially overlap with projections of the first contact pad on the substrate;

[0022] forming a plurality of partial capacitor structures in the capacitor hole;

[0023] removing a portion of the dielectric layer to expose the second contact pad;

[0024] A plurality of magnetic storage structures and contact structures are sequentially formed on the second contact pad.

[0025] In some disclosed embodiments, the capacitor structure includes a lower electrode, an upper electrode and a capacitor dielectric layer, the capacitor dielectric layer is located between the lower electrode and the upper electrode, the second bit line structure includes a plurality of second bit lines located above the contact structure, the plurality of second bit lines extend along the second direction and are spaced apart in the first direction; the upper electrode and the second bit lines are formed synchronously on the capacitor dielectric layer and the contact structure.

[0026] The present invention provides a semiconductor structure and a method for fabricating the same. The structure comprises a substrate comprising a first array region and a second array region; the first array region comprises a first storage array consisting of a plurality of first storage structures; and the second array region comprises a second storage array consisting of a plurality of second storage structures. Compared to related art techniques in which different storage structures are stacked on a substrate, this embodiment arranges the first and second storage structures side by side on the substrate, simplifying the manufacturing process and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0029] Figure 2 A top view of a substrate provided in an embodiment of the present application;

[0030] Figure 3 A flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of a structure for simultaneously forming a first bit line structure and a source line structure in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0032] Figure 5 A schematic structural diagram of the simultaneous formation of a first active pillar and a second active pillar in the method for manufacturing a semiconductor structure provided by an embodiment of the present application;

[0033] Figure 6 A schematic diagram of a structure for simultaneously forming a first word line and a second word line in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of a structure in which a first contact pad and a second contact pad are simultaneously formed in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0035] Figure 8 A schematic diagram of a structure for forming a dielectric layer in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0036] Figure 9 A schematic diagram of a structure in which a portion of a capacitor structure is formed in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0037] Figure 10 A schematic diagram of a structure in which a portion of a dielectric layer is removed in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0038] Figure 11 A schematic structural diagram of a magnetic storage structure formed in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0039] Figure 12 A schematic structural diagram of a contact structure formed in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0040] Figure 13 A schematic structural diagram of the simultaneous formation of an upper electrode and a second bit line structure in a method for manufacturing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0042] The semiconductor structure provided in the embodiment of the present application includes a substrate, such as Figure 1 and Figure 2 As shown, the material of the substrate 10 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as III-V group compounds such as gallium arsenide. The substrate 10 is provided with a peripheral region 13 and an array region adjacent to the peripheral region 13, referring to Figure 2 The peripheral area 13 is located on the left side of the substrate 10 in the illustrated position, and the array area is located on the right side of the substrate 10 in the illustrated position, and the peripheral area 13 can be set on the periphery of the array area. Of course, in some other examples, the relative positions of the peripheral area 13 and the array area can also be set according to actual needs. The peripheral area 13 can be used to form a matching structure with the peripheral circuit, and the array area can be used to form a matching structure with the memory cell. The array area includes a first array area 11 and a second array area 12. Figure 2 , the second array region 12 can be located at the left portion of the array region in the substrate 10 , and the first array region 11 can be disposed at the periphery of the second array region 12 .

[0043] A first memory array consisting of a plurality of first memory structures is provided in the first array area 11, and a second memory array consisting of a plurality of second memory structures is provided in the second array area 12. In this embodiment, the storage principle of the first memory structures in the first memory array is different from the storage principle of the second memory structures in the second memory array. For example, the first memory structures may include memory cells of a dynamic random access memory, and the second memory structures may include memory cells of a magnetic random access memory.

[0044] It is worth noting that dynamic random access memory is a volatile memory device, while magnetic random access memory is a non-volatile memory device. By separately providing a first memory structure with volatile memory characteristics and a second memory structure with non-volatile memory characteristics on the same substrate 10, the flexible storage performance and fast access performance of the semiconductor structure can be further improved.

[0045] An embodiment of the present application provides a semiconductor structure comprising a substrate 10, comprising a first array region 11 and a second array region 12. A first memory array consisting of a plurality of first memory structures is provided on the first array region 11, and a second memory array consisting of a plurality of second memory structures is provided on the second array region 12. Compared to related art techniques in which different memory structures are stacked on substrate 10, this embodiment arranges the first and second memory structures side by side on substrate 10, simplifying the manufacturing process, reducing wiring complexity, and improving production efficiency.

[0046] Continue to refer to Figure 1 In the first array region 11, the first storage structure may include a first bitline structure 21, a first transistor structure, and a capacitor structure. The first bitline structure 21 is located below the first transistor, and the capacitor structure is provided above the corresponding first transistor structure. In the second array region 12, the second storage structure may include a source line structure 22, a second bitline structure 623, and a second transistor structure. The source line structure 22 is located below the second transistor structure, and the second bitline structure 623 is located above the second transistor structure.

[0047] In this embodiment, the first bit line structure 21 and the source line structure 22 can be arranged in the same layer. The first bit line structure 21 and the source line structure 22 have the same height in the direction perpendicular to the surface of the substrate 10, and have the same shape in the cross section parallel to the surface of the substrate 10, so that the first bit line structure 21 and the source line structure 22 can be formed simultaneously, thereby simplifying the process of the semiconductor structure.

[0048] Reference Figure 1 The direction parallel to the substrate 10 in the illustrated position is the first direction, and the direction parallel to the substrate 10 and perpendicular to the first direction in the illustrated position is the second direction. The first bit line structure 21 includes a plurality of first bit lines extending along the first direction and spaced apart in the second direction, and the source line structure 22 includes a plurality of source lines extending along the first direction and spaced apart in the second direction. The first bit line and the source line can be made of the same material to further improve the manufacturing efficiency of the first bit line and the source line. The material of the first bit line and the source line can include a conductive material selected from one or more combinations of doped polysilicon, titanium, titanium nitride, and tungsten.

[0049] like Figure 1As shown, a first isolation structure 211 can be provided between adjacent first bit lines, and a second isolation structure 221 can be provided between adjacent source lines. Since the first bit lines in the first bit line structure 21 and the source lines in the source line structure 22 can be formed simultaneously, the first isolation structure 211 and the second isolation structure 221 can also be formed simultaneously, and the first isolation structure 211 and the second isolation structure 221 can be made of the same material, thereby further simplifying the process of the semiconductor structure. The material of the first isolation structure 211 and the second isolation structure 221 can include, for example, one or a combination of silicon nitride, silicon oxynitride, and silicon oxide.

[0050] In this embodiment, the first transistor structure includes a plurality of first active pillars 311 arranged on the first bit line, and the second transistor structure includes a plurality of second active pillars 312 arranged on the source line. The first active pillars 311 and the second active pillars 312 have the same height in the direction perpendicular to the surface of the substrate 10, and have the same shape in the cross section parallel to the surface of the substrate 10. The first active pillars 311 and the second active pillars 312 can be arranged in the same layer so that the first active pillars 311 and the second active pillars 312 can be formed synchronously, thereby simplifying the process of the semiconductor structure.

[0051] Continue to refer to Figure 1 The first active pillar 311 extends perpendicular to the surface of the substrate 10. The projection of the first active pillar 311 on the substrate 10 at least partially overlaps with the projection of the first bit line on the substrate 10, allowing the first transistor structure to be electrically connected to the first bit line via the first active pillar 311. The second active pillar 312 extends perpendicular to the surface of the substrate 10. The projection of the second active pillar 312 on the substrate 10 at least partially overlaps with the projection of the source line on the substrate 10, allowing the second transistor structure to be electrically connected to the source line via the second active pillar 312. The first active pillar 311 and the second active pillar 312 can be made of the same material. The materials of the first active pillar 311 and the second active pillar 312 may include silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), or other materials, such as Group III-V compounds such as gallium arsenide. The first active pillar 311 and the second active pillar 312 have the same structure, including a source region, a drain region, and a channel region between the source region and the drain region. It is worth noting that in this embodiment, the source line is connected to the source region of the second active pillar 312, and the first bit line is connected to the source region of the first active pillar 311.

[0052] In this embodiment, the first transistor structure also includes multiple first word lines 321, and the second transistor structure also includes multiple second word lines 322. The first word lines 321 and the second word lines 322 can be arranged in the same layer. The first word lines 321 and the second word lines 322 have the same height in the direction perpendicular to the surface of the substrate 10, and have the same shape in the cross-section parallel to the surface of the substrate 10, so that the first word lines 321 and the second word lines 322 can be formed synchronously, thereby simplifying the process of the semiconductor structure.

[0053] Reference Figure 1 A plurality of first word lines 321 extend along the second direction and are spaced apart in the first direction. The first word lines 321 surround the middle sidewall of the first active pillar 311. In this embodiment, the first word lines 321 surround the channel region in the middle of the first active pillar 311, and a first gate dielectric layer may be disposed between the first word lines 321 and the first active pillar 311. A plurality of second word lines 322 extend along the second direction and are spaced apart in the first direction. The second word lines 322 surround the middle sidewall of the second active pillar 312. In this embodiment, the second word lines 322 surround the channel region in the middle of the second active pillar 312, and a second gate dielectric layer may be disposed between the second word lines 322 and the second active pillar 312. The second gate dielectric layer has the same structure and material as the first gate dielectric layer, and the second gate dielectric layer and the first gate dielectric layer may be formed simultaneously. A first insulating structure 314 is provided between the first active pillars 311 to isolate adjacent first active pillars 311. A second insulating structure 324 is provided between the second active pillars 312 to isolate adjacent second active pillars 312. The first insulating structure 314 and the second insulating structure 324 have the same structure and material, and may include one or a combination of silicon nitride, silicon oxynitride, and silicon oxide. The first insulating structure 314 and the second insulating structure 324 may also be formed simultaneously.

[0054] It is worth noting that each first word line 321 is connected to a different first active pillar 311, and adjacent first word lines 321 are not connected. Similarly, each second word line 322 is connected to a different second active pillar 312, and adjacent second word lines 322 are not connected. Those skilled in the art can adjust the width of the first word line 321 or the second word line 322 (herein, "width" refers to the width of the first word line 321 or the second word line 322 in the first direction) so that the first word line 321 or the second word line 322 can connect as many adjacent first active pillars 311 or second active pillars 312 as possible and evenly.

[0055] It is worth noting that the first transistor structure and the second transistor structure in this embodiment are vertical all-around gate transistors (Gate-All-Around, GAA), which has the characteristics of high integration and is conducive to increasing the number of first storage structures and second storage structures per unit area to improve the arrangement density.

[0056] In this embodiment, the first storage structure may further include a plurality of first contact pads 41, and the second storage structure may further include a plurality of second contact pads 42. The first contact pads 41 and the second contact pads 42 may be arranged in the same layer. The first contact pads 41 and the second contact pads 42 have the same height in a direction perpendicular to the surface of the substrate 10, and have the same shape in a cross section parallel to the surface of the substrate 10, so that the first contact pads 41 and the second contact pads 42 can be formed synchronously, thereby simplifying the process of the semiconductor structure.

[0057] Reference Figure 1 , the first contact pad 41 is arranged on the corresponding first active column 311, and the second contact pad 42 is arranged on the corresponding second active column 312. The material of the first contact pad 41 and the second contact pad 42 can be the same, and the material of the first contact pad 41 and the second contact pad 42 can include one or more combinations of tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), and titanium nitride (TiNx). A first insulating block 411 is also arranged between adjacent first contact pads 41, and a second insulating block 421 is also arranged between adjacent second contact pads 42. The structure and material of the first insulating block 411 and the second insulating block 421 are the same, and can include one or more combinations of silicon nitride, silicon oxynitride and silicon oxide. The first insulating block 411 and the second insulating block 421 can also be formed simultaneously.

[0058] like Figure 1 As shown, in the first storage structure, a first dielectric layer 50 and a capacitor structure are disposed on the first transistor structure. A capacitor hole 51 is disposed through the first dielectric layer 50. The projection of the capacitor hole 51 on the substrate 10 at least partially overlaps with the projection of the first contact pad 41 on the substrate 10. Part of the capacitor structure is disposed within the capacitor hole 51 to connect to the first contact pad 41.

[0059] The capacitor structure may include a lower electrode 611, an upper electrode 613, and a capacitor dielectric layer 612, wherein the capacitor dielectric layer 612 is located between the lower electrode 611 and the upper electrode 613. The lower electrode 611 covers the hole wall of the capacitor hole 51, the capacitor dielectric layer 612 covers the surface of the lower electrode 611, and the upper electrode 613 covers the capacitor dielectric layer 612. Of course, the capacitor structure may also include other structures in the related art, which are not specifically limited in the embodiments of the present application.

[0060] like Figure 1As shown, in the second storage structure, a contact structure 622, a magnetic storage structure 621 and a second bit line structure 623 are provided on the second transistor, the magnetic storage structure 621 is provided on the corresponding second contact pad 42; the contact structure 622 is provided on the corresponding magnetic storage structure 621, and further reference is made to Figure 1 The projection of the contact structure 622 on the substrate 10 at least partially overlaps with the projection of the magnetic storage structure 621 on the substrate 10, so that the contact structure 622 is electrically connected to the magnetic storage structure 621. A second bitline structure 623 is disposed on the contact structure 622, and the magnetic storage structure 621 is electrically connected to the second bitline structure 623 via the contact structure 622. The second bitline structure 623 includes a plurality of second bitlines extending along the second direction and spaced apart in the first direction. A first support structure 6211 is further disposed between adjacent magnetic storage structures 621, and a second support structure 6222 is further disposed between adjacent contact structures 622.

[0061] In this embodiment, the upper electrode 613 and the second bit line structure 623 can be set in the same layer, the upper electrode 613 and the second bit line structure 623 can be set in the same layer, the upper electrode 613 and the second bit line structure 623 have the same height in the direction perpendicular to the surface of the substrate 10, and the same shape in the cross section parallel to the surface of the substrate 10, so that the upper electrode 613 and the second bit line structure 623 can be formed synchronously, thereby simplifying the process of the semiconductor structure.

[0062] like Figure 1 As shown, the magnetic storage structure 621 of this embodiment is a magnetic tunnel junction (MTJ), including a reference layer, a magnetic tunneling barrier layer and a free layer. The reference layer is provided on the corresponding second contact pad 42, and the magnetic tunneling barrier layer is located between the reference layer and the free layer. That is, in this embodiment, the magnetic storage structure 621 is a reference layer, a magnetic tunneling barrier layer and a free layer in the direction from close to the substrate 10 to the direction away from the substrate 10. It is worth noting that in another embodiment of the magnetic storage structure 621, the direction from close to the substrate 10 to the direction away from the substrate 10 is a free layer, a magnetic tunneling barrier layer and a reference layer. In a specific implementation, the material of the free layer and the reference layer may include cobalt iron boron (CoFeB), and the material of the magnetic tunneling barrier layer may be magnesium oxide (MgO).

[0063] The following briefly describes the principle behind magnetic storage structure 621: It relies on the quantum tunneling effect to allow electrons to pass through the magnetic tunneling barrier layer. The tunneling probability of polarized electrons is related to the relative magnetization orientations of the reference layer and the free layer. The magnetization orientation of the reference layer remains unchanged. When the magnetization orientations of the reference layer and the free layer are aligned, the tunneling probability of polarized electrons is high, and the magnetic storage structure 621 exhibits a low resistance state. When the magnetization orientations of the reference layer and the free layer are opposite, the tunneling probability of polarized electrons is low, and the magnetic storage structure 621 exhibits a high resistance state. The low and high resistance states of the magnetic storage structure 621 are used to represent the logical states "1" and "0," thereby enabling data storage.

[0064] The present application also provides a method for manufacturing a semiconductor structure, which is used to manufacture the semiconductor structure in the above embodiment. Figure 3 , the steps include:

[0065] Step S101: providing a substrate, wherein the substrate includes a first array region and a second array region.

[0066] like Figure 2 As shown, the substrate 10 is provided with a peripheral region 13 and an array region adjacent to the peripheral region 13. The peripheral region is located at the left portion of the substrate 10 in the illustrated position, and the array region is located at the right portion of the substrate 10 in the illustrated position, and the peripheral region 13 can be provided at the periphery of the array region. The array region includes a first array region 11 and a second array region 12. Figure 2 The first array region 11 is located at the left portion of the array region in the substrate 10 , and the second array region 12 is disposed on the periphery of the first array region 11 .

[0067] In this embodiment, after providing the substrate 10, the following steps are further included:

[0068] Step S102: forming a first memory array consisting of a plurality of first memory structures arranged in an array on the first array area, and forming a second memory array consisting of a plurality of second memory structures arranged in an array on the second array area; the first memory array and the second memory array are formed simultaneously.

[0069] It is worth noting that in the embodiments of the present application, the first storage array and the second storage array are formed simultaneously by synchronously forming the film layer structure in the first storage structure and the film layer structure of the same film layer in the second storage structure. In this embodiment, the storage principle of the first storage structure in the first storage array is different from the storage principle of the second storage structure in the second storage array. For example, the first storage structure may include storage cells of a dynamic random access memory, and the second storage structure may include storage cells of a magnetic random access memory.

[0070] This embodiment provides a method for fabricating a semiconductor structure, including: providing a substrate 10, the substrate 10 including a first array region 11 and a second array region 12; forming a first memory array comprising a plurality of first memory structures arranged in an array on the first array region 11, and forming a second memory array comprising a plurality of second memory structures arranged in an array on the second array region 12; and forming the first memory array and the second memory array simultaneously. Compared to related art methods in which the first and second memory structures are formed in a distributed manner, forming the first and second memory structures simultaneously on the substrate 10 facilitates simplified manufacturing processes and improved production efficiency.

[0071] In this embodiment, refer to Figure 4 、 Figure 5 as well as Figure 6 The first storage structure includes a first bitline structure 21, a first transistor structure, and a capacitor structure. The first bitline structure 21 is located below the first transistor, and the capacitor structure is provided on the corresponding first transistor. The second storage structure includes a source line structure 22, a second bitline structure 623, and a second transistor structure. The source line structure 22 is located below the second transistor structure, and the second bitline structure 623 is located above the second transistor structure. The step of simultaneously forming the first and second storage arrays may include: simultaneously forming the first bitline structure 21 and the source line structure 22 on the first array area 11 and the second array area 12.

[0072] In a specific embodiment, a first isolation structure 211 and a second isolation structure 221 can be simultaneously formed on the first array region 11 and the second array region 12 of the substrate 10 through a deposition process. The first isolation structure 211 and the second isolation structure 221 are used to define a first bit line structure 21 and a source line structure 22. A first bit line structure 21 and a source line structure 22 are then simultaneously formed between adjacent first isolation structures 211 and adjacent second isolation structures 221 through a deposition process. The direction parallel to the substrate 10 in the illustrated position is the first direction, and the direction parallel to the substrate 10 and perpendicular to the first direction in the illustrated position is the second direction. The first bit line structure 21 includes a plurality of first bit lines extending along the first direction and spaced apart in the second direction. The source line structure 22 includes a plurality of source lines extending along the first direction and spaced apart in the second direction. Furthermore, to ensure that the first bit line structure 21 and the source line structure 22 can be deposited and formed simultaneously, the first bit line structure 21 and the source line structure 22 are made of the same material.

[0073] In this embodiment, the first transistor structure may further include a plurality of first active pillars 311, and the second transistor structure may further include a plurality of second active pillars 312; the extension direction of the first active pillars 311 is perpendicular to the surface of the substrate 10, and the projection of the first active pillars 311 on the substrate 10 at least partially overlaps with the projection of the first bit line on the substrate 10; the extension direction of the second active pillars 312 is perpendicular to the surface of the substrate 10, and the projection of the second active pillars 312 on the substrate 10 at least partially overlaps with the projection of the source line on the substrate 10.

[0074] In this embodiment, after the first bit line structure 21 and the source line structure 22 are simultaneously formed on the first array area 11 and the second array area 12 , the first active pillar 311 and the second active pillar 312 are simultaneously formed on the first bit line structure 21 and the source line structure 22 .

[0075] In a specific embodiment, a first initial active pillar and a second initial active pillar can be simultaneously formed on the first bit line structure 21 and the source line structure 22 through a deposition process. To enable the simultaneous formation of the first initial active pillar and the second initial active pillar, the first initial active pillar and the second initial active pillar are made of the same material. After the first initial active pillar and the second initial active pillar are formed, the first active pillar 311 and the second active pillar 312 can be simultaneously formed through three ion implantation techniques. For example, first, the ion injection energy and the type of injected doping ions in the ion injection technology can be controlled to form a drain region at the bottom of the first initial active column and the second initial active column, and then, the ion injection energy and the type of injected doping ions in the ion injection technology can be controlled to form a channel region in the middle of the first initial active column and the second initial active column, and finally, the ion injection energy and the type of injected doping ions in the ion injection technology can be controlled to form a source region at the top of the first initial active column and the second initial active column, wherein the type of doping ions in the drain region can be the same as the type of doping ions in the source region, for example, the doping ions can include N-type ions; the doping ions in the channel region are different from the type of doping ions in the drain region, for example, the doping ions can include P-type ions.

[0076] In this embodiment, the first transistor structure also includes multiple first word lines 321, and the second transistor structure also includes multiple second word lines 322; the multiple first word lines 321 extend along the second direction and are spaced apart in the first direction, and the first word lines 321 are arranged around the middle side wall of the first active pillar 311; the multiple second word lines 322 extend along the second direction and are spaced apart in the first direction, and the second word lines 322 are arranged around the middle side wall of the second active pillar 312.

[0077] In this embodiment, after the first active pillar 311 and the second active pillar 312 are simultaneously formed on the first bit line structure 21 and the source line structure 22 , the first word line 321 and the second word line 322 are simultaneously formed on the first bit line structure 21 and the source line structure 22 .

[0078] In one specific embodiment, a first filling region 313 is defined between adjacent first active pillars 311, and a second filling region 323 is defined between adjacent second active pillars 312. The first and second filling regions 313 and 323 are simultaneously filled with a first insulating material and a second insulating material until the first and second insulating materials cover the source regions of the first and second active pillars 311 and 312. A first conductive layer and a second conductive layer are simultaneously formed on the first and second insulating materials, covering the channel regions of the first and second active pillars 311 and 312. Portions of the first and second conductive layers are removed to simultaneously form first and second word lines 321 and 322. After the first and second word lines 321 and 322 are formed, the first and second insulating materials are continuously filled into the first and second filling regions 313 and 323, so that the first insulating material in the first filling region 313 forms a first insulating structure 314, and the second insulating material in the second filling region 323 forms a second insulating structure 324. It is worth noting that in order to form the first insulating structure 314 and the second insulating structure 324 simultaneously, the first insulating material and the second insulating material are made of the same material. In order to form the first word line 321 and the second word line 322 simultaneously, the first conductive layer and the second conductive layer are made of the same material.

[0079] In this embodiment, refer to Figure 7 The first storage structure further includes a first contact pad 41 disposed on the corresponding first active pillar 311 , and the second storage structure further includes a second contact pad 42 disposed on the corresponding second active pillar 312 .

[0080] In this embodiment, after the first word line 321 and the second word line 322 are synchronously formed on the first bit line structure 21 and the source line structure 22 , the process further includes: synchronously forming the first contact pad 41 and the second contact pad 42 on the first active pillar 311 and the second active pillar 312 .

[0081] In a specific embodiment, the first contact pad 41 and the second contact pad 42 can be formed simultaneously on the first active pillar 311 and the second active pillar 312 through a deposition process. Furthermore, the first insulating block 411 and the second insulating block 421 can also be formed simultaneously between adjacent first contact pads 41 and adjacent second contact pads 42 through a deposition process. Furthermore, to ensure that the first contact pad 41 and the second contact pad 42 can be deposited and formed simultaneously, the first contact pad 41 and the second contact pad 42 are made of the same material. To ensure that the first insulating block 411 and the second insulating block 421 can be deposited and formed simultaneously, the first insulating block 411 and the second insulating block 421 are made of the same material.

[0082] In this embodiment, refer to Figure 8 After the first contact pad 41 and the second contact pad 42 are simultaneously formed on the first active pillar 311 and the second active pillar 312, the method further includes: forming a dielectric layer 50 on the first contact pad 41 and the second contact pad 42, wherein the dielectric layer 50 has a plurality of capacitor holes 51, and the projection of the capacitor holes 51 on the substrate 10 is located in the first array area 11 and at least partially overlaps with the projection of the first contact pad 41 on the substrate 10. By providing the capacitor holes 51 in the dielectric layer 50, a capacitor structure can be defined, and the dielectric layer 50 can also support the capacitor structure to prevent collapse. The dielectric layer 50 shields the second array area 12 and can also prevent other film structures from forming on the second contact pad 42.

[0083] In this embodiment, refer to Figure 9 , after forming the dielectric layer 50, it also includes: forming multiple partial capacitor structures in the capacitor hole 51. The capacitor structure may include a lower electrode 611, an upper electrode 613 and a capacitor dielectric layer 612, and the capacitor dielectric layer 612 is located between the lower electrode 611 and the upper electrode 613. As shown in the figure, the partial capacitor structure includes a lower electrode 611 and a capacitor dielectric layer 612, the lower electrode 611 covers the hole wall of the capacitor hole 51, and the capacitor dielectric layer 612 covers the surface of the lower electrode 611 and fills the capacitor hole 51. Of course, the capacitor structure may also include other structures in the relevant technology, which is not specifically limited in the embodiment of the present application.

[0084] In this embodiment, refer to Figure 10 After forming multiple capacitor structures in the capacitor hole 51 , the method further includes: removing a portion of the dielectric layer 50 to expose the second contact pad 42 , thereby facilitating the subsequent formation of other film layer structures on the second contact pad 42 .

[0085] Reference Figure 11 and Figure 12, a plurality of magnetic storage structures 621 and contact structures 622 are sequentially formed on the second contact pad 42. The magnetic storage structure 621 of this embodiment is a magnetic tunneling junction (MTJ), including a reference layer, a magnetic tunneling barrier layer and a free layer. Its specific structure and working principle are not described in detail here. The projection of the contact structure 622 on the substrate 10 and the projection of the magnetic storage structure 621 on the substrate 10 at least partially overlap, so that the contact structure 622 is electrically connected to the magnetic storage structure 621. In a specific implementation, the magnetic storage structure 621 and the contact structure 622 can be formed by a deposition process. Figure 13 A first supporting structure 6211 is further provided between adjacent magnetic storage structures 621 , and a second supporting structure 6222 is further provided between adjacent contact structures 622 .

[0086] In this embodiment, refer to Figure 13 After sequentially forming a plurality of magnetic storage structures 621 and contact structures 622 on the second contact pad 42 , the method further includes: synchronously forming an upper electrode 613 and a second bit line structure 623 on the capacitor dielectric layer 612 and the contact structure 622 .

[0087] The second bit line structure 623 includes a plurality of second bit lines located above the contact structure 622. The plurality of second bit lines extend along the second direction and are spaced apart in the first direction. The upper electrode 613 covers the capacitor dielectric layer 612. Furthermore, to ensure that the upper electrode 613 and the second bit line structure 623 can be deposited and formed simultaneously, the upper electrode 613 and the second bit line structure 623 are made of the same material.

[0088] Those skilled in the art will clearly understand that for the sake of convenience and brevity, the division of the above-mentioned functional modules is only used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first array region and a second array region; A first memory array is formed on the first array area, comprising a plurality of first memory structures arranged in an array; and a second memory array is formed on the second array area, comprising a plurality of second memory structures arranged in an array; the first memory array and the second memory array are formed simultaneously; The first storage structure includes a first bit line structure, a first transistor structure and a capacitor structure, and the second storage structure includes a source line structure, a second bit line structure and a second transistor structure; forming the first bit line structure and the source line structure simultaneously on the first array region and the second array region; The first bit line structure is located below the first transistor, and the capacitor structure is provided on the corresponding first transistor; The source line structure is located below the second transistor structure, and the second bit line structure is located above the second transistor structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The first transistor structure includes a plurality of first active pillars, and the second transistor structure includes a plurality of second active pillars; synchronously forming the first active pillar and the second active pillar; An extension direction of the first active pillar is perpendicular to a surface of the substrate, and a projection of the first active pillar on the substrate at least partially overlaps with a projection of the first bit line on the substrate; An extension direction of the second active pillar is perpendicular to the surface of the substrate, and a projection of the second active pillar on the substrate at least partially overlaps with a projection of the source line on the substrate.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The first transistor structure further includes a plurality of first word lines, and the second transistor structure further includes a plurality of second word lines; Synchronously forming a first word line and a second word line on the first bit line structure and the source line structure; Multiple first word lines extend along the second direction and are spaced apart in the first direction, and the first word lines are arranged around the middle side wall of the first active pillar; multiple second word lines extend along the second direction and are spaced apart in the first direction, and the second word lines are arranged around the middle side wall of the second active pillar.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The first storage structure further includes a first contact pad disposed on the corresponding first active pillar, and the second storage structure further includes a second contact pad disposed on the corresponding second active pillar; The first contact pad and the second contact pad are simultaneously formed on the first active pillar and the second active pillar.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: forming a dielectric layer on the first contact pad and the second contact pad, wherein the dielectric layer has a plurality of capacitor holes, wherein projections of the capacitor holes on the substrate are located in the first array region and at least partially overlap with projections of the first contact pad on the substrate; forming a plurality of partial capacitor structures in the capacitor hole; removing a portion of the dielectric layer to expose the second contact pad; A plurality of magnetic storage structures and contact structures are sequentially formed on the second contact pad.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric layer, wherein the capacitor dielectric layer is located between the lower electrode and the upper electrode; the second bit line structure includes a plurality of second bit lines located above the contact structure, the plurality of second bit lines extending along the second direction and spaced apart in the first direction; The upper electrode and the second bit line structure are simultaneously formed on the capacitor dielectric layer and the contact structure.

7. A semiconductor structure manufactured according to the manufacturing method according to any one of claims 1 to 6, characterized in that: include: a substrate comprising a first array region and a second array region; A first storage array consisting of a plurality of first storage structures is provided on the first array area; A second storage array consisting of a plurality of second storage structures is provided on the second array area; The first storage structure includes a first bit line structure, a first transistor structure and a capacitor structure, the first bit line structure is located below the first transistor, and the capacitor structure is provided on the corresponding first transistor structure; The second storage structure includes a source line structure, a second bit line structure, and a second transistor structure, wherein the source line structure is located below the second transistor structure, and the second bit line structure is located above the second transistor structure; The first bit line structure and the source line structure are arranged in the same layer.

8. The semiconductor structure according to claim 7, wherein: The first bit line structure includes a plurality of first bit lines extending along a first direction and spaced apart in a second direction, the first transistor structure includes a plurality of first active pillars disposed on the first bit lines, the first active pillars extending in a direction perpendicular to the substrate surface, projections of the first active pillars on the substrate at least partially overlapping with projections of the first bit lines on the substrate, and the first direction is perpendicular to the second direction; The source line structure includes a plurality of source lines extending in a first direction and spaced apart in a second direction, the second transistor structure includes a plurality of second active pillars disposed on the source lines, the second active pillars extending in a direction perpendicular to the substrate surface, and projections of the second active pillars on the substrate at least partially overlapping with projections of the source lines on the substrate; The first active pillar and the second active pillar are arranged in the same layer.

9. The semiconductor structure according to claim 8, wherein: The first transistor structure includes a plurality of first word lines extending along the second direction and spaced apart in the first direction, wherein the first word lines are arranged around the middle sidewall of the first active pillar; The second transistor structure includes a plurality of second word lines extending along the second direction and spaced apart in the first direction, wherein the second word lines are arranged around the middle sidewall of the second active pillar; The first word line and the second word line are arranged in the same layer.

10. The semiconductor structure according to claim 9, wherein: The first storage structure further includes a first contact pad, and the first contact pad is disposed on the corresponding first active pillar; The second storage structure further includes a second contact pad, and the second contact pad is disposed on the corresponding second active pillar; The first contact pad and the second contact pad are arranged in the same layer.

11. The semiconductor structure according to claim 7, wherein: The capacitor structure includes a lower electrode, an upper electrode and a capacitor dielectric layer. The capacitor dielectric layer is located between the lower electrode and the upper electrode. The upper electrode and the second bit line structure are arranged in the same layer.

12. The semiconductor structure according to claim 10, wherein: The second storage structure includes a contact structure and a magnetic storage structure. The magnetic storage structure is disposed on the corresponding second contact pad. The magnetic storage structure is electrically connected to the second bit line via the contact structure.

13. The semiconductor structure according to claim 12, wherein: The magnetic storage structure includes a reference layer, a magnetic tunneling barrier layer, and a free layer. The reference layer is disposed on the corresponding second contact pad, and the magnetic tunneling barrier layer is located between the reference layer and the free layer.

14. The semiconductor structure according to claim 11, wherein: The second bit line structure includes a plurality of second bit lines extending along the second direction and spaced apart in the first direction.

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