Semiconductor Structure and Method for Preparing the Same

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same, relating to the field of semiconductor technology. The method for manufacturing the semiconductor structure includes providing a substrate, the substrate including a peripheral circuit region and an array region having memory cells, and the peripheral circuit region including a first region and a second region. The present disclosure uses the process for manufacturing a dynamic random access memory to simultaneously manufacture a logic device for controlling the memory cells and a magnetic memory device in the peripheral circuit region, so that the same semiconductor structure has two storage structures at the same time. Compared with the technology of separately manufacturing two storage structures, the manufacturing steps can be simplified and the manufacturing cost can be reduced. In addition, by using the process for manufacturing a dynamic random access memory to manufacture the magnetic memory device, the integration degree of the magnetic memory device can be improved, which is convenient for the semiconductor structure to develop in the direction of integration.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Magnetic Random Access Memory (MRAM) is an integration based on silicon-based complementary metal-oxide-semiconductor and magnetic tunnel junction technology. It is a non-volatile memory that has the high-speed read and write capabilities of Static Random Access Memory (SRAM) and the high integration of Dynamic Random Access Memory (DRAM).

[0003] However, due to the limitations of the manufacturing process, it is difficult to improve the integration of magnetic random access memory when forming it, which is not conducive to the development of semiconductor structures towards the direction of integration. Summary of the Invention

[0004] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can simultaneously manufacture the logic devices of dynamic random access memory and the magnetic storage devices of magnetic random access memory using the same manufacturing process, simplifying the manufacturing steps of the semiconductor structure.

[0005] The first aspect of the embodiments of the present disclosure provides a method for manufacturing a semiconductor structure, which includes:

[0006] Providing a substrate, the substrate includes an adjacent peripheral circuit region and an array region having storage units, and the peripheral circuit region includes an adjacent first region and a second region;

[0007] Forming logic devices in the first region and magnetic storage devices in the second region using the same manufacturing process, the manufacturing process being a process for manufacturing dynamic random access memory, wherein the logic devices are connected to the storage units to control the storage units, and the magnetic storage devices include access transistors and magnetic tunnel junctions connected to the access transistors.

[0008] In some embodiments, the step of forming logic devices in the first region and magnetic storage devices in the second region using the same manufacturing process includes:

[0009] Forming logic transistors in the first region and access transistors in the second region;

[0010] Form a first interconnect structure on a substrate located in the first region and the second region, the first interconnect structure including a first interconnect layer and a second interconnect layer, the first interconnect layer being connected to the logic transistor, and the second interconnect layer being connected to the access transistor;

[0011] Form a magnetic tunnel junction on the second interconnect layer;

[0012] Form a second interconnect structure above the first interconnect layer and the magnetic tunnel junction, the second interconnect structure including a third interconnect layer and a fourth interconnect layer, the third interconnect layer being electrically connected to the first interconnect layer, and the fourth interconnect layer being electrically connected to the magnetic tunnel junction, wherein the logic transistor, the first interconnect layer, and the third interconnect layer constitute the logic device, and the access transistor, the second interconnect layer, the magnetic tunnel junction, and the fourth interconnect layer constitute the magnetic storage device.

[0013] In some embodiments, in the step of providing the substrate, it includes:

[0014] Form a plurality of active regions and isolation structures for separating the active regions in the substrate;

[0015] In the step of forming a logic transistor in the first region of the substrate and an access transistor in the second region, it includes:

[0016] Form a stacked gate oxide layer and a gate on the first region and the second region of the substrate, the gate projecting on the substrate to cover a part of the active regions;

[0017] Form a protective layer wrapping around the sides of the gate and the gate oxide layer, wherein the active region, the gate oxide layer, the gate, and the protective layer located in the first region constitute the logic transistor, and the active region, the gate oxide layer, the gate, and the protective layer located in the second region constitute the access transistor.

[0018] In some embodiments, after the step of forming a logic transistor in the substrate in the first region and an access transistor in the second region, and before the step of forming a first interconnect structure on the substrate located in the first region and the second region, the manufacturing method further includes:

[0019] Form a first dielectric layer covering the logic transistor and the access transistor on the substrate;

[0020] Form a plurality of conductive plugs in the first dielectric layer, the conductive plugs located in the first region being used to connect the first interconnect layer to the logic transistor, and the conductive plugs located in the second region being used to connect the first interconnect layer to the access transistor.

[0021] In some embodiments, the step of forming a plurality of conductive plugs in the first dielectric layer includes:

[0022] Patterning the first dielectric layer to form a plurality of first vias spaced apart from each other in the first dielectric layer, each of the first vias exposing a source region or a drain region of the active region;

[0023] Depositing a conductive material in each of the first vias to form the conductive plugs.

[0024] In some embodiments, the step of forming a first interconnect structure on the substrates located in the first region and the second region includes:

[0025] Forming a first conductive layer on the first dielectric layer;

[0026] Removing a part of the first conductive layer, the remaining first conductive layer forming a first interconnect layer in the first region and the remaining first conductive layer forming a second interconnect layer in the second region, the first interconnect layer and the second interconnect layer being electrically connected to the conductive plugs respectively.

[0027] In some embodiments, in a plane parallel to the substrate, the projections of the first interconnect layer and the second interconnect layer respectively cover the projections of the conductive plugs to which they are electrically connected.

[0028] The step of forming a magnetic tunnel junction on the second interconnect layer includes:

[0029] Forming a magnetic layer on the first interconnect structure;

[0030] Removing a part of the magnetic layer to retain the magnetic layer on one of the second interconnect layers above the second region, the remaining magnetic layer forming the magnetic tunnel junction.

[0031] In some embodiments, after the step of forming a magnetic tunnel junction on the second interconnect layer and before the step of forming a second interconnect structure above the first interconnect layer and the magnetic tunnel junction, the manufacturing method further includes:

[0032] Forming a third dielectric layer on the first interconnect structure and the magnetic tunnel junction;

[0033] Forming first silicon vias and second silicon vias spaced apart from each other in the third dielectric layer, the first silicon vias being located above the first region and being electrically connected to one of the first interconnect layers, and the second silicon vias being located above the second region and being electrically connected to the magnetic tunnel junction.

[0034] In some embodiments, in the step of forming a second interconnect structure above the first interconnect layer and the magnetic tunnel junction, it includes:

[0035] Form a second conductive layer on the third dielectric layer;

[0036] Remove a part of the second conductive layer, and the remaining second conductive layer forms a third interconnect layer in the first region, and the remaining second conductive layer forms a fourth interconnect layer in the second region.

[0037] In some embodiments, the step of forming a stacked gate oxide layer and a gate on the first region and the second region of the substrate includes:

[0038] Form a stacked gate oxide material layer and a gate material layer on the first region and the second region of the substrate;

[0039] Form a conductive material layer on the gate material layer;

[0040] Pattern the conductive material layer, the gate oxide material layer and the gate material layer to form a stacked gate oxide layer and a gate, and a word line formed on the gate.

[0041] A second aspect of the embodiments of the present disclosure provides a semiconductor structure, which is obtained by the preparation method of the semiconductor structure in the above embodiments, and includes:

[0042] A substrate, the substrate includes an adjacent peripheral circuit region and an array region having memory cells, and the peripheral circuit region includes an adjacent first region and a second region;

[0043] Logic devices, the logic devices are disposed in the first region and are connected to the memory cells to control the memory cells;

[0044] Magnetic storage devices, the magnetic storage devices are disposed in the second region, wherein the magnetic storage devices include access transistors and magnetic tunnel junctions connected to the access transistors.

[0045] In some embodiments, the logic devices include logic transistors, a first interconnect layer and a third interconnect layer, and the first interconnect layer and the third interconnect layer are stacked on the logic transistors;

[0046] The first interconnect layer is connected to the logic transistors through conductive plugs located above the first region, and the third interconnect layer is connected to the first interconnect layer through first through-silicon vias.

[0047] In some embodiments, the magnetic storage device further includes a second interconnect layer and a fourth interconnect layer. The second interconnect layer is disposed between the access transistor and the magnetic tunnel junction to electrically connect the access transistor and the magnetic tunnel junction;

[0048] The fourth interconnect layer is disposed on the magnetic tunnel junction and is electrically connected to the magnetic tunnel junction.

[0049] In some embodiments, the second interconnect layer is connected to the access transistor through a conductive plug located on a second region, and the fourth interconnect layer is connected to the magnetic tunnel junction through a second via silicon through hole.

[0050] In the semiconductor structure and its manufacturing method provided by the embodiments of the present disclosure, by using the process for manufacturing a dynamic random access memory to simultaneously manufacture a logic device for controlling a storage cell and a magnetic storage device in a peripheral circuit region, the same semiconductor structure has two storage structures at the same time. Compared with the technology of separately manufacturing two storage structures, the manufacturing steps can be simplified and the manufacturing cost can be reduced; in addition, by using the process for manufacturing a dynamic random access memory to manufacture a magnetic storage device, the integration degree of the magnetic storage device can be improved, which is convenient for the semiconductor structure to develop towards the direction of integration.

[0051] In addition to the technical problems solved by the embodiments of the present disclosure described above, the technical features constituting the technical solutions, and the beneficial effects brought by these technical features of the technical solutions, other technical problems that can be solved by the semiconductor structure and its manufacturing method provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manners. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0053] Figure 1 is the process flow diagram of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure Figure 1 ;

[0054] Figure 2 is the distribution diagram of the array region and the peripheral circuit region in the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure;

[0055] Figure 3 is the structural schematic diagram of the substrate in the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure;

[0056] Figure 4 Process flow of the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;

[0057] Figure 5 Schematic structural diagram of forming a logic transistor and an access transistor in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0058] Figure 6 Schematic structural diagram of forming a first dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0059] Figure 7 Schematic structural diagram of forming a first via hole in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0060] Figure 8 Schematic structural diagram of forming a conductive plug in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0061] Figure 9 Schematic structural diagram of forming a first conductive layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0062] Figure 10 Schematic structural diagram of forming a first interconnect structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0063] Figure 11 Schematic structural diagram of forming a second dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0064] Figure 12 Schematic structural diagram of forming a magnetic layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0065] Figure 13 Schematic structural diagram of forming a magnetic tunnel junction in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0066] Figure 14 Schematic structural diagram of forming a third dielectric layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0067] Figure 15 Schematic structural diagram of forming a first through-silicon via and a second through-silicon via in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0068] Figure 16 Schematic structural diagram of forming a second conductive layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0069] Figure 17 Schematic diagram of forming a second interconnect structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0070] Reference numerals:

[0071] 10: Substrate; 11: Peripheral circuit region; 111: First region; 112: Second region; 12: Array region; 13: Active region; 14: Isolation structure;

[0072] 20: Logic transistor; 21: Gate oxide layer; 22: Gate; 23: Protection layer;

[0073] 30: Access transistor;

[0074] 40: First dielectric layer; 41: First via; 42: Conductive plug;

[0075] 50: First interconnect structure; 51: First interconnect layer; 52: Second interconnect layer; 53: First conductive layer;

[0076] 60: Second dielectric layer;

[0077] 70: Magnetic tunnel junction; 71: Magnetic layer;

[0078] 80: Third dielectric layer; 81: First through-silicon via; 82: Second through-silicon via;

[0079] 90: Second interconnect structure; 91: Third interconnect layer; 92: Fourth interconnect layer; 93: Second conductive layer;

[0080] 100: Word line;

[0081] 110: Logic device; 120: Magnetic storage device. Detailed implementation manners

[0082] In the related art, due to the limitation of the manufacturing process, it is difficult to improve the integration degree of a magnetic random access memory (MRAM), which is not conducive to the development of semiconductor structures towards integration. Based on the above technical problems, in the disclosed embodiment, a logic device for controlling a storage unit and a magnetic storage device are simultaneously fabricated in the peripheral circuit region by using the process for manufacturing a dynamic random access memory, so that the same semiconductor structure has two storage structures at the same time. Compared with the technology of separately fabricating two storage structures, the manufacturing steps can be simplified and the manufacturing cost can be reduced. In addition, by using the process for manufacturing a dynamic random access memory to fabricate the magnetic storage device, the integration degree of the magnetic storage device can be improved, which is convenient for the development of semiconductor structures towards integration.

[0083] To make the above objects, features, and advantages of the embodiments of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0084] As Figure 1 shown, the method for preparing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:

[0085] Step S100: Provide a substrate, the substrate includes an adjacent peripheral circuit region and an array region having memory cells, and the peripheral circuit region includes an adjacent first region and a second region.

[0086] Exemplarily, as Figure 2 shown, the substrate 10 includes an adjacent peripheral circuit region 11 and an array region 12. For example, the peripheral circuit region 11 is usually disposed around the array region 12. The array region 12 is usually used to dispose memory cells to implement the storage function of the memory. Among them, the memory cells can be devices of a dynamic random access memory, that is, one memory cell includes a read transistor and a capacitor.

[0087] As Figure 3 shown, a plurality of active regions 13 and isolation structures 14 for separating the respective active regions 13 are formed in the substrate 10. That is to say, the active regions 13 exist both in the peripheral circuit region 11 and in the array region 12.

[0088] Specifically, the preparation process can be: first pattern the substrate 10 to form isolation trenches in the substrate 10, and then deposit an insulating material in the isolation trenches by a deposition process to form the isolation structure 14, but not limited thereto.

[0089] Among them, the substrate 10 can be made of a semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds. The material of the isolation structure 14 is an insulating material, and the insulating material includes any one or any combination of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

[0090] The peripheral circuit region 11 includes an adjacent first region 111 and a second region 112. Among them, the adjacent setting can be understood as in a certain direction, the first region 111 and the second region 112 are arranged side by side, or it can be understood that the first region 111 surrounds the second region 112, or alternatively, the second region 112 surrounds the first region 111.

[0091] Step S200: A logic device is formed in a first region and a magnetic storage device is formed in a second region using the same fabrication process, where the fabrication process is a process for fabricating a dynamic random access memory. The logic device is connected to a storage cell to control the storage cell. The magnetic storage device includes an access transistor and a magnetic tunnel junction connected to the access transistor.

[0092] In this embodiment, by using the process for fabricating a dynamic random access memory to simultaneously fabricate a logic device for controlling a storage cell and a magnetic storage device in the peripheral circuit region, the same semiconductor structure has two storage structures at the same time. Compared with the technology of separately fabricating two storage structures, the fabrication steps can be simplified and the fabrication cost can be reduced. In addition, by using the process for fabricating a dynamic random access memory to fabricate the magnetic storage device, the integration degree of the magnetic storage device can be improved, which is convenient for the semiconductor structure to develop in the direction of integration.

[0093] In some embodiments, as Figure 4 shown, the steps of forming a logic device in a first region and a magnetic storage device in a second region using the same fabrication process include the following steps:

[0094] Step S210: A logic transistor is formed in the first region and an access transistor is formed in the second region.

[0095] Among them, the logic transistor 20 and the access transistor 30 are formed in the same process step, and their structures are as Figure 5 shown.

[0096] Exemplarily, an ion doping process can be used to form a channel region and a source region and a drain region respectively disposed on both sides of the channel region in the active region 13. Among them, the types of doping ions in the source region and the drain region are the same, and the type of doping ions in the channel region is different from the type of doping ions in the source region.

[0097] After that, a gate oxide layer 21 and a gate 22 are formed in a stacked manner on the first region 111 and the second region 112 of the substrate 10. The projection of the gate 22 on the substrate 10 covers a part of the active region 13, that is, the projection of the gate 22 on the substrate 10 covers at least the channel region to facilitate the gate 22 to apply a voltage to the channel region.

[0098] In this step, a gate oxide material layer and a gate material layer can be formed in a stacked manner on the substrate 10 located in the first region 111 and the second region 112 by using a deposition process. The gate oxide material layer is disposed on the substrate 10. Among them, the material of the gate oxide material layer can include silicon oxide or other materials with a high dielectric constant, such as aluminum oxide; the material of the gate material layer includes polysilicon.

[0099] After that, a conductive material layer is formed on the gate material layer, wherein the material of the conductive material layer includes one or any combination of copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), titanium nitride (TiN), cobalt silicide (CoSi), and titanium aluminide (TiAl).

[0100] Finally, a mask layer is formed on the conductive material layer, and the mask layer is patterned. Using the patterned mask layer as a mask, the conductive material layer, the gate oxide material layer, and the gate material layer are etched in sequence to form a stacked gate oxide layer 21 and a gate 22, and a word line 100 formed on the gate 22. The gate oxide layer 21 is located on the upper surface of the substrate 10.

[0101] After the gate oxide layer 21, the gate 22, and the word line 100 are formed, a protective layer 23 is formed on the sides of the gate 22, the gate oxide layer 21, and the word line 100. For example, an initial protective layer can be formed on the active region 13 through a deposition process. The initial protective layer covers the sides of the gate oxide layer 21, the sides of the gate 22, the sides, and the top surface of the word line 100. Then, the initial protective layer located on the top surface of the word line 100 is removed using an etching gas or an etching solution, and the remaining initial protective layer constitutes the protective layer 23. The setting of the protective layer 23 can achieve the isolation between the gate 22 and the word line 100 and other devices. Among them, the material of the protective layer 23 can be an insulating material composed of a single layer or a multi-layer structure of silicon oxide, silicon nitride, or silicon oxynitride.

[0102] In this embodiment, the active region 13, the gate oxide layer 21, the gate 22, and the protective layer 23 located in the first region 111 constitute a logic transistor 20, and the active region 13, the gate oxide layer 21, the gate 22, and the protective layer 23 located in the second region 112 constitute a memory transistor 30. The logic transistor 20 and the memory transistor 30 are fabricated in the same process step, which can simplify the fabrication process.

[0103] Step S220: Form a first dielectric layer on the substrate to cover the logic transistor and the memory transistor.

[0104] As Figure 6 shown, a first dielectric layer 40 can be formed on the substrate 10 through a deposition process. The first dielectric layer 40 covers the logic transistor 20 and the memory transistor 30. Among them, the material of the first dielectric layer 40 can include insulating materials such as silicon oxide or silicon nitride.

[0105] Step S230: Form a plurality of conductive plugs in the first dielectric layer. The conductive plugs located in the first region are used to connect the first interconnect layer to the logic transistor, and the conductive plugs located in the second region are used to connect the first interconnect layer to the memory transistor.

[0106] Exemplarily, as Figure 7 shown, the first dielectric layer 40 is patterned to form a plurality of first vias 41 spaced apart within the first dielectric layer 40, and each first via 41 exposes the source region or the drain region of the active region; for example, the number of the first vias 41 is four. From left to right, the first first via 41 is used to expose the source region of the active region 13 located in the first region 111, the second first via 41 is used to expose the drain region of the active region 13 located in the first region 111, and both the first first via 41 and the second first via 41 are located above one active region 13. The third first via 41 is used to expose the source region of the active region 13 located in the second region 112, and the fourth first via 41 is used to expose the drain region of the active region 13 located in the second region 112, and both the third first via 41 and the fourth first via 41 are located above one active region 13.

[0107] After that, as Figure 8 shown, a conductive material is deposited in each first via 41 to form a conductive plug 42, and the conductive plug 42 is used to realize the connection between the subsequently formed first interconnect layer and the second interconnect layer and the active region 13 respectively.

[0108] Step S240: A first interconnect structure is formed on the substrates located in the first region and the second region. The first interconnect structure includes a first interconnect layer and a second interconnect layer. The first interconnect layer is connected to the logic transistor, and the second interconnect layer is connected to the access transistor.

[0109] Exemplarily, as Figure 9 shown, a first conductive layer 53 is formed on the first dielectric layer 40 by a deposition process. Among them, the material of the first conductive layer 53 may include one of tungsten metal, aluminum metal, copper metal or titanium metal.

[0110] After that, as Figure 10 shown, the first conductive layer 53 is patterned, and a part of the first conductive layer 53 is removed, and the first conductive layer 53 located above each conductive plug 42 is retained. The retained first conductive layer 53 forms the first interconnect layer 51 within the first region 111, and the retained first conductive layer 53 forms the second interconnect layer 52 within the second region 112. The first interconnect layer 51 and the second interconnect layer 52 form the first interconnect structure 50, wherein the first interconnect layer 51 and the second interconnect layer 52 are electrically connected to the conductive plug 42 respectively.

[0111] It should be noted that in this embodiment, the number of the first interconnection layers 51 is two. Among them, one first interconnection layer 51 is electrically connected to the source region of the active region 13 located in the first region 111 through a conductive plug 42, and the other first interconnection layer 51 is electrically connected to the drain region of the active region 13 located in the second region 112 through a conductive plug 42. Correspondingly, the number of the second interconnection layers 52 is two, and their connection manner with the active region 13 located in the second region 112 is similar to the connection manner of the two first interconnection layers 51 with the active region 13 located in the first region 111, and this embodiment will not elaborate further here.

[0112] In this embodiment, on the plane parallel to the substrate 10, the projections of the first interconnection layer 51 and the second interconnection layer 52 respectively cover the projections of the conductive plugs 42 to which they are electrically connected.

[0113] Taking the first first interconnection layer 51 and the conductive plug 42 electrically connected thereto as an example for illustration, the projected area of the first interconnection layer 51 on the substrate 10 is larger than the projected area of the conductive plug 42 on the substrate 10. Such a setting can increase the contact area between the first interconnection layer 51 and the conductive plug 42, reduce the contact resistance between the above two, and improve the performance of the semiconductor structure.

[0114] As Figure 11 shown, in order to achieve insulation between the first interconnection layer 51 and the second interconnection layer 52, and between adjacent first interconnection layers 51 or adjacent second interconnection layers 52, a second dielectric layer 60 is provided between the first interconnection layer 51 and the second interconnection layer 52, between adjacent first interconnection layers 51, and between adjacent second interconnection layers 52.

[0115] Step S250: Form a magnetic tunnel junction on the second interconnection layer.

[0116] Exemplarily, as Figure 12 and Figure 13 shown, a magnetic layer 71 is formed on the first interconnection structure 50 and the second dielectric layer 60 by a deposition process, and then the magnetic layer 71 is patterned to remove part of the magnetic layer 71, and the magnetic layer 71 on the second interconnection layer 52 located on the second region 112 is retained. The remaining part of the magnetic layer 71 constitutes the magnetic tunnel junction 70. Among them, the magnetic tunnel junction 70 includes a fixed layer, a tunneling layer, and a free layer arranged in a stacked manner. When the semiconductor structure operates normally, the magnetization direction of the free layer can be changed, while the magnetization direction of the fixed layer remains unchanged. When the magnetization direction of the free layer changes relative to the magnetization direction of the fixed layer, the resistance value of the magnetic storage device changes accordingly, corresponding to different stored information.

[0117] It should be noted that when the magnetic tunnel junction 70 is connected to the drain region of the access transistor 30, correspondingly, the magnetic tunnel junction 70 is formed on the conductive plug 42 connected to the drain region. When the magnetic tunnel junction 70 is connected to the source region of the access transistor 30, correspondingly, the magnetic tunnel junction 70 is formed on the conductive plug 42 connected to the source region.

[0118] In this embodiment, by using the manufacturing process for forming a dynamic random access memory, the magnetic tunnel junction 70 is formed on the second interconnect layer in the first interconnect structure. Compared with the related art where the magnetic tunnel junction 70 is formed on the fourth interconnect structure, the number of magnetic storage devices per unit area can be increased, thereby improving the integration degree of the magnetic storage devices.

[0119] Step S260: Form a second interconnect structure above the first interconnect layer and the magnetic tunnel junction. The second interconnect structure includes a third interconnect layer and a fourth interconnect layer. The third interconnect layer is electrically connected to the first interconnect layer, and the fourth interconnect layer is electrically connected to the magnetic tunnel junction. Among them, the logic transistor, the first interconnect layer, and the third interconnect layer constitute a logic device, and the access transistor, the second interconnect layer, the magnetic tunnel junction, and the fourth interconnect layer constitute a magnetic storage device.

[0120] Exemplarily, as Figure 14 shown, a third dielectric layer 80 is formed on the first interconnect structure 50 and the magnetic tunnel junction 70 by using a deposition process. The material of the third dielectric layer 80 may include silicon oxide and silicon nitride.

[0121] As Figure 15 shown, first silicon vias 81 and second silicon vias 82 are formed in the third dielectric layer 80 at intervals. The first silicon vias 81 are located above the first region 111 and are electrically connected to the first interconnect layer 51, and the second silicon vias 82 are located above the second region 112 and are electrically connected to the magnetic tunnel junction 70.

[0122] Taking Figure 15 the orientation shown as an example, the number of the first silicon vias 81 is two, and the two first silicon vias 81 are arranged in one-to-one correspondence with the two first interconnect layers 51.

[0123] After the first silicon vias 81 and the second silicon vias 82 are formed, as Figure 16 shown, a second conductive layer 93 is formed on the third dielectric layer 80.

[0124] As Figure 17As shown, part of the second conductive layer 93 is removed, and the retained second conductive layer 93 forms a third interconnect layer 91 in the first region 111, and the retained second conductive layer 93 forms a fourth interconnect layer 92 in the second region, and the third interconnect layer 91 and the fourth interconnect layer 92 constitute a second interconnect structure 90, wherein the third interconnect layer 91 is electrically connected to the first through silicon via 81, and the fourth interconnect layer 92 is electrically connected to the second through silicon via 82, and the fourth interconnect layer 92 can be used as a bit line structure of the magnetic memory device 120.

[0125] It should be noted that the number of the third interconnection layers 91 in this embodiment is two, corresponding to the number of the first through silicon vias 81. Figure 17 Taking the orientation shown as an example, from left to right, the first third interconnect layer 91 is connected to the first first interconnect layer 51 through the first first silicon via 81, and the second third interconnect layer 91 is also connected to the second first interconnect layer 51 through the second first silicon via 81 to avoid crosstalk in signal transmission.

[0126] The third interconnection layer 91 and the fourth interconnection layer 92 may be formed in other exemplary embodiments. For example, after the first through silicon via 81 and the second through silicon via 82 are formed, an insulating layer is formed on the third dielectric layer 80, and the insulating layer is patterned to form a groove, wherein the groove exposes the top of the first through silicon via 81 and the top of the second through silicon via 82, and a conductive material is deposited in the groove, wherein the conductive material electrically connected to the first through silicon via 81 constitutes the third interconnection layer 91, and the conductive material electrically connected to the second through silicon via 82 constitutes the fourth interconnection layer 92. The insulating layer is located between the third interconnection layer 91 and the fourth interconnection layer 92, and is used to isolate the third interconnection layer 91 from the fourth interconnection layer 92, and plays an insulating role.

[0127] In this embodiment, the logic transistor 20 , the first interconnect layer 51 and the third interconnect layer 91 constitute a logic device 110 , and the access transistor 30 , the second interconnect layer 52 , the magnetic tunnel junction 70 and the fourth interconnect layer 92 constitute a magnetic memory device 120 .

[0128] This embodiment utilizes the process of preparing dynamic random access memory to simultaneously prepare logic devices and magnetic storage devices for controlling storage units in the peripheral circuit area, so that the same semiconductor structure has two storage structures at the same time. Compared with the technology of preparing two storage structures separately, the manufacturing steps can be simplified and the manufacturing cost can be reduced. In addition, by preparing magnetic storage devices through the process of preparing dynamic random access memory, the integration of magnetic storage devices can be improved, which facilitates the development of semiconductor structures towards integration.

[0129] The embodiments of the present disclosure also provide a semiconductor structure, which is manufactured by the method for manufacturing the semiconductor structure in the above embodiments.

[0130] As shown Figure 17 in FIG. Figure 17 , the semiconductor structure includes a substrate 10, a logic device 110, and a magnetic storage device 120. The substrate 10 includes an adjacent peripheral circuit region 11 and an array region 12 having memory cells. The peripheral circuit region 11 includes an adjacent first region 111 and a second region 112. The area of the first region 111 may be the same as or different from the area of the second region 112.

[0131] The logic device 110 is disposed in the first region 111 and is connected to the memory cells disposed in the array region 12 to control the memory cells.

[0132] The magnetic storage device 120 is disposed in the second region 112. The magnetic storage device includes an access transistor 30 and a magnetic tunnel junction 70 connected to the access transistor 30.

[0133] In this embodiment, the semiconductor structure has both the memory cells of a dynamic random access memory and the magnetic tunnel junctions of a magnetic random access memory, enabling the same semiconductor structure to have two different forms of storage devices, which can improve the diversity of the semiconductor structure.

[0134] In some embodiments, the logic device 110 includes logic transistors 20, a first interconnect layer 51, and a third interconnect layer 91. The first interconnect layer 51 and the third interconnect layer 91 are stacked on the logic transistors 20. The first interconnect layer 51 is connected to the logic transistors 20 through conductive plugs 42 located above the first region 111. For example, the first first interconnect layer 51 is connected to the source region of the logic transistor 20 through the first conductive plug 42 located above the first region 111, and the second first interconnect layer 51 is connected to the drain region of the logic transistor 20 through the second conductive plug 42 located above the first region 111.

[0135] The third interconnect layer 91 is connected to the first interconnect layer 51 through first vias 81 to enable the transfer of electrical signals between the first interconnect layer 51 and the third interconnect layer 91. The material of the first vias 81 may include copper.

[0136] In some embodiments, the magnetic storage device 120 further includes a second interconnect layer 52 and a fourth interconnect layer 92. The second interconnect layer 52 is disposed between the access transistor 30 and the magnetic tunnel junction 70 to electrically connect the access transistor 30 and the magnetic tunnel junction 70. That is, the upper surface of the second interconnect layer 52 is connected to the magnetic tunnel junction 70, and the lower surface of the second interconnect layer 52 is electrically connected to the access transistor 30.

[0137] The lower surface of the second interconnection layer 52 can be directly or indirectly connected to the access transistor 30. For example, the second interconnection layer 52 and the access transistor are connected through a conductive plug 42 located on the second region 112.

[0138] The fourth interconnection layer 92 is disposed on the magnetic tunnel junction 70 and electrically connected to the magnetic tunnel junction 70. For example, the fourth interconnection layer 92 is connected to the magnetic tunnel junction 70 through a second via 82. In this embodiment, the second via 82 and the conductive plug located on the second region 112 are used to achieve electrical connection between the components in the magnetic storage device.

[0139] The embodiments or implementation manners in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0140] In the description of this specification, the description with reference to the terms "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure.

[0141] In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including an adjacent peripheral circuit region and an array region having memory cells, the peripheral circuit region including an adjacent first region and a second region; Forming a logic device in the first region and a magnetic memory device in the second region using the same manufacturing process, the manufacturing process being a process for manufacturing a dynamic random access memory; Specifically including: forming a logic transistor in the first region and an access transistor in the second region; Forming a first interconnect structure on the substrate located in the first region and the second region, the first interconnect structure including a first interconnect layer and a second interconnect layer, the first interconnect layer being connected to the logic transistor, and the second interconnect layer being connected to the access transistor; Forming a magnetic tunnel junction on the second interconnect layer; Forming a second interconnect structure above the first interconnect layer and the magnetic tunnel junction, the second interconnect structure including a third interconnect layer and a fourth interconnect layer, the third interconnect layer being electrically connected to the first interconnect layer, and the fourth interconnect layer being electrically connected to the magnetic tunnel junction; wherein, the logic transistor, the first interconnect layer, and the third interconnect layer constitute the logic device, and the logic device is connected to the memory cell to control the memory cell; the access transistor, the second interconnect layer, the magnetic tunnel junction, and the fourth interconnect layer constitute the magnetic memory device.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein In the step of providing the substrate, it includes: Forming a plurality of active regions and isolation structures for separating the active regions in the substrate; In the step of forming a logic transistor in the first region and an access transistor in the second region, it includes: Forming a stacked gate oxide layer and a gate on the first region and the second region of the substrate, the gate projecting on the substrate to cover a part of the active regions; Forming a protective layer covering the sides of the gate and the gate oxide layer, wherein the active region, the gate oxide layer, the gate, and the protective layer located in the first region constitute the logic transistor, and the active region, the gate oxide layer, the gate, and the protective layer located in the second region constitute the access transistor.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein, After the step of forming a logic transistor in the substrate in the first region and an access transistor in the second region, and before the step of forming a first interconnect structure on the substrate located in the first region and the second region, the manufacturing method further includes: Forming a first dielectric layer covering the logic transistor and the access transistor on the substrate; Forming a plurality of conductive plugs in the first dielectric layer, the conductive plugs located in the first region being used to connect the first interconnect layer and the logic transistor, and the conductive plugs located in the second region being used to connect the first interconnect layer and the access transistor.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein, In the step of forming a plurality of conductive plugs in the first dielectric layer, it includes: Patterning the first dielectric layer to form a plurality of first through holes arranged at intervals in the first dielectric layer, each first through hole exposing the source region or the drain region of the active region; Deposit a conductive material in each of the first vias to form the conductive plugs.

5. The method for preparing a semiconductor structure according to claim 3 or 4, characterized in that, The step of forming a first interconnect structure on a substrate in the first region and the second region includes: Form a first conductive layer on the first dielectric layer; Remove a portion of the first conductive layer, and the remaining first conductive layer forms a first interconnect layer in the first region, and the remaining first conductive layer forms a second interconnect layer in the second region. The first interconnect layer and the second interconnect layer are electrically connected to the conductive plugs respectively.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein, In a plane parallel to the substrate, the projections of the first interconnect layer and the second interconnect layer respectively cover the projections of the conductive plugs to which they are electrically connected.

7. The method for manufacturing a semiconductor structure according to claim 5, wherein, The step of forming a magnetic tunnel junction on the second interconnect layer includes: Form a magnetic layer on the first interconnect structure; Remove a portion of the magnetic layer to retain the magnetic layer on one of the second interconnect layers above the second region. The remaining magnetic layer forms the magnetic tunnel junction.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein After the step of forming a magnetic tunnel junction on the second interconnect layer and before the step of forming a second interconnect structure above the first interconnect layer and the magnetic tunnel junction, the manufacturing method further includes: Form a third dielectric layer on the first interconnect structure and the magnetic tunnel junction; Form a first silicon via and a second silicon via spaced apart from each other in the third dielectric layer. The first silicon via is located above the first region and is electrically connected to one of the first interconnect layers, and the second silicon via is located above the second region and is electrically connected to the magnetic tunnel junction.

9. The method for preparing a semiconductor structure according to claim 8, wherein The step of forming a second interconnect structure above the first interconnect layer and the magnetic tunnel junction includes: Form a second conductive layer on the third dielectric layer; Remove a portion of the second conductive layer, and the remaining second conductive layer forms a third interconnect layer in the first region, and the remaining second conductive layer forms a fourth interconnect layer in the second region.

10. The manufacturing method of the semiconductor structure according to any one of claims 2-4, characterized in that, The step of forming a stacked gate oxide layer and a gate on the first region and the second region of the substrate includes: Form a stacked gate oxide material layer and a gate material layer on the first region and the second region of the substrate; Form a conductive material layer on the gate material layer; Pattern the conductive material layer, the gate oxide material layer, and the gate material layer to form a stacked gate oxide layer and a gate, and a word line formed on the gate.

11. A semiconductor structure, characterized in that, The semiconductor structure is obtained by the manufacturing method of the semiconductor structure according to any one of claims 1-10, including: A substrate including an adjacent peripheral circuit region and an array region having memory cells, the peripheral circuit region including adjacent first and second regions; Logic device, the logic device is disposed within the first region and connected to the memory cell to control the memory cell; the logic device includes logic transistors, a first interconnect layer, and a third interconnect layer, the first interconnect layer and the third interconnect layer are stacked on the logic transistors; the first interconnect layer is connected to the logic transistors through conductive plugs located above the first region, and the third interconnect layer is connected to the first interconnect layer through a first through-silicon via; Magnetic memory device, the magnetic memory device is disposed within the second region, wherein the magnetic memory device includes access transistors and magnetic tunnel junctions connected to the access transistors; the magnetic memory device further includes a second interconnect layer and a fourth interconnect layer, the second interconnect layer is disposed between the access transistors and the magnetic tunnel junctions to electrically connect the access transistors and the magnetic tunnel junctions; the fourth interconnect layer is disposed on the magnetic tunnel junctions and electrically connected to the magnetic tunnel junctions.

12. The semiconductor structure according to claim 11, wherein The second interconnect layer is connected to the access transistors through conductive plugs located above the second region, and the fourth interconnect layer is connected to the magnetic tunnel junctions through a second through-silicon via.

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