Capacitor and method of manufacturing the same, and semiconductor device

Abstract

The present disclosure provides a capacitor and a method for manufacturing the same, and a semiconductor device. The capacitor includes a plurality of lower electrodes, an upper electrode structure, a dielectric layer, and a gap filling layer. The plurality of upper electrode structures are formed on one side of the plurality of lower electrodes. The dielectric layer contacts the plurality of lower electrodes on one side and contacts the upper electrode structure on the other side. The gap filling layer fills the remaining gaps between the plurality of lower electrodes. The capacitor provided by the exemplary embodiments of the present disclosure has a size that is not limited by the manufacturing process, and the capacitance density per unit volume is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a capacitor and a method for manufacturing the same, and a semiconductor device. BACKGROUND

[0002] With the continuous development of semiconductor memory, the miniaturization of its size has become the main research direction. Similarly, the size of the capacitor in the semiconductor memory also needs to be reduced to meet the demand. At present, the capacitor structure is generally divided into cylindrical and pillar two kinds, but no matter which structure, due to the limitation of process technology, there is a limit to miniaturization. If the miniaturization of the capacitor structure exceeds the corresponding limit, while ensuring a thick high dielectric layer to avoid large leakage, the upper plate material may not be filled in when filling the upper plate material, resulting in a significant reduction in the effective area of the capacitor. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] The present disclosure provides a capacitor and a method for manufacturing the same, and a semiconductor device.

[0005] A first aspect of the present disclosure provides a capacitor, comprising: a plurality of lower electrodes; an upper electrode structure formed on one side of the plurality of lower electrodes; a dielectric layer, one side of the dielectric layer contacting the plurality of lower electrodes, and the other side contacting the upper electrode structure; a gap filling layer filling the remaining gaps between the plurality of lower electrodes.

[0006] According to some embodiments of the present disclosure, the upper electrode structure comprises: a plurality of first upper electrodes, the plurality of first upper electrodes contacting the dielectric layer, and the plurality of first upper electrodes being further filled with the gap filling layer.

[0007] According to some embodiments of the present disclosure, the plurality of first upper electrodes and the plurality of lower electrodes are arranged on both sides of the dielectric layer.

[0008] According to some embodiments of the present disclosure, the lower electrode comprises a first plane and a first curved surface, the first plane contacting the dielectric layer, and the first curved surface contacting the gap filling layer.

[0009] According to some embodiments of the present disclosure, the upper electrode structure further comprises: a second upper electrode, the second upper electrode contacting the plurality of first upper electrodes to connect the plurality of first upper electrodes together.

[0010] According to some embodiments of the present disclosure, the dielectric layer comprises a metal oxide material with a dielectric constant of between 6 and 20.

[0011] According to some embodiments of the disclosure, the gap filling layer comprises an oxygen-containing insulating material having a density greater than that of the dielectric layer.

[0012] According to some embodiments of the disclosure, the plurality of lower electrodes are arranged in an array.

[0013] A second aspect of the disclosure provides a method for manufacturing a capacitor, the method comprising: providing a filling layer; forming a plurality of openings on the filling layer; forming a plurality of lower electrodes in the plurality of openings, respectively; forming a dielectric layer on a remaining portion of the filling layer and on the plurality of lower electrodes, one side of the dielectric layer contacting the plurality of lower electrodes; forming an upper electrode structure on the dielectric layer, another side of the dielectric layer contacting the upper electrode structure; and forming a gap filling layer from a remaining portion of the filling layer, the gap filling layer filling a remaining gap between the plurality of lower electrodes.

[0014] According to some embodiments of the disclosure, the process of forming an upper electrode structure on the dielectric layer comprises:

[0015] forming a plurality of first upper electrodes on another side of the dielectric layer, the plurality of first upper electrodes having the gap filling layer therebetween.

[0016] According to some embodiments of the disclosure, the plurality of first upper electrodes and the plurality of lower electrodes are formed on both sides of the dielectric layer simultaneously, such that both are disposed on both sides of the dielectric layer.

[0017] According to some embodiments of the disclosure, the process of forming the plurality of first upper electrodes and the plurality of lower electrodes simultaneously comprises:

[0018] forming a plurality of electrode pillars in the plurality of openings, respectively; patterning the remaining portion of the filling layer and the plurality of electrode pillars to form isolation trenches in the remaining portion of the filling layer and the plurality of electrode pillars, the isolation trenches separating the plurality of electrode pillars into the plurality of first upper electrodes and the plurality of lower electrodes, respectively; and forming the dielectric layer in the isolation trenches, one side of the dielectric layer contacting the plurality of lower electrodes and another side of the dielectric layer contacting the plurality of first upper electrodes.

[0019] According to some embodiments of the disclosure, the process of forming an upper electrode structure on the dielectric layer further comprises:

[0020] forming a second upper electrode on the plurality of first upper electrodes, the second upper electrode connecting the plurality of first upper electrodes together.

[0021] According to some embodiments of the present disclosure, the filling layer comprises an oxygen-containing insulating layer, the process of providing the filling layer comprises: forming an oxide layer; and heat treating the oxide layer in a preset temperature range to form the oxygen-containing insulating layer, and the density of the oxygen-containing insulating layer is greater than the density of the dielectric layer.

[0022] A third aspect of the present disclosure provides a semiconductor device, comprising: a substrate; a plurality of contact pads formed on the substrate; and the capacitor of any one of the first aspect, wherein the plurality of lower electrodes of the capacitor are respectively located on the plurality of contact pads.

[0023] The capacitor, the preparation method of the capacitor, and the semiconductor device provided by the embodiments of the present disclosure can improve the capacitance density in a unit volume without being limited by the process technology.

[0024] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a method flow chart of a method for manufacturing a semiconductor structure according to an example embodiment.

[0026] Figure 2 is a structure schematic diagram of a filling layer according to an example embodiment.

[0027] Figure 3 is a cross-sectional schematic diagram of a filling layer after a plurality of openings are formed in the filling layer according to an example embodiment.

[0028] Figure 4 is a structure schematic diagram of a plurality of lower electrodes respectively formed in a plurality of openings according to an example embodiment.

[0029] Figure 5 is a cross-sectional structure schematic diagram of a plurality of lower electrodes respectively formed in a plurality of openings according to an example embodiment.

[0030] Figure 6 is a structure schematic diagram of a dielectric layer formed on a plurality of lower electrodes according to an example embodiment.

[0031] Figure 7 is a structure schematic diagram of a preparation method of a capacitor, after an upper electrode structure is formed on a dielectric layer according to an example embodiment.

[0032] Figure 8 is a structure schematic diagram of a preparation method of a capacitor, after an upper electrode structure is formed on a dielectric layer according to an example embodiment.

[0033] Figure 9FIG. 6 is a schematic diagram illustrating a structure after forming an upper electrode structure on a dielectric layer in a method of fabricating a capacitor according to an example embodiment.

[0034] Figure 10 FIG. 6 is a schematic diagram illustrating a structure after forming an upper electrode structure on a dielectric layer in a method of fabricating a capacitor according to an example embodiment.

[0035] Figure 11 FIG. 1 is a flowchart of a method of fabricating a semiconductor structure according to an example embodiment.

[0036] Figure 12 FIG. 7 is a schematic diagram illustrating a structure after forming a plurality of electrode pillars in a plurality of openings, respectively, according to an example embodiment.

[0037] Figure 13 FIG. 8 is a schematic diagram illustrating a cross-sectional structure after forming a plurality of electrode pillars in a plurality of openings, respectively, according to an example embodiment.

[0038] Figure 14 FIG. 9 is a schematic diagram illustrating a structure after forming a plurality of isolation trenches in a method of fabricating a capacitor according to an example embodiment.

[0039] Figure 15 FIG. 10 is a schematic diagram illustrating a planar structure after forming a plurality of isolation trenches in a method of fabricating a capacitor according to an example embodiment.

[0040] Figure 16 FIG. 11 is a schematic diagram illustrating a structure after forming a dielectric layer in an isolation trench in a method of fabricating a capacitor according to an example embodiment.

[0041] Figure 17 FIG. 12 is a schematic diagram illustrating a cross-sectional structure after forming a dielectric layer in an isolation trench in a method of fabricating a capacitor according to an example embodiment.

[0042] Figure 18 FIG. 13 is a schematic diagram illustrating a cross-sectional structure after forming a barrier layer in a method of fabricating a capacitor according to an example embodiment.

[0043] Figure 19 FIG. 14 is a schematic diagram illustrating a cross-sectional structure after forming a second upper electrode in a method of fabricating a capacitor according to an example embodiment.

[0044] Figure 20 FIG. 15 is a flowchart of a method of forming an upper electrode structure on a dielectric layer according to an example embodiment.

[0045] Figure 21 FIG. 16 is a flowchart of a method of filling a layer according to an example embodiment.

[0046] Figure 22is a method flow chart of a semiconductor device manufacturing method according to an exemplary embodiment.

[0047] Figure 23 is a structural schematic diagram of a semiconductor device according to an exemplary embodiment.

[0048] Figure 24 is a structural schematic diagram of a semiconductor device according to an exemplary embodiment.

[0049] Figure 25 is a structural schematic diagram of a semiconductor device according to an exemplary embodiment.

[0050] Figure 26 is a structural schematic diagram of a semiconductor device according to an exemplary embodiment.

[0051] Figure 27 is a structural schematic diagram of a semiconductor device according to an exemplary embodiment.

[0052] Reference signs:

[0053] 1, capacitor; 10, filling layer; 101, remaining part of the filling layer; 102, gap filling layer; 20, opening; 201, opening group; 30, lower electrode; 301, first arc surface; 302, first plane; 40, dielectric layer; 401, one side of the dielectric layer; 402, the other side of the dielectric layer; 50, upper electrode structure; 501, first upper electrode; 5011, second plane; 5012, second arc surface; 502, second upper electrode; 60, electrode column; 70, isolation trench; 701, first trench; 702, second trench; 80, shielding layer; 1000, semiconductor device, 100, substrate; 90, contact pad. DETAILED DESCRIPTION

[0054] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any manner without conflict.

[0055] This disclosure provides an exemplary embodiment of a capacitor fabrication method and a corresponding capacitor, in which an upper electrode structure is formed on one side of multiple lower electrodes. For example, multiple lower electrodes and upper electrode structures are disposed on both sides of a dielectric layer, provided that sufficient dielectric layer thickness is maintained between the multiple lower electrodes and upper electrode structures. This ensures a sufficiently thick dielectric layer to avoid significant leakage current while also preventing situations where the upper electrode material cannot be filled, thus avoiding a significant reduction in the effective area of ​​the capacitor. This greatly improves the miniaturization limit of the capacitor structure, allowing the capacitor to be made smaller, with dimensions reaching 10+ nanometers, significantly increasing the capacitance density per unit volume. This overcomes the miniaturization limitations imposed by the manufacturing process on the annular or columnar structure of capacitors in related technologies.

[0056] This disclosure provides a method for manufacturing a capacitor 1. Figure 1 This is a schematic flowchart illustrating a method for fabricating a capacitor 1 according to an exemplary embodiment of this disclosure, as shown below. Figure 1 As shown, the method for manufacturing a capacitor includes:

[0057] Step S110: Provide a fill layer.

[0058] like Figure 2 As shown, Figure 2 This is a schematic diagram of the filling layer 10 provided in the fabrication method of capacitor 1 according to an exemplary embodiment of this disclosure. The material of the filling layer 10 may include oxides, such as, but not limited to, silicon oxide and silicon oxynitride. The material of the filling layer 10, including oxides, can prevent leakage and short circuit between the upper and lower electrodes of capacitor 1.

[0059] Step S120: Form multiple openings in the filler layer.

[0060] Continue to refer to Figure 2 As shown, openings 20 are formed in the filling layer 10. There can be multiple openings 20, such as circular, rectangular, or other irregularly shaped openings. These multiple openings 20 can be arranged in an array, for example, as shown in... Figure 2 As shown, some of the multiple openings 20 are evenly arranged into opening groups 201 along the first direction, and multiple opening groups 201 are arranged in parallel along the second direction, with the first direction perpendicular to the second direction. The multiple openings 20 can also be arranged randomly.

[0061] The distance between adjacent openings 20 can be determined as needed to meet functional requirements; for example, the distance between adjacent openings 20 can be greater than a preset distance. The depth of the openings 20 can be set as needed, along the thickness direction of the filling layer 10. Figure 3 As shown, Figure 3is a cross-sectional view of the structure after forming a plurality of openings in the filling layer 10 in the method of manufacturing a capacitor according to an example embodiment of the present disclosure. Figure 3 The sidewall of the opening 20 extends along the thickness of the filling layer.

[0062] The method of forming the openings 20 in the filling layer 10 can be any method that can form the openings 20. For example, a patterned first mask layer can be formed on the filling layer 10, the patterned first mask layer having a plurality of first opening patterns. The filling layer 10 can be etched to a predetermined height using the patterned first mask layer as a mask to form a plurality of openings 20 in the filling layer 10. In an example embodiment, the projection of the sidewall of the opening 20 on the filling layer 10 can be a circular structure. The number and the size of the diameter of the openings 20 can be set according to the density of the capacitor.

[0063] At step S130, a plurality of lower electrodes are formed in the plurality of openings, respectively.

[0064] Referring to Figure 4 and Figure 5 , it is shown that a plurality of lower electrodes 30 are formed in the plurality of openings 20, respectively, in the method of manufacturing a capacitor according to an example embodiment of the present disclosure. Figure 4 is a cross-sectional view of the structure after forming a plurality of lower electrodes 30 in the plurality of openings 20, respectively, in the method of manufacturing a capacitor according to an example embodiment of the present disclosure. Figure 5 is a cross-sectional view of the structure after forming a plurality of lower electrodes 30 in the plurality of openings 20, respectively, in the method of manufacturing a capacitor according to an example embodiment of the present disclosure.

[0065] In an example embodiment of the present disclosure, a plurality of lower electrodes 30 are formed in the plurality of openings 20, respectively. One lower electrode 30 is formed in each opening 20, and the lower electrode 30 covers part of the sidewall of the opening 20. Figure 3 In an example embodiment, the projection of the sidewall of the opening 20 on the filling layer 10 is a circular structure, and the lower electrode 30 includes a first arc surface 301. The first arc surface 301 covers part of the sidewall of the opening 20.

[0066] The lower electrode 30 can be deposited on part of the sidewall of the opening 20 using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process, and the lower electrode 30 covers part of the sidewall of the opening 20. The material of the lower electrode 30 can be any electrode material, for example, can include but is not limited to, selected from titanium nitride, molybdenum nitride, tungsten nitride, tantalum nitride, aluminum nitride, ruthenium nitride, or an alloy thereof, or selected from indium tin oxide, tin oxide, indium zinc oxide, and selected from aluminum, tantalum, chromium, copper, gold, platinum, ruthenium.

[0067] In step S140, a dielectric layer is formed on the remaining portion of the fill layer and on the plurality of lower electrodes, with one side of the dielectric layer contacting the plurality of lower electrodes.

[0068] like Figure 6 and Figure 7 As shown, Figure 6 A schematic diagram of the structure after forming a dielectric layer 40 on a plurality of lower electrodes 30 is shown in a method for fabricating a capacitor according to an exemplary embodiment of the present disclosure. Figure 7 A schematic cross-sectional view of the capacitor fabrication method shown in an exemplary embodiment of this disclosure is illustrated, showing the dielectric layer 40 formed on a plurality of lower electrodes 30.

[0069] like Figure 4 , Figure 6 and Figure 7 As shown, a lower electrode 30 is formed within the opening 20, and the lower electrode 30 includes a first arcuate surface 301 and a first flat surface 302. The first arcuate surface 301 covers a portion of the sidewall of the opening 20. A dielectric layer 40 is formed on the remaining portion 101 of the filling layer 10 and on the plurality of lower electrodes 30. Figure 6 As shown, one side 401 of the dielectric layer 40 contacts the first plane 302 of the plurality of lower electrodes 30. The dielectric layer 40 penetrates the plurality of openings 20 and the remaining portion 101 of the fill layer 10, such that one side 401 of the dielectric layer 40 contacts the first plane 302 of the plurality of lower electrodes 20. The thickness of the dielectric layer 40 can be set according to the functional requirements of the capacitor. The first arc surfaces 301 of the plurality of lower electrodes 30 respectively cover a portion of the sidewalls of the plurality of openings 20, and one side 401 of the dielectric layer 40 contacts the first plane 302 of the plurality of lower electrodes 30.

[0070] A first trench 701 penetrating the plurality of openings 20 can be formed in the remaining portion 101 of the fill layer 10, the depth of the trench being the same as the depth of the plurality of openings 20. A dielectric layer 40 is deposited in the first trench 701 and the first plane 301 of the plurality of lower electrodes 30 using atomic layer deposition (ALD) or chemical vapor deposition (CVD). One side 401 of the dielectric layer 40 contacts the first plane 302 of the plurality of lower electrodes 30.

[0071] The material of the dielectric layer 40 can be a material mixed from a plurality of materials, so that the dielectric layer 40 contains at least one dielectric material, which can be selected from a material with a high dielectric constant (High K), for example, a material with a dielectric constant of 6-30. Within this range, the material not only has a high dielectric constant to ensure a high storage density of the capacitor, but also is suitable for process filling, avoiding the situation that the dielectric constant is too high to adapt to the aspect ratio of the opening 20, resulting in the inability to fill. Further, for example, the dielectric constant can be 6-20, and specific materials can include one or more combinations of silicon nitride (Si3N4), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), hafnium oxide (HfO), zirconium dioxide (NbO), etc.

[0072] The first groove 701 can be set in any manner, for example, along the opening group 201 group. Figure 6 It can be seen that the first groove 701 is arranged between each opening in each opening group 201.

[0073] Step S150, forming an upper electrode structure on the dielectric layer, the other side of the dielectric layer contacts the upper electrode structure.

[0074] As shown in Figures 7-10 , the preparation method of the capacitor shown in the exemplary embodiment of the present disclosure is shown after the upper electrode structure 50 is formed on the dielectric layer 40. Figures 7-10 As shown in

[0075] , the first arc surface 301 of the plurality of lower electrodes 30 respectively covers part of the sidewall of the plurality of openings 20, and the one side 401 of the dielectric layer 40 contacts the first plane 302 of the plurality of lower electrodes 30. The upper electrode structure 50 is formed on the other side 402 of the dielectric layer 40. The other side 402 of the dielectric layer 40 contacts the upper electrode structure 50. The plurality of lower electrodes 30 and the upper electrode structure 50 are arranged on the two sides of the dielectric layer 40, so that the capacitor can meet the micro requirements without being affected by the thickness of the dielectric layer 40, greatly improving the limit of the capacitor micro. Figures 7-10 Step S160, the remaining filling layer is finally formed as a gap filling layer, which fills the remaining gaps between the plurality of lower electrodes.

[0076] Continuing to refer to

[0077] , the remaining filling layer is finally formed as a gap filling layer 102, which fills the remaining gaps between the plurality of lower electrodes 30. Figures 7-10

[0078] ​In the exemplary embodiment of the present disclosure, after forming a plurality of openings 20 in the filling layer 10 by forming a patterned mask layer having a plurality of opening patterns on the filling layer 10, etching the filling layer 10 to a predetermined height using the patterned mask layer as a mask, forming a plurality of lower electrodes 30 in the plurality of openings 20, forming a first trench 701 through the plurality of openings 20 in the remaining portion 101 of the filling layer 10, depositing a dielectric layer 40 on the first plane 301 of the first trench 701 and the plurality of lower electrodes 30, and contacting one side 401 of the dielectric layer 40 with the plurality of lower electrodes 30, forming an upper electrode structure 50 on the dielectric layer 40, and contacting the other side 402 of the dielectric layer 40 with the upper electrode structure 50, the remaining filling layer is finally formed as a gap filling layer 102 that fills the remaining gaps between the plurality of lower electrodes 30. The gap filling layer 102 separates adjacent two lower electrodes 30, and can prevent leakage or short circuit between the adjacent two lower electrodes 30.

[0079] In the exemplary embodiment of the present disclosure, the upper electrode structure 50 is formed on one side of the plurality of lower electrodes 30, and the plurality of lower electrodes 30 and the upper electrode structure 50 are formed on both sides of the dielectric layer 40, so that the size adjustment of the plurality of lower electrodes 30 and the upper electrode structure 50 during the preparation of the capacitor can not be affected by the required thickness of the dielectric layer 40 when meeting the miniaturization requirement. As long as sufficient spacing is reserved between the plurality of lower electrodes 30 and the upper electrode structure 50, sufficient thickness of the dielectric layer 40 is ensured, and the capacitance density in a unit volume is greatly improved.

[0080] In the exemplary embodiment of the present disclosure, as shown in Figure 7 and Figure 8 The upper electrode structure 50 includes a plurality of first upper electrodes 501. The process of forming the upper electrode structure 50 on the dielectric layer 40 includes:

[0081] Forming a plurality of first upper electrodes 501 on the other side 402 of the dielectric layer 40, and the plurality of first upper electrodes 501 have the gap filling layer 102 therebetween.

[0082] Continuing to refer to Figure 8A plurality of lower electrodes 30 are formed in the plurality of openings 20 respectively. One side 401 of the dielectric layer 40 contacts the first planes 302 of the plurality of lower electrodes 30. A plurality of first upper electrodes 501 are formed on the other side 402 of the dielectric layer 40. The plurality of first upper electrodes 501 are formed in the plurality of openings 20 respectively, and each of the first upper electrodes 501 includes a second plane 5011 and a second arc surface 5012. The other side 402 of the dielectric layer 40 contacts the second planes 5011 of the plurality of first upper electrodes 501. The second arc surfaces 5012 of the plurality of first upper electrodes 501 cover the other part of the sidewalls of the openings 20 respectively. The material of the plurality of first upper electrodes 501 can be any electrode material, which can be the same as or different from the material of the plurality of lower electrodes 30.

[0083] With reference to the foregoing Figure 7 and Figure 8 , the plurality of first upper electrodes 501 have a gap filling layer 102 therebetween. The gap filling layer 102 fills the remaining gaps between the plurality of first upper electrodes 501. The gap filling layer 102 separates the adjacent two first upper electrodes 501, which can prevent the leakage or short circuit between the plurality of first upper electrodes 501.

[0084] In an exemplary embodiment of the present disclosure, the plurality of first upper electrodes 501 and the plurality of lower electrodes 30 can be symmetrically arranged on both sides of the dielectric layer 40, as shown in Figure 7 and Figure 8 . They can also be arranged in other ways on both sides of the dielectric layer 40, which is not limited in the present disclosure.

[0085] In the preparation method of the capacitor provided in the exemplary embodiment of the present disclosure, the plurality of first upper electrodes 501 are arranged in the plurality of openings 20 respectively, which ensures that the plurality of lower electrodes 30 and the upper electrode structure 50 can be arranged on both sides of the dielectric layer 40, so that the size adjustment of the plurality of lower electrodes 30 and the upper electrode structure 50 will not be affected by the dielectric layer 40 when the capacitor is adapted to the miniaturization requirement, thereby improving the capacitance density in the unit volume.

[0086] In the preparation method of the capacitor provided in the exemplary embodiment of the present disclosure, the plurality of first upper electrodes 501 and the plurality of lower electrodes 30 can be formed on both sides of the dielectric layer 40 at the same time, so that they are arranged on both sides of the dielectric layer 40, for example, symmetrically arranged on both sides of the dielectric layer 40. The plurality of first upper electrodes 501 and the plurality of lower electrodes 30 are formed on both sides of the dielectric layer 40 at the same time, which ensures the consistency and stability of the performance between the plurality of first upper electrodes 501 and the plurality of lower electrodes 30.

[0087] As shown in Figure 11 , Figure 11 shows a method flowchart of the preparation method of the capacitor provided in the exemplary embodiment of the present disclosure, which includes:

[0088] Step S210, providing a filling layer.

[0089] Step S220, forming a plurality of openings on the filling layer.

[0090] The implementation manners of S210-S220 of this embodiment and S110-S120 of the foregoing embodiment are the same, and details are not described herein.

[0091] Step S230, forming a plurality of electrode pillars in the plurality of openings respectively.

[0092] As shown in Figure 12 and 13 , a structure schematic diagram of a capacitor after a plurality of electrode pillars 60 are formed in a plurality of openings 20 in a preparation method of the capacitor is shown. Figure 12 A cross-sectional structure schematic diagram of a capacitor after a plurality of electrode pillars 60 are formed in a plurality of openings 20 in a preparation method of the capacitor is shown. Figure 13 A cross-sectional structure schematic diagram of a capacitor after a plurality of electrode pillars 60 are formed in a plurality of openings 20 in a preparation method of the capacitor is shown.

[0093] The electrode material is deposited in the plurality of openings 20 to form the plurality of electrode pillars 60. The plurality of openings 20 can be arranged in an array, and the plurality of electrode pillars 60 also correspondingly arranged in an array along with the array arrangement of the plurality of openings 20. For example, as shown in Figure 12 , some of the plurality of electrode pillars 60 are arranged into electrode pillar groups 601 along a first direction, and a plurality of groups of electrode pillars 60 are arranged in parallel along a second direction, and the first direction is perpendicular to the second direction. The plurality of electrode pillars 60 can also be arranged randomly. The upper surfaces of the plurality of electrode pillars 60 can be flush with the upper surface of the filling layer 20. The material of the plurality of electrode pillars 60 can be any electrode material, for example, can include but is not limited to, selected from titanium nitride, molybdenum nitride, tungsten nitride, tantalum nitride, aluminum nitride, ruthenium nitride, or an alloy thereof, or selected from indium tin oxide, tin oxide, indium zinc oxide, and selected from aluminum, tantalum, chromium, copper, gold, platinum, ruthenium.

[0094] Step S240, patterning the remaining part of the filling layer and the plurality of electrode pillars to form isolation trenches 70 in the remaining part of the filling layer 10 and the plurality of electrode pillars 60, and the isolation trenches 70 respectively separate the plurality of electrode pillars 60 into a plurality of first upper electrodes 501 and a plurality of lower electrodes 30.

[0095] As shown in Figure 14 and Figure 15 , a structure schematic diagram of a capacitor after a plurality of isolation trenches 70 are formed in a preparation method of the capacitor is shown. Figure 14 A cross-sectional structure schematic diagram of a capacitor after a plurality of isolation trenches 70 are formed in a preparation method of the capacitor is shown. Figure 15 A cross-sectional structure schematic diagram of a capacitor after a plurality of isolation trenches 70 are formed in a preparation method of the capacitor is shown.

[0096] A plurality of electrode pillars 60 are formed in the plurality of openings 20. A second mask layer can be formed on the surface formed by the upper surfaces of the plurality of electrode pillars 60 and the upper surface of the remaining portion 101 of the filling layer 10, and a plurality of second opening patterns are arranged on the second mask layer in a preset direction. The plurality of electrode pillars 60 and the remaining portion 101 of the filling layer 10 are etched downwards along the plurality of second opening patterns until the plurality of electrode pillars 60 are penetrated, with the second mask layer as a mask and the etching being stopped. A plurality of isolation trenches 70 are formed in the plurality of electrode pillars 60 and the remaining portion 101 of the filling layer 10. The plurality of isolation trenches 70 include a first trench 701 in the remaining portion 101 of the filling layer 10 and a second trench 702 penetrating the plurality of electrode pillars 60. The second trench 702 separates the plurality of electrode pillars 60 into a plurality of first upper electrodes 501 and a plurality of lower electrodes 30, respectively. The preset direction forms a preset angle with the first direction, i.e., the preset direction and the first direction have a preset included angle. The preset included angle is determined according to actual needs. For example, if the first upper electrode 501 and the lower electrode 30 in each electrode pillar 60 are required to be symmetrically arranged, the preset included angle can be set to 0 degrees. If the first upper electrode 501 and the lower electrode 30 in each electrode pillar 60 are required to be asymmetrically arranged, the angle of the preset included angle can be set according to needs. The pattern of the isolation trench 70 can be determined according to needs, i.e., the second opening pattern can be determined according to needs. For example, the side edges of the second opening on opposite sides can be linear. The sidewall of the isolation trench 70 is planar.

[0097] In step S250, a dielectric layer 40 is formed in the isolation trench, one side of the dielectric layer 40 being in contact with the plurality of lower electrodes 30 and the other side being in contact with the plurality of first upper electrodes 501.

[0098] As shown in Figure 16 and Figure 17 , the preparation method of the capacitor is shown in the structure schematic diagram after the dielectric layer 40 is formed in the isolation trench 70. Figure 16 The preparation method of the capacitor is shown in the cross-sectional structure schematic diagram after the dielectric layer 40 is formed in the isolation trench 70. Figure 17 The preparation method of the capacitor is shown in the cross-sectional structure schematic diagram after the dielectric layer 40 is formed in the isolation trench 70.

[0099] A plurality of isolation trenches 70 are formed in the plurality of electrode pillars 60 and the remaining portion 101 of the filling layer 10. A dielectric layer 40 is deposited in the plurality of isolation trenches 70. The dielectric layer 40 can be deposited in the isolation trenches 70 using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The dielectric layer 40 comprises at least one dielectric material. The dielectric material can be a high-k material, such as a material having a dielectric constant of 6-30. The high-k material can be one or a combination of silicon nitride (Si3N4), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), hafnium oxide (HfO), zirconium dioxide (NbO), or the like.

[0100] The dielectric layer 40 is formed in the isolation trenches 70. One side 401 of the dielectric layer 40 contacts the plurality of lower electrodes 30, and the other side 402 of the dielectric layer 40 contacts the plurality of first upper electrodes 501. As shown in FIG. 2, the plurality of lower electrodes 30 and the plurality of first upper electrodes 501 are formed in the openings 20 and are separated by the dielectric layer 40. Figure 16 and Figure 17 The plurality of lower electrodes 30 and the plurality of first upper electrodes 501 are formed in the openings 20 and are separated by the dielectric layer 40. Each lower electrode 30 comprises a first curved surface 301 and a first flat surface 302. The first curved surface 301 covers part of the sidewall of the opening 20. The one side 401 of the dielectric layer 40 contacts the first flat surface 302 of the plurality of lower electrodes 30. Each first upper electrode 501 comprises a second flat surface 5011 and a second curved surface 5012. The second curved surfaces 5012 of the plurality of first upper electrodes 501 respectively cover other parts of the sidewall of the opening 20, and the other side 402 of the dielectric layer 40 contacts the second flat surfaces 5011 of the plurality of first upper electrodes 501. The dielectric layer 40 penetrates the plurality of electrode pillars 60 due to the plurality of isolation trenches 70. The plurality of lower electrodes 30 and the plurality of first upper electrodes 501 separated by the dielectric layer 40 are thus isolated, and short-circuiting between the plurality of lower electrodes 30 and the plurality of first upper electrodes 501 is avoided.

[0101] The one side 401 of the dielectric layer 40 contacts the first flat surfaces 302 of the plurality of lower electrodes 30, and the other side 402 of the dielectric layer 40 contacts the second flat surfaces 5011 of the plurality of first upper electrodes. The sidewalls of the one side 401 and the other side 402 of the dielectric layer 40 are flat, ensuring that the plurality of lower electrodes 30 and the plurality of first upper electrodes 501 are separated by the dielectric layer 40. The upper surface of the dielectric layer 40 can be flush with the upper surfaces of the plurality of lower electrodes 30 and the plurality of first upper electrodes 501, and flush with the upper surface of the filling layer 10.

[0102] In the method for manufacturing the capacitor provided by the exemplary embodiments of the present disclosure, the plurality of first upper electrodes 501 and the plurality of lower electrodes 30 are formed on both sides of the dielectric layer 40 at the same time, ensuring the consistency and stability of the performance between the plurality of first upper electrodes 501 and the plurality of lower electrodes 30, and avoiding short circuit between the plurality of lower electrodes 30 and the plurality of first upper electrodes 501 by arranging the plurality of electrode pillars 60 through the dielectric layer 40 on both sides of the dielectric layer 40.

[0103] In the method for manufacturing the capacitor provided by the exemplary embodiments of the present disclosure, the upper electrode structure 50 further comprises a second upper electrode 502, Figure 20 The process of forming the upper electrode structure on the dielectric layer provided by the exemplary embodiments of the present disclosure is shown to include:

[0104] Step S310, providing a filling layer.

[0105] Step S320, forming a plurality of openings on the filling layer.

[0106] Step S330, forming a plurality of electrode pillars in the plurality of openings, respectively.

[0107] Step S340, patterning the remaining part of the filling layer and the plurality of electrode pillars to form isolation trenches in the remaining part of the filling layer and the plurality of electrode pillars, respectively, the isolation trenches separating the plurality of electrode pillars into a plurality of first upper electrodes and a plurality of lower electrodes.

[0108] Step S350, forming a dielectric layer in the isolation trenches, one side of the dielectric layer contacting the plurality of lower electrodes and the other side contacting the plurality of first upper electrodes.

[0109] The implementation manners of steps S310-350 of the present embodiment and steps S210-250 of the foregoing embodiments are the same, and thus will not be described here again

[0110] Step S360, forming a shielding layer 80 on the plurality of lower electrodes.

[0111] Step S370, forming a second upper electrode on the plurality of first upper electrodes, the second upper electrode connecting the plurality of first upper electrodes together.

[0112] Continuing to refer to Figure 9 and Figure 10 and Figure 18 and Figure 19 forming a dielectric layer 40 in the isolation trenches, one side 401 of the dielectric layer contacting the plurality of lower electrodes 30 and the other side 402 contacting the plurality of first upper electrodes 501. The upper surface of the dielectric layer 40 can be flush with the upper surfaces of the plurality of lower electrodes 30 and the plurality of first upper electrodes 501, and flush with the upper surface of the filling layer 10.

[0113] A second upper electrode 502 is formed on the plurality of first upper electrodes 501, and the second upper electrode 502 connects the plurality of first upper electrodes 501 together. The second upper electrode 502 is a common upper electrode layer, such as, but not limited to, germanium silicon, to connect the plurality of first upper electrodes 501 to a target layer, such as, but not limited to, a metal layer (not shown).

[0114] Since the second upper electrode 502 cannot contact the plurality of lower electrodes 30, the second upper electrode 502 avoids shorting with the plurality of lower electrodes 30. Before forming the second upper electrode 502, a blocking layer 80 can also be formed on the plurality of lower electrodes.

[0115] To avoid connecting with the plurality of lower electrodes 30 during the process of forming the second upper electrode 502, the blocking layer 80 is formed on the plurality of lower electrodes 30 before forming the second upper electrode 502. An initial blocking layer can be formed on the surface of the dielectric layer 40, the upper surface of the plurality of lower electrodes 30, the upper surface of the plurality of first upper electrodes 501, and the upper surface of the fill layer 10. A third mask layer is formed on the initial blocking layer, and the third mask layer is provided with a plurality of third opening patterns. The projection of the area of the third mask layer other than the plurality of third opening patterns on the fill layer 10 covers the plurality of lower electrodes 30. The third mask layer is used as a mask to etch downward along the plurality of third opening patterns. The exposed initial blocking layer is removed, and the remaining initial blocking layer forms the blocking layer 80, which blocks the plurality of lower electrodes 30. For further reference, see Figure 9 and Figure 10 and Figure 18 and Figure 19 The blocking layer 80 blocks the plurality of lower electrodes 30. The material of the blocking layer can be a photoresist material.

[0116] After forming the blocking layer 80, a second upper electrode material is deposited on the surface of the dielectric layer 40, the upper surface of the plurality of lower electrodes 30, the upper and side surfaces of the blocking layer 80, and the upper surface of the fill layer 10 to form an initial second upper electrode layer 502. The thickness of the second upper electrode layer 502 can be the same as or different from the thickness of the blocking layer 80. When the thickness of the second upper electrode layer 502 is the same as the thickness of the blocking layer 80, the second upper electrode material covering the upper surface of the blocking layer 80 is removed. When the thickness of the second upper electrode layer 502 is different from the thickness of the blocking layer 80, the second upper electrode material covering the upper surface and part of the side surface of the blocking layer 80 is removed, so that the area other than the blocking layer 80 is covered with the second upper electrode material to form the second upper electrode layer 502. The blocking layer 80 covers the plurality of lower electrodes 30, which effectively isolates the second upper electrode 502 from the plurality of lower electrodes 30, avoiding shorting between the second upper electrode 502 and the plurality of lower electrodes 30.

[0117] In the method for manufacturing a capacitor provided by the exemplary embodiments of the present disclosure, the filling layer 10 comprises an oxygen-containing insulating layer. Figure 21 The process for providing a filling layer provided by the exemplary embodiments of the present disclosure is shown as follows:

[0118] Step S111, forming an oxide layer;

[0119] Step S112, heat treating the oxide layer in a preset temperature range to form an oxygen-containing insulating layer, and the density of the oxygen-containing insulating layer is greater than the density of the dielectric layer.

[0120] In the present embodiment, the filling layer can comprise an oxygen-containing insulating layer 11, and the oxide of the oxygen-containing insulating layer can comprise but is not limited to silicon oxide and silicon oxynitride. The filling layer comprising the oxygen-containing insulating layer 11 can prevent the leakage and short circuit between the upper and lower electrodes of the capacitor. In order to improve the insulation performance of the filling layer, after the oxide layer 12 is formed, the oxide layer 12 is heat treated in a preset temperature range, for example, 1100-2300℃, for example, 1300℃ or 1800℃, to form a high-density oxygen-containing insulating layer 11, and the density of the oxygen-containing insulating layer is greater than the density of the dielectric layer. The density of the oxygen-containing insulating layer 11 is greater than the density of the dielectric layer 40, which further improves the insulation between the plurality of lower electrodes 30 or the plurality of first upper electrodes 501, and provides more possibilities for improving the capacitance density per unit volume.

[0121] The capacitor provided by the exemplary embodiments of the present disclosure is shown as follows: Figure 10 and Figure 19 As can be seen, the capacitor comprises a plurality of lower electrodes 30; an upper electrode structure 50 formed on one side of the plurality of lower electrodes 30; a dielectric layer 40, one side 401 of the dielectric layer 40 contacting the plurality of lower electrodes 30, and the other side 402 contacting the upper electrode structure 50; and a gap filling layer 102 filling the remaining gaps between the plurality of lower electrodes. The plurality of lower electrodes 30 are filled with the gap filling layer 102, which can prevent the leakage or short circuit between the plurality of lower electrodes 30.

[0122] In the capacitor provided by the exemplary embodiments of the present disclosure, the upper electrode structure 50 is formed on one side of the plurality of lower electrodes 30, and the plurality of lower electrodes 30 and the upper electrode structure 50 are formed on both sides of the dielectric layer 40, so that the size adjustment of the plurality of lower electrodes 30 and the upper electrode structure 50 will not be affected by the required thickness of the dielectric layer 40. As long as there is enough space between the plurality of lower electrodes 30 and the upper electrode structure 50, and the dielectric layer 40 has enough thickness, the capacitance density per unit volume is greatly improved.

[0123] The capacitor provided by the exemplary embodiments of the present disclosure is shown as follows: Figure 6 and Figure 14The plurality of lower electrodes 30 can be arranged in an array. For example, the plurality of lower electrodes 30 are arranged in a plurality of lower electrode groups 301 in a first direction, and the plurality of lower electrode groups 301 are arranged in parallel in a second direction, the first direction being perpendicular to the second direction. The plurality of lower electrodes 30 can also be arranged randomly. The lower electrode includes a first planar surface and a first curved surface, the first planar surface contacting the dielectric layer, and the first curved surface contacting the gap fill layer. As shown in Figure 5 and 6 The side 401 of the dielectric layer 40 contacts the first planar surfaces 302 of the plurality of lower electrodes 30. The first curved surfaces 301 of the plurality of lower electrodes 30 respectively cover part of the sidewalls of the plurality of openings 20, and the side 401 of the dielectric layer 40 contacts the first planar surfaces 302 of the plurality of lower electrodes 30.

[0124] Continuing to refer to Figure 10 and Figure 19 The upper electrode structure 50 can include a plurality of first upper electrodes 501, the plurality of first upper electrodes 501 contacting the dielectric layer 40, and the plurality of first upper electrodes 501 being filled with the gap fill layer 102. The plurality of first upper electrodes 501 being filled with the gap fill layer 102 can prevent leakage or short circuit between the plurality of first upper electrodes 501.

[0125] The side 401 of the dielectric layer 40 contacts the plurality of lower electrodes 30, and the other side 402 contacts the plurality of first upper electrodes 501, so that the plurality of first upper electrodes 501 and the plurality of lower electrodes 30 are arranged on both sides of the dielectric layer 40. The sidewalls of the dielectric layer 40 on both sides are planar, so that the plurality of first upper electrodes 501 and the plurality of lower electrodes 30 are arranged on both sides of the dielectric layer 40, and the plurality of first upper electrodes 501 are arranged on one side of the plurality of lower electrodes 30. When the capacitor is adapted to the miniaturization requirement, the size adjustment of the plurality of lower electrodes 30 and the upper electrode structure 50 will not be affected by the dielectric layer 40, and the capacitance density in a unit volume is improved. The material of the dielectric layer 40 can include a metal oxide material with high dielectric constant, for example, the dielectric layer 40 includes a metal oxide material with a dielectric constant of 6 to 30. In order to improve the insulation between the plurality of lower electrodes 30 or the plurality of first upper electrodes 501, the gap fill layer 102 can include an oxygen-containing insulating material with a higher density than the dielectric layer 40.

[0126] The upper electrode structure can further include a second upper electrode 502, the second upper electrode 502 contacting the plurality of first upper electrodes 501 to connect the plurality of first upper electrodes 501 together. The second upper electrode 502 is formed on the plurality of first upper electrodes 501, the second upper electrode 502 connecting the plurality of first upper electrodes 501 together, the second upper electrode 502 being a common upper electrode layer, so that the plurality of first upper electrodes 501 are connected to a target layer, for example, a metal layer (not shown), through the common upper electrode layer.

[0127] In the exemplary embodiment of the present disclosure, a preparation method of the semiconductor device 1000 is provided. In the exemplary embodiment of the present disclosure, the plurality of first upper electrodes 501 and the plurality of lower electrodes 30 are formed on both sides of the dielectric layer 40 at the same time, so that the two are arranged on both sides of the dielectric layer 40. As shown in Figure 22 Figure 22 A flow chart of the preparation method of the semiconductor device 1000 provided by the exemplary embodiment of the present disclosure is shown:

[0128] Step S410, providing a substrate.

[0129] Referring to Figures 23-27 Figures 23-27 A structure schematic diagram of the semiconductor device 1000 provided by the exemplary embodiment of the present disclosure is shown.

[0130] The substrate 100 can include a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compound, and silicon-carbon compound. Exemplarily, the substrate 100 can be a Silicon-On-Onsulator (SOI) substrate or a Germanium-on-Insulator (GOI) substrate. In other embodiments, the substrate 100 can also be an insulating material such as silicon oxide or silicon nitride.

[0131] Step S420, forming a plurality of contact pads on the substrate;

[0132] Continuing to refer to Figures 23-27 A plurality of contact pads 90 are formed on the substrate 100, and the positions of the plurality of contact pads correspond to the positions of the plurality of lower electrodes 30.

[0133] Step S430, forming a filling layer on the substrate.

[0134] The filling layer 10 can include an oxygen-containing insulating layer 11. The filling layer can be formed in the manner shown in the flowchart. Figure 22 The density of the oxygen-containing insulating layer 11 is greater than the density of the dielectric layer 40, so as to improve the insulation between the plurality of lower electrodes 30 or the plurality of first upper electrodes 501.

[0135] Step S440, forming a plurality of openings 20 on the filling layer.

[0136] In the present embodiment, as shown in Figure 24 The plurality of openings 20 penetrate the filling layer 10 to expose part of the substrate 100 and the plurality of contact pads 90. The step of forming the openings 20 and the arrangement of the openings 20 are the same as those in other embodiments, and will not be described here.

[0137] ​​Step S450, forming a plurality of electrode pillars 60 in the plurality of openings 20 respectively.

[0138] In this embodiment, this step is the same as the implementation of the foregoing step S230, and thus will not be described again here.

[0139] Step S460, patterning the remaining part of the filling layer and the plurality of electrode pillars 60, and forming an isolation trench 70 in the remaining part of the filling layer and the plurality of electrode pillars 60, the isolation trench 70 respectively separates the plurality of electrode pillars 60 into a plurality of first upper electrodes 501 and a plurality of lower electrodes 30.

[0140] In this embodiment, this step is the same as the implementation of the foregoing step S240, and thus will not be described again here. The difference is that, as shown in Figure 25 In this step, the plurality of lower electrodes 30 are respectively located on the plurality of contact pads 90.

[0141] Step S470, forming a dielectric layer 40 in the isolation trench 70, one side 401 of the dielectric layer 40 contacts the plurality of lower electrodes 30, and the other side 402 contacts the plurality of first upper electrodes 501.

[0142] Step S480, forming a shielding layer on the plurality of lower electrodes 30.

[0143] Step S490, forming a second upper electrode 502 on the plurality of first upper electrodes 501, the second upper electrode 502 connects the plurality of first upper electrodes 501 together.

[0144] The implementation of steps S470-490 of this embodiment and steps S350-370 of the foregoing embodiment is the same, and thus will not be described again here.

[0145] The semiconductor device prepared by the preparation method of the semiconductor device provided by the exemplary embodiments of the present disclosure is as shown in Figure 27 The semiconductor device 1000 includes a substrate 100, a plurality of contact pads 90 and a capacitor 1 formed on the substrate 100, wherein the plurality of lower electrodes of the capacitor 1 are respectively located on the plurality of contact pads 90.

[0146] In the semiconductor device provided by the exemplary embodiments of the present disclosure, the semiconductor device 1000 comprises a substrate 100, a plurality of contact pads 90 formed on the substrate 100, and the capacitor 1 provided by the present disclosure, the plurality of lower electrodes 30 of the capacitor 1 are respectively located on the plurality of contact pads 90, and the upper electrode structure 50 is formed on one side of the plurality of lower electrodes 30, the plurality of lower electrodes 30 and the upper electrode structure 50 are formed on both sides of the dielectric layer 40, so that the size adjustment of the plurality of lower electrodes 30 and the upper electrode structure 50 will not be affected by the required thickness of the dielectric layer 40. As long as a sufficient gap is reserved between the plurality of lower electrodes 30 and the upper electrode structure 50, the sufficient thickness of the dielectric layer 40 is ensured, and the capacitance density in the unit volume is greatly improved.

[0147] Each embodiment or implementation in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between embodiments can be referred to each other.

[0148] In the specification, the illustrative description of the above terms does not necessarily refer to the same implementation or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any one or more implementations or examples in a suitable manner.

[0149] In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore cannot be understood as a limitation on the present disclosure.

[0150] It can be understood that the terms "first", "second" and the like used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish the first structure from another structure.

Claims

1. A capacitor, comprising: a plurality of lower electrodes; an upper electrode structure formed on one side of the plurality of lower electrodes; a dielectric layer contacting the plurality of lower electrodes on one side and contacting the upper electrode structure on the other side; a gap filling layer filling the remaining gaps between the plurality of lower electrodes, the length of the lower electrodes being the same as the length of the dielectric layer along the thickness direction of the gap filling layer.

2. The capacitor of claim 1, wherein the upper electrode structure comprises: a plurality of first upper electrodes contacting the dielectric layer and being filled with the gap filling layer between the plurality of first upper electrodes.

3. The capacitor of claim 2, wherein the plurality of first upper electrodes and the plurality of lower electrodes are disposed on both sides of the dielectric layer.

4. The capacitor of any one of claims 1-3, wherein the lower electrodes comprise a first flat surface contacting the dielectric layer and a first curved surface contacting the gap filling layer.

5. The capacitor of any one of claims 2 or 3, wherein the upper electrode structure further comprises: a second upper electrode contacting the plurality of first upper electrodes to connect the plurality of first upper electrodes together.

6. The capacitor of claim 1, wherein the dielectric layer comprises a metal oxide material having a dielectric constant between 6 and 20.

7. The capacitor of claim 1, wherein the gap filling layer comprises an oxygen-containing insulating material having a density greater than the dielectric layer.

8. The capacitor of claim 1, wherein the plurality of lower electrodes are arranged in an array.

9. A method of fabricating a capacitor, comprising: providing a filling layer; forming a plurality of openings on the filling layer; forming a plurality of lower electrodes in the plurality of openings, respectively; forming a dielectric layer on the remaining portion of the filling layer and on the plurality of lower electrodes, the dielectric layer contacting the plurality of lower electrodes on one side and contacting an upper electrode structure on the other side, the length of the lower electrodes being the same as the length of the dielectric layer along the thickness direction of the filling layer; forming the upper electrode structure on the dielectric layer; forming a gap filling layer from the remaining portion of the filling layer to fill the remaining gaps between the plurality of lower electrodes.

10. The method of claim 9, wherein the forming the upper electrode structure on the dielectric layer comprises: forming a plurality of first upper electrodes on the other side of the dielectric layer, the plurality of first upper electrodes being filled with the gap filling layer between the plurality of first upper electrodes.

11. The method of claim 10, wherein the plurality of first upper electrodes and the plurality of lower electrodes are formed on both sides of the dielectric layer at the same time to be disposed on both sides of the dielectric layer.

12. The method of claim 11, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The process of simultaneously forming the plurality of first upper electrodes and the plurality of lower electrodes comprises: forming a plurality of electrode pillars in the plurality of openings, respectively; patterning the remaining portion of the filling layer and the plurality of electrode pillars to form isolation trenches in the remaining portion of the filling layer and the plurality of electrode pillars, the isolation trenches separating the plurality of electrode pillars into the plurality of first upper electrodes and the plurality of lower electrodes, respectively; forming the dielectric layer in the isolation trenches, one side of the dielectric layer contacting the plurality of lower electrodes and the other side of the dielectric layer contacting the plurality of first upper electrodes.

13. The method of any one of claims 10-12, wherein: the process of forming the upper electrode structure on the dielectric layer further comprises: forming second upper electrodes on the plurality of first upper electrodes, the second upper electrodes connecting the plurality of first upper electrodes together.

14. The method of claim 9, wherein: the filling layer comprises an oxygen-containing insulating layer, and the process of providing the filling layer comprises: forming an oxide layer; heat treating the oxide layer at a predetermined temperature range to form the oxygen-containing insulating layer, and the oxygen-containing insulating layer has a higher density than the dielectric layer.

15. A semiconductor device, comprising: a substrate; a plurality of contact pads formed on the substrate; a capacitor as claimed in any one of claims 1-8, the plurality of lower electrodes of the capacitor being located on the plurality of contact pads, respectively. ​

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