Optoelectronic detection circuit, method for controlling the same and pixel cell

Abstract

Provided are a photoelectric detection circuit (100), a control method thereof, and a pixel unit. The photoelectric detection circuit (100) comprises: a detection sub-circuit (10) connected to a detection voltage signal end (V_S), a bias voltage signal end (V_B), and an input node (PD), and configured to generate a current flowing between the bias voltage signal end (V_B) and the input node (PD) in response to a light signal under the control of the potential of the detection voltage signal end (V_S); a storage sub-circuit (20) connected between the bias voltage signal end (V_B) and the input node (PD), and configured to perform energy storage based on the current generated by the detection sub-circuit (10); an integration sub-circuit (30) having a first input end (V_IN), a second input end (V_R), and an output end (V_OUT), and configured to integrate a signal of the first input end (V_IN) based on the potential of the second input end (V_R) to generate an integrated signal and output at the output end (V_OUT); and a control sub-circuit (40) connected to a control signal end (GATE), the input node (PD), and the first input end (V_IN) of the integration sub-circuit (30).

Description

Technical Field

[0001] This disclosure relates to the field of photoelectric detection technology, and in particular to a photoelectric detection circuit, its control method, and a pixel unit. Background Technology

[0002] Typically, for optical fingerprint recognition, photosensitive devices are arranged in an array to collect intensity changes in reflected or transmitted light caused by finger textures, and then the photosensitive devices perform photoelectric conversion. Based on the electrical signal converted from light intensity, a fingerprint image can be acquired, thereby enabling optical fingerprint recognition. However, the detection performance of most current detection circuits is not ideal. Summary of the Invention

[0003] This disclosure provides a photoelectric detection circuit, which includes:

[0004] The detection sub-circuit connects the detection voltage signal terminal, the bias voltage signal terminal, and the input node, and is configured to generate a current flowing between the bias voltage signal terminal and the input node in response to a light signal under the control of the potential of the detection voltage signal terminal.

[0005] A storage subcircuit is connected between the bias voltage signal terminal and the input node and is configured to store energy based on the current generated by the detection subcircuit.

[0006] An integrator circuit has a first input terminal, a second input terminal, and an output terminal, and is configured to integrate the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal;

[0007] A control subcircuit is connected to a control signal terminal, an input node, and a first input terminal of the integrator circuit, and is configured to provide the potential of the input node to the first input terminal of the integrator circuit under the control of the control signal terminal.

[0008] For example, the storage sub-circuit includes a first capacitor, the first electrode of which is connected to the bias voltage signal terminal, and the second electrode of which is connected to the input node.

[0009] For example, the photoelectric detection circuit further includes a reset auxiliary sub-circuit, wherein the detection sub-circuit is connected to the bias voltage signal terminal through the reset auxiliary sub-circuit, and the reset auxiliary sub-circuit is configured to electrically connect the detection sub-circuit to the bias voltage signal terminal during the detection period under the control of the reset auxiliary signal terminal, and electrically isolate the detection sub-circuit from the bias voltage signal terminal during the reset period.

[0010] For example, the reset auxiliary sub-circuit includes a first transistor, the gate of which is connected to the reset auxiliary signal terminal, the first terminal of which is connected to the bias voltage signal terminal, and the second terminal of which is connected to the detection sub-circuit.

[0011] For example, the photoelectric detection circuit further includes a reset sub-circuit, connected to a reset signal terminal, the input node, and a reset voltage terminal, and configured to provide the potential of the reset voltage terminal to the input node under the control of the signal at the reset signal terminal, wherein the potential of the reset voltage terminal is equal to the potential of the second input terminal of the integrator circuit.

[0012] For example, the reset sub-circuit includes a second transistor, the gate of which is connected to the reset signal terminal, the first terminal of which is connected to the reset voltage terminal, and the second terminal of which is connected to the input node.

[0013] For example, the photoelectric detection circuit further includes an amplification sub-circuit connected between the input node and the control sub-circuit, and connected to a reference voltage terminal. The amplification sub-circuit is configured to generate a current flowing between the reference signal terminal and the control sub-circuit under the control of the potential of the input node.

[0014] For example, the amplification sub-circuit includes a third transistor, the gate of which is connected to the input node, the first terminal of which is connected to the reference voltage terminal, and the second terminal of which is connected to the control sub-circuit.

[0015] For example, the detection sub-circuit includes a fourth transistor, the gate of which is connected to the detection voltage signal terminal, the first terminal of which is connected to the bias voltage signal terminal, and the second terminal of which is connected to the input node.

[0016] For example, the photoelectric detection circuit includes multiple detection sub-circuits.

[0017] For example, the control sub-circuit includes a fifth transistor, the gate of which is connected to the control signal terminal, the first terminal of which is connected to the input node, and the second terminal of which is connected to the first input terminal of the integrator circuit.

[0018] For example, the integrator circuit includes:

[0019] An operational amplifier, wherein the first input terminal of the operational amplifier is connected to the first input terminal of the integrator circuit, the second input terminal of the operational amplifier is connected to the second input terminal of the integrator circuit, and the output terminal of the operational amplifier is connected to the output terminal of the integrator circuit;

[0020] The second capacitor has its first electrode connected to the first input terminal of the operational amplifier, and its second electrode connected to the second input terminal of the operational amplifier.

[0021] For example, the detection sub-circuit includes a fourth transistor, and the control sub-circuit includes a fifth transistor. The fourth transistor and the fifth transistor are disposed on a substrate. The first and second terminals of the fourth transistor are disposed on the same layer as the first and second terminals of the fifth transistor. The active layer of the fourth transistor is disposed on the same layer as the active layer of the fifth transistor. The gate of the fourth transistor is disposed on the side of the active layer of the fourth transistor facing the substrate, and the gate of the fifth transistor is disposed on the side of the active layer of the fifth transistor away from the substrate.

[0022] For example, the fourth and fifth transistors have a planarization layer on the side away from the substrate, the first electrode of the first capacitor is located on the side of the planarization layer away from the substrate, and the second electrode of the first capacitor is located on the side of the planarization layer facing the substrate.

[0023] This disclosure also provides a pixel unit, including:

[0024] At least one pixel circuit, each pixel circuit being configured to emit light based on a data voltage; and

[0025] The photoelectric detection circuit described above.

[0026] For example, the pixel circuit includes a driving transistor, the driving transistor including an active layer on a substrate, a gate on the side of the active layer away from the substrate, a first gate insulating layer between the active layer and the gate, a second gate insulating layer on the side of the gate away from the substrate, an interlayer dielectric layer on the side of the second gate insulating layer away from the substrate, and a source and a drain on the side of the interlayer dielectric layer away from the substrate.

[0027] The detection sub-circuit of the photoelectric detection circuit includes a fourth transistor, and the control sub-circuit of the photoelectric detection circuit includes a fifth transistor. The gate of the fourth transistor is located between the first gate insulating layer and the substrate. The first and second terminals of the fourth transistor are disposed on the same layer as at least one of the source and drain terminals of the driving transistor. The active layer of the fourth transistor is disposed on the same layer as the active layer of the driving transistor. The gate of the fifth transistor is disposed on the same layer as the gate of the driving transistor. The first and second terminals of the fifth transistor are disposed on the same layer as at least one of the source and drain terminals of the driving transistor. The active layer of the fifth transistor is disposed on the same layer as the active layer of the driving transistor.

[0028] For example, the pixel circuit further includes a light-emitting unit, which includes an anode, a cathode, and a light-emitting layer located between the anode and the cathode, wherein a planarization layer is disposed on the side of the interlayer dielectric layer away from the substrate, and the anode is located on the side of the planarization layer away from the substrate and is connected to the source or drain of the driving transistor through the planarization layer.

[0029] The storage sub-circuit of the photoelectric detection circuit includes a first capacitor, the first electrode of the first capacitor is disposed on the same layer as the anode, and the second electrode of the first capacitor is located on the side of the planar surface facing the substrate.

[0030] For example, a first passivation layer and a second passivation layer are further disposed between the planarization layer and the interlayer dielectric layer, wherein the source and drain of the driving transistor are located between the first passivation layer and the interlayer dielectric layer, and the second electrode of the first capacitor is located between the second passivation layer and the first passivation layer.

[0031] This disclosure also provides a control method for the photoelectric detection circuit described above, comprising:

[0032] The detection sub-circuit responds to the optical signal to generate a current flowing between the bias voltage signal terminal and the input node;

[0033] The storage sub-circuit stores energy based on the current generated by the detection sub-circuit.

[0034] Under the control of the control signal terminal, the control sub-circuit provides the potential of the input node to the first input terminal of the integrator circuit;

[0035] The integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal, which is then output at the output terminal.

[0036] For example, the photoelectric detection circuit further includes a reset auxiliary sub-circuit, and the method includes:

[0037] During the detection period, the reset auxiliary sub-circuit, under the control of the reset auxiliary signal terminal, electrically connects the detection sub-circuit to the bias voltage signal terminal. The detection sub-circuit generates a current flowing between the bias voltage signal terminal and the input node in response to the optical signal. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. Under the control of the control signal terminal, the control sub-circuit provides the potential of the input node to the first input terminal of the integrator circuit. The integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal.

[0038] During the reset period, the reset auxiliary sub-circuit electrically isolates the detection sub-circuit from the bias voltage signal terminal under the control of the reset auxiliary signal terminal. The detection sub-circuit electrically connects the bias voltage signal terminal to the input node under the control of the potential of the detection voltage signal terminal. The control sub-circuit electrically connects the input node to the first input terminal of the integrator circuit under the control of the control signal terminal.

[0039] For example, the photoelectric detection circuit further includes a reset sub-circuit, and the method includes:

[0040] During the detection period, the reset sub-circuit electrically isolates the reset voltage terminal from the input node under the control of the reset signal terminal. The detection sub-circuit generates a current flowing between the bias voltage signal terminal and the input node in response to the optical signal. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. The control sub-circuit provides the potential of the input node to the first input terminal of the integrator circuit under the control of the control signal terminal. The integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal.

[0041] During the reset period, the reset sub-circuit connects the reset voltage terminal to the input node under the control of the reset signal terminal, and the control sub-circuit electrically isolates the input node from the first input terminal of the integrator circuit under the control of the control signal terminal.

[0042] For example, the photoelectric detection circuit further includes an amplification sub-circuit, and the method includes:

[0043] During the detection period, the detection sub-circuit, under the control of the potential at the detection voltage signal terminal, responds to the optical signal to generate a current flowing between the bias voltage signal terminal and the input node. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. The amplification sub-circuit, under the control of the potential at the input node, generates a current flowing between the reference signal terminal and the control sub-circuit. The control sub-circuit, under the control of the control signal terminal, provides the current generated by the amplification sub-circuit to the first input terminal of the integrator circuit. The integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal.

[0044] During the reset period, the detection sub-circuit electrically connects the bias voltage signal terminal to the input node under the control of the potential of the detection voltage signal terminal, wherein the potential of the bias voltage signal terminal during the reset period is different from the potential during the detection phase. Attached Figure Description

[0045] Figure 1 This is a schematic block diagram of the photoelectric detection circuit according to an embodiment of the present disclosure;

[0046] Figure 2 This is a circuit diagram of a photoelectric detection circuit according to an embodiment of the present disclosure;

[0047] Figure 3 This is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure;

[0048] Figure 4 This is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure;

[0049] Figure 5 This is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure;

[0050] Figure 6 This is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure;

[0051] Figure 7 This is a cross-sectional view of a photoelectric detection circuit according to an embodiment of the present disclosure;

[0052] Figure 8A This is a top view of a photoelectric detection circuit according to an embodiment of the present disclosure;

[0053] Figure 8B This is a top view of a photoelectric detection circuit according to an embodiment of the present disclosure;

[0054] Figure 9 This is a cross-sectional view of a photoelectric detection circuit according to another embodiment of this disclosure;

[0055] Figure 10 This is a cross-sectional view of a photoelectric detection circuit according to another embodiment of this disclosure;

[0056] Figure 11 This is a cross-sectional view of a photoelectric detection circuit according to another embodiment of this disclosure;

[0057] Figure 12 This is a cross-sectional view of a photoelectric detection circuit according to another embodiment of this disclosure;

[0058] Figure 13 This is a cross-sectional view of a pixel unit according to an embodiment of the present disclosure;

[0059] Figure 14 This is an operation timing diagram of a photoelectric detection circuit according to an embodiment of the present disclosure;

[0060] Figure 15 This is an operation timing diagram of a photoelectric detection circuit according to another embodiment of this disclosure;

[0061] Figure 16 This is an operation timing diagram of a photoelectric detection circuit according to another embodiment of this disclosure;

[0062] Figure 17 This is an operation timing diagram of a photoelectric detection circuit according to another embodiment of the present disclosure; and

[0063] Figure 18 This is a flowchart of a control method for a photoelectric detection circuit according to an embodiment of the present disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0065] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0066] Furthermore, in the description of the embodiments disclosed herein, the terms "connected" or "connected to" can refer to two components being directly connected, or to two components being connected via one or more other components. Additionally, these two components can be connected or coupled via wired or wireless means.

[0067] Terminal devices, such as smartphones and laptops, can provide fingerprint recognition functionality to identify users. In related technologies, for optical fingerprint recognition, photosensitive devices can be arrayed to collect reflected or transmitted light signals from different finger areas. These photosensitive devices then perform photoelectric conversion to obtain an electrical signal based on the light-to-light signal. Finally, an analog-to-digital converter (ADC) is used to convert the electrical signal into a digital signal to complete fingerprint image acquisition.

[0068] In the fabrication of in-display (under-display) fingerprint recognition components, PIN photodiodes are commonly used. PIN photodiodes have a similar structure to semiconductor diodes. The die of a PIN photodiode is a PN junction with photosensitive characteristics, exhibiting unidirectional conductivity. Therefore, a reverse voltage can be provided to the PIN photodiode during operation. In the absence of light, there is a very small saturation reverse leakage current, i.e., dark current, at which point the photodiode is off. When exposed to light, the saturation reverse leakage current increases significantly, forming a photocurrent. This photocurrent varies with the intensity of the incident light. When light shines on the PN junction, electron-hole pairs are generated, increasing the minority carrier density. These carriers drift under reverse voltage, increasing the photocurrent (reverse current). Therefore, the current in the circuit can be changed by utilizing the intensity of light.

[0069] Thin-film transistors (TFTs) can be used as switches to control the discharge of charge in PIN photodiodes. Ideally, no current flows when a TFT is off. However, because there are two PN junctions between the drain / source and the substrate, there is still a reverse saturation current (leakage current) between the drain and source even if the TFT has no channel. When a TFT is illuminated, its output current changes with the intensity of the light; in other words, a TFT can function as a photosensitive device that responds to light.

[0070] Compared to PIN photodiodes, TFTs, as photosensitive devices, can save costs by reducing the number of masks required during fabrication. However, TFTs cannot store electrical charge when used as photosensitive devices.

[0071] Figure 1 This is a schematic block diagram of the photoelectric detection circuit according to an embodiment of the present disclosure.

[0072] like Figure 1 As shown, the photoelectric detection circuit 100 includes a detection sub-circuit 10, a storage sub-circuit 20, an integration sub-circuit 30, and a control sub-circuit 40.

[0073] The detection sub-circuit 10 is connected to the detection voltage signal terminal V_S, the bias voltage signal terminal V_B, and the input node PD. Under the control of the potential of the detection voltage signal terminal V_S, the detection sub-circuit 10 can generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to the optical signal.

[0074] Storage sub-circuit 20 is connected between the bias voltage signal terminal V_B and the input node PD. Storage sub-circuit 20 can store energy based on the current generated by the detection sub-circuit 10. For example, storage sub-circuit 20 may include a first capacitor, with its first electrode connected to the bias voltage signal terminal V_B and its second electrode connected to the input node PD.

[0075] The integrator circuit 30 has a first input terminal V_IN, a second input terminal V_R, and an output terminal V_OUT. The integrator circuit 30 can integrate the signal at the first input terminal V_IN based on the potential of the second input terminal V_R to generate an integrated signal, which is then output at the output terminal V_OUT.

[0076] The control sub-circuit 40 is connected to the control signal terminal GATE, the input node PD, and the first input terminal V_IN of the integrator circuit 30. Under the control of the control signal terminal GATE, the control sub-circuit 40 can provide the potential of the input node PD to the first input terminal V_IN of the integrator circuit 30.

[0077] According to embodiments of this disclosure, by setting the above-described energy storage sub-circuit, energy can be stored based on the current generated by the detection sub-circuit, thereby improving the accuracy of detection.

[0078] The following will refer to Figures 2 to 7 Here are some examples illustrating the output circuitry of embodiments of this disclosure.

[0079] Figure 2 This is a circuit diagram of a photoelectric detection circuit according to an embodiment of the present disclosure.

[0080] like Figure 2 As shown, the photoelectric detection circuit 200 includes a detection sub-circuit 210, a storage sub-circuit 220, an integration sub-circuit 230, and a control sub-circuit 240. The above description of the detection sub-circuit 210, storage sub-circuit 220, integration sub-circuit 230, and control sub-circuit 240 also applies to this embodiment.

[0081] In some embodiments, the detection sub-circuit 210 may include a fourth transistor T4. The gate of the fourth transistor T4 is connected to the detection voltage signal terminal V_S, the first terminal of the fourth transistor T4 is connected to the bias voltage signal terminal V_B, and the second terminal of the fourth transistor T4 is connected to the input node PD. The fourth transistor T4 is configured to generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to an optical signal, under the control of the potential of the detection voltage signal terminal V_S.

[0082] In some embodiments, the storage subcircuit 220 may include a first capacitor C. A first electrode of the first capacitor C is connected to the bias voltage signal terminal V_B, and a second electrode of the first capacitor C is connected to the input node PD. The first capacitor C is configured to store energy based on the current generated by the detection subcircuit 210.

[0083] In some embodiments, the integrator circuit 230 includes an operational amplifier AMP and a second capacitor CF. The first input terminal of the operational amplifier AMP is connected to the first input terminal V_IN of the integrator circuit 230, the second input terminal of the operational amplifier AMP is connected to the second input terminal V_R of the integrator circuit 230, and the output terminal of the operational amplifier AMP is connected to the output terminal V_OUT of the integrator circuit 230. The first electrode of the second capacitor CF is connected to the first input terminal of the operational amplifier, and the second electrode of the second capacitor CF is connected to the second input terminal of the operational amplifier AMP.

[0084] In some embodiments, the control sub-circuit 240 includes a fifth transistor T5. The gate of the fifth transistor T5 is connected to the control signal terminal GATE, the first terminal of the fifth transistor T5 is connected to the input node PD, and the second terminal of the fifth transistor T5 is connected to the first input terminal V_IN of the integrator circuit 30. The fifth transistor T5 can be turned on or off under the control of the control signal terminal GATE. When the fifth transistor T5 is on, the input node PD is electrically connected to the first input terminal V_IN, thereby providing the potential of the input node PD to the first input terminal V_IN of the integrator circuit 30. When the fifth transistor T5 is off, the input node PD is electrically isolated from the first input terminal V_IN, thereby preventing the potential of the input node PD from affecting the output signal of the output terminal V_OUT.

[0085] Figure 3 This is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure.

[0086] like Figure 3As shown, the photoelectric detection circuit 300 includes a detection sub-circuit 310, a storage sub-circuit 320, an integrating sub-circuit 330, and a control sub-circuit 340. The above description of the detection sub-circuit 210, storage sub-circuit 220, integrating sub-circuit 230, and control sub-circuit 240 also applies to the detection sub-circuit 310, storage sub-circuit 320, integrating sub-circuit 330, and control sub-circuit 340, and will not be repeated here.

[0087] like Figure 3 As shown, the photoelectric detection circuit 300 also includes a reset auxiliary sub-circuit 350.

[0088] The detection sub-circuit 310 is connected to the bias voltage signal terminal V_B via the reset auxiliary sub-circuit 350. Under the control of the reset auxiliary signal terminal L_RST, the reset auxiliary sub-circuit 350 can electrically connect the detection sub-circuit 310 to the bias voltage signal terminal V_B during the detection period, and electrically isolate the detection sub-circuit 310 from the bias voltage signal terminal V_B during the reset period.

[0089] For example, the reset auxiliary sub-circuit 350 may include a first transistor T1, the gate of which is connected to the reset auxiliary signal terminal L_RST, the first terminal of which is connected to the bias voltage signal terminal V_B, and the second terminal of which is connected to the detection sub-circuit 310, such as the first terminal of the fourth transistor T4.

[0090] During the detection process, the charge generated by the fourth transistor T4 is stored in the first capacitor C. The signal at the output terminal V_OUT can be read by the back-end readout circuit. During reading, the charge is discharged from the first capacitor C to the capacitor in the back-end readout circuit. When the light intensity is high or the charge discharge time is insufficient, if the charge on the first capacitor C is not completely discharged, this part of the charge will accumulate on C. The next time it is read, the charge left over from the previous frame will be read along with it, causing the readout signal to have a lag.

[0091] By setting a reset auxiliary sub-circuit 350 between the bias voltage signal terminal V_B and the detection sub-circuit 310, the input node PD can be reset, thereby reducing the leakage current of the detection sub-circuit 310.

[0092] For example, during the detection phase, the first transistor T1 of the reset auxiliary sub-circuit 350 is turned on under the control of the reset auxiliary signal terminal L_RST, thereby providing the bias voltage of the bias voltage signal terminal V_B to the detection sub-circuit 310 for photoelectric detection.

[0093] After the data reading at the output terminal V_OUT is completed, i.e., after the first capacitor C has discharged, the reset phase begins. The first transistor T1 of the reset auxiliary sub-circuit 350 is turned off under the control of the reset auxiliary signal terminal L_RST, thereby electrically isolating the fourth transistor T4 and the fifth transistor T5 from the bias voltage signal terminal V_B. During the reset phase, both the fourth transistor T4 and the fifth transistor T5 are turned on, thus resetting the potential of the input node PD to the voltage of the second input terminal V_R. The width-to-length ratio of the first transistor T1 can be set to be smaller than that of the fourth transistor T4. Although there is a voltage difference between the first and second terminals of the first transistor T1, the resulting leakage current is small, thus having a smaller impact on the potential at the first terminal of the first transistor T1. Since there is no voltage difference between the first and second terminals of the fourth transistor T4 in the detection sub-circuit 310, no leakage current can be formed, thereby reducing hysteresis.

[0094] Figure 4 This is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure.

[0095] like Figure 4 As shown, the photoelectric detection circuit 400 includes a detection sub-circuit 410, a storage sub-circuit 420, an integrating sub-circuit 430, and a control sub-circuit 440. The above description of the detection sub-circuit 210, storage sub-circuit 220, integrating sub-circuit 230, and control sub-circuit 240 also applies to the detection sub-circuit 410, storage sub-circuit 420, integrating sub-circuit 430, and control sub-circuit 440, and will not be repeated here.

[0096] like Figure 4 As shown, the photoelectric detection circuit 400 may also include a reset circuit 460.

[0097] The reset sub-circuit 460 can be connected to the reset signal terminal RST, the input node PD, and the reset voltage terminal V_RST. Under the control of the signal from the reset signal terminal RST, the reset sub-circuit 460 can provide the potential of the reset voltage terminal V_RST to the input node PD, wherein the potential of the reset voltage terminal V_RST is equal to the potential of the second input terminal V_R of the integrator circuit 430.

[0098] For example, the reset sub-circuit 460 may include a second transistor T2. The gate of the second transistor T2 is connected to the reset signal terminal RST, the first terminal of the second transistor T2 is connected to the reset voltage terminal V_RST, and the second terminal of the second transistor T2 is connected to the input node PD.

[0099] By setting the reset sub-circuit 460, the potential of the reset voltage terminal V_RST can be provided to the input node PD after the data reading is completed, thereby clearing the charge on the first capacitor C.

[0100] In some embodiments, the photoelectric detection circuit 400 may further include the aforementioned reset auxiliary sub-circuit 350 to further reduce hysteresis.

[0101] Figure 5 This is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure.

[0102] like Figure 5 As shown, the photoelectric detection circuit 500 includes a detection sub-circuit 510, a storage sub-circuit 520, an integrating sub-circuit 530, and a control sub-circuit 540. The above description of the detection sub-circuit 210, storage sub-circuit 220, integrating sub-circuit 230, and control sub-circuit 240 also applies to the detection sub-circuit 510, storage sub-circuit 520, integrating sub-circuit 530, and control sub-circuit 540, and will not be repeated here.

[0103] like Figure 5 As shown, the photoelectric detection circuit 500 may also include an amplification sub-circuit 570.

[0104] The amplification sub-circuit 570 is connected between the input node PD and the control sub-circuit 540, and is also connected to the reference voltage terminal V_D. The amplification sub-circuit 570 can generate a current Ids flowing between the reference signal terminal V_D and the control sub-circuit 540 under the control of the potential of the input node PD.

[0105] For example, the amplification sub-circuit 570 may include a third transistor T3. The gate of the third transistor T3 is connected to the input node PD, the first terminal of the third transistor T3 is connected to the reference voltage terminal V_D, and the second terminal of the third transistor T3 is connected to the control sub-circuit 540. For example, the second terminal of the third transistor T3 is connected to the first terminal of the fifth transistor T5 in the control sub-circuit 540.

[0106] By setting up the amplification sub-circuit 570, the current generated by the detection sub-circuit 510 can be amplified, for example, by a factor of 5-20. The current amplification at the first input terminal V_IN of the integrator sub-circuit 530 reduces the proportion of noise signals, thereby achieving noise reduction. In addition, the amplification sub-circuit 570 can also reset the input node PD. For example, during the reset phase, a low level can be applied to the detection voltage signal terminal V_S, and the bias voltage signal terminal V_B can be switched from the bias voltage (e.g., -4V) to the reference voltage (e.g., 1.4V), thereby turning on the fourth transistor T4 and providing the reference voltage to the input node PD, completing the reset of the input node PD. In some embodiments, a reset circuit (e.g., the reset circuit 460 described above) can be added to the photodetector circuit 500 to reset the input node PD. In this case, the voltage of the bias voltage signal terminal V_B does not need to be changed during the reset phase. This improves the anti-interference capability of the output signal.

[0107] Figure 6 This is a circuit diagram of a photoelectric detection circuit according to another embodiment of the present disclosure.

[0108] like Figure 6 As shown, the photoelectric detection circuit 600 includes a detection sub-circuit 610, a storage sub-circuit 620, an integrating sub-circuit 630, and a control sub-circuit 640. The above description of the detection sub-circuit 210, storage sub-circuit 220, integrating sub-circuit 230, and control sub-circuit 240 also applies to the detection sub-circuit 610, storage sub-circuit 620, integrating sub-circuit 630, and control sub-circuit 640, and will not be repeated here.

[0109] like Figure 6 As shown, the photoelectric detection circuit 600 may also include multiple detection sub-circuits, such as detection sub-circuit 611 and detection sub-circuit 612. The above description of detection sub-circuit 210 also applies to either detection sub-circuit 611 or detection sub-circuit 612.

[0110] In some embodiments, the detection sub-circuit 611 includes a fourth transistor T4, the gate of the fourth transistor T4 of the detection sub-circuit 611 is connected to the detection voltage signal terminal V_S, the first terminal of the fourth transistor T4 of the detection sub-circuit 611 is connected to the bias voltage signal terminal V_B, and the second terminal of the fourth transistor T4 of the detection sub-circuit 611 is connected to the input node PD.

[0111] The detection sub-circuit 612 also includes a fourth transistor T4, the second terminal of which is also connected to the input node PD.

[0112] It should be understood that Figure 6The number of detection sub-circuits shown in this disclosure is only one example, and more detection sub-circuits can be set as needed.

[0113] By providing embodiments of this disclosure, multiple detection sub-circuits are provided, which can increase the photocurrent.

[0114] While the photoelectric detection circuit has been described above with specific examples, the embodiments of this disclosure are not limited thereto. The above embodiments can be combined in any suitable manner as needed to form new photoelectric detection circuit structures. For example, the photoelectric detection circuit 200 may further include one or more of the reset auxiliary sub-circuit 350, reset sub-circuit 460, and amplification sub-circuit 570, and the number of detection sub-circuits 220 in the photoelectric detection circuit 200 can be arranged as follows: Figure 6 The method shown can be expanded as needed, for example, to two, three or more.

[0115] In the above embodiments, each transistor in the detection circuit, such as the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor, is a P-type transistor, such as a P-type TFT. However, the embodiments of this disclosure are not limited to this, and each transistor can be an N-type transistor.

[0116] Figure 7 This is a cross-sectional view of a photoelectric detection circuit according to an embodiment of the present disclosure. For ease of description, only the fourth transistor T4, the fifth transistor T5, and the first capacitor C in the above-described photoelectric detection circuit are shown.

[0117] like Figure 7 As shown, in, for example Figure 2 In the photoelectric detection circuit shown, the detection sub-circuit may include a fourth transistor T4, and the control sub-circuit may include a fifth transistor T5. The fourth transistor T4 and the fifth transistor T5 may be disposed on a substrate 701. The first electrode 7104 and the second electrode 7103 of the fourth transistor T4 are disposed on the same layer as the first electrode 7123 and the second electrode 7124 of the fifth transistor T5. The second electrode 7103 of the fourth transistor T4 is electrically connected to the first electrode 7123 of the fifth transistor T5. The active layer 7102 of the fourth transistor T4 is disposed on the same layer as the active layer 7122 of the fifth transistor T5. The gate 7101 of the fourth transistor T4 is disposed on the side of the active layer 7102 of the fourth transistor T4 facing the substrate 701, and the gate 7121 of the fifth transistor T5 is disposed on the side of the active layer 7122 of the fifth transistor T5 away from the substrate 701.

[0118] A planarization layer 708 is disposed on the side of the fourth transistor T4 and the fifth transistor T5 away from the substrate 701. The first electrode 7111 of the first capacitor C is located on the side of the planarization layer 708 away from the substrate 701, and the second electrode 7112 of the first capacitor C is located on the side of the planarization layer 708 facing the substrate 701.

[0119] In some embodiments, a first gate insulating layer 703 and a second gate insulating layer 704 are further disposed on the substrate 701. The active layer 7102 of the fourth transistor T4 and the active layer 7122 of the fifth transistor T5 are both located between the first gate insulating layer 703 and the substrate 701. The gate 7101 of the fourth transistor T4 is disposed on the side of the first gate insulating layer 703 facing the substrate 701. The gate 7121 of the fifth transistor T5 is disposed between the first gate insulating layer 703 and the second gate insulating layer 704.

[0120] In some embodiments, an interlayer dielectric layer 705 may be disposed on the side of the second gate insulating layer 704 facing away from the substrate 701. The first electrode 7104 and the second electrode 7103 of the fourth transistor T4, and the first electrode 7123 and the second electrode 7124 of the fifth transistor T5, may all be located on the side of the interlayer dielectric layer 705 facing away from the substrate 701. The first electrode 7104 and the second electrode 7103 of the fourth transistor T4 are in contact with the active layer 7101 through vias in the interlayer dielectric layer 705, the second gate insulating layer 704, and the first gate insulating layer 703. The first electrode 7123 and the second electrode 7124 of the fifth transistor T5 are in contact with the active layer 7122 through vias in the interlayer dielectric layer 705, the second gate insulating layer 704, and the first gate insulating layer 703.

[0121] In some embodiments, a first passivation layer 706 and a second passivation layer 707 may be disposed between the interlayer dielectric layer 705 and the planarization layer 708. The second passivation layer 707 is located between the first passivation layer 706 and the planarization layer 708. The second electrode 7112 of the first capacitor C is located between the second passivation layer 707 and the first passivation layer 706. In some embodiments, an encapsulation layer 709 may be disposed on the side of the planarization layer 708 facing away from the substrate 701. The first electrode 7111 of the first capacitor C may be located between the encapsulation layer 709 and the planarization layer 708. In some embodiments, the second electrode 7112 of the first capacitor C contacts the first electrode 7103 of the fourth transistor T4 and the second electrode 7123 of the fifth transistor T5 through vias in the first passivation layer 706, respectively.

[0122] In some embodiments, a barrier layer 702 may also be provided between the substrate 701 and the first gate insulating layer 702.

[0123] Figure 8AThis is a top view of a photoelectric detection circuit according to an embodiment of the present disclosure. For ease of description, only the fourth transistor T4, the fifth transistor T5, and the first capacitor C in the above-described photoelectric detection circuit are shown. Figure 8B This is a top view of a photoelectric detection circuit according to an embodiment of the present disclosure, wherein capacitor C has been removed to clearly show the structure of the fifth transistor T5.

[0124] like Figure 8A and Figure 8B As shown, the gate 7101 of the fourth transistor T4 is connected to the detection voltage signal terminal V_S, the first electrode of the fourth transistor T4 is connected to the bias voltage signal terminal V_B, and the second electrode of the fourth transistor T4 is connected to the first electrode of the fifth transistor T5. The gate of the fifth transistor T5 is connected to the control signal terminal GATE. The first electrode of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4. The second electrode of the fifth transistor T5 is connected to the first input terminal V_IN of the integrator circuit through a signal trace. The first electrode 7111 of the first capacitor C is connected to the bias voltage signal terminal V_S. The second electrode 7112 of the first capacitor C is connected to the input node PD.

[0125] Although the fourth transistor, the fifth transistor, and the first capacitor are shown in a specific layout in the above embodiments, the embodiments of this disclosure are not limited thereto, and the individual transistors in the detection circuit can be arranged in any other suitable layout as needed.

[0126] Figure 9 This is a cross-sectional view of a photoelectric detection circuit according to another embodiment of the present disclosure. Figure 9 The cross-sectional view can be applied to, for example, the photoelectric detection circuit 300 described above. Figure 9 As shown, the photoelectric detection circuit may further include a reset auxiliary sub-circuit, which may include a first transistor T1. For ease of description, only the fourth transistor T4, the fifth transistor T5, and the first transistor T1 are shown. Figure 9 The arrangement of components in the photoelectric detection circuit and Figure 7 Similarly, the difference lies at least in Figure 9 It also includes the first transistor T1. For the sake of simplicity, the following will mainly focus on the differences.

[0127] The first transistor T1 can be disposed on the substrate 701. The first electrode 7033 and the second electrode 7134 of the first transistor T1, the first electrode 7104 and the second electrode 7103 of the fourth transistor T4, and the first electrode 7123 and the second electrode 7124 of the fifth transistor T5 can be disposed on the same layer. The active layer 7132 of the first transistor T1, the active layer 7102 of the fourth transistor T4, and the active layer 7122 of the fifth transistor T5 are disposed on the same layer. The gate 7131 of the first transistor T1 is disposed on the side of the active layer 7132 of the first transistor T1 facing away from the substrate 701. The second electrode 7134 of the first transistor T1 is electrically connected to the first electrode 7104 of the fourth transistor T4.

[0128] Figure 10 This is a cross-sectional view of a photoelectric detection circuit according to another embodiment of the present disclosure. This cross-sectional view is applicable, for example, to the described electrical detection circuit 400. Figure 10 As shown, the detection circuit may also include a reset sub-circuit, which may include a second transistor T2. Figure 10 The arrangement of components in the photoelectric detection circuit and Figure 7 Similarly, the difference lies at least in Figure 10 It also includes a second transistor T2. For the sake of simplicity, the following will mainly focus on the differences.

[0129] The second transistor T2 can be disposed on the substrate 701. The first electrode 7143 and the second electrode 7144 of the second transistor T2, the first electrode 7104 and the second electrode 7103 of the fourth transistor T4, and the first electrode 7123 and the second electrode 7124 of the fifth transistor T5 can be disposed on the same layer. The active layer 7122 of the second transistor T2, the active layer 7102 of the fourth transistor T4, and the active layer 7122 of the fifth transistor T5 are disposed on the same layer. The gate 7141 of the second transistor T2 is disposed on the side of the active layer 7142 of the second transistor T2 facing away from the substrate 701.

[0130] In some embodiments, the second electrode 7144 of the second transistor T2 is electrically connected to the second electrode 7103 of the fourth transistor T4 and the first electrode 7123 of the fifth transistor T5, and the second electrode 7112 of the first capacitor C is in contact with the second electrode 7144 of the second transistor T2 through a via in the first passivation layer 706.

[0131] Figure 11 This is a cross-sectional view of a photoelectric detection circuit according to another embodiment of the present disclosure. This cross-sectional view is applicable, for example, to the described electrical detection circuit 400. Figure 11 As shown, the photoelectric detection circuit may also include an amplification sub-circuit, and the reset sub-circuit may include a third transistor T3. Figure 11 The arrangement of components in the photoelectric detection circuit and Figure 7 Similarly, the difference lies at least in Figure 11 It also includes a third transistor T3. For the sake of simplicity, the following will mainly focus on the differences.

[0132] The third transistor T3 can be disposed on the substrate 701. The first electrode 7153 and the second electrode 7154 of the third transistor T3, the first electrode 7104 and the second electrode 7103 of the fourth transistor T4, and the first electrode 7123 and the second electrode 7124 of the fifth transistor T5 can be disposed on the same layer. The active layer 7152 of the third transistor T3, the active layer 7102 of the fourth transistor T4, and the active layer 7122 of the fifth transistor T5 are disposed on the same layer. The gate 7151 of the third transistor T3 is disposed on the side of the active layer 7152 of the third transistor T3 facing away from the substrate 701.

[0133] In some embodiments, the second electrode 7154 of the third transistor T3 is electrically connected to the first electrode 7123 of the fifth transistor T5, and the second electrode 7112 of the first capacitor C is in contact with the gate 7151 of the third transistor T3 through a via in the first passivation layer 706, the interlayer dielectric layer 705, and the second gate insulating layer 704.

[0134] Figure 12 This is a cross-sectional view of a photoelectric detection circuit according to another embodiment of the present disclosure. This cross-sectional view is applicable, for example, to the photoelectric detection circuit 600 described above. Figure 12 As shown, the photoelectric detection circuit may include multiple detection sub-circuits, and each detection sub-circuit may include a fourth transistor T4. Figure 11 The arrangement of components in the photoelectric detection circuit and Figure 7 Similarly, the difference lies at least in Figure 12 There are multiple fourth transistors T4 in the middle. For the sake of simplicity, the following will mainly focus on the differences.

[0135] like Figure 12 As shown, the two fourth transistors T4 have the same layer structure and circuit connection. The description of the fourth transistor T4 in the above embodiments also applies to this embodiment. The second terminal 7104 of each fourth transistor T4 is electrically connected to the first terminal 7123 of the fifth transistor T5 and the second terminal 7112 of the first capacitor C.

[0136] In some embodiments, the second electrode 7112 of the first capacitor C is in contact with the second electrode 7104 of the plurality of fourth transistors T4 through a plurality of (two) vias of the first passivation layer 706.

[0137] Figure 13 This is a cross-sectional view of a pixel unit according to an embodiment of the present disclosure.

[0138] like Figure 13 As shown, the pixel unit 1300 includes at least one pixel circuit 1301 and a photoelectric detection circuit of any of the above embodiments. For simplicity, only the fourth transistor T4, the fifth transistor T5, and the first capacitor C1 in the photoelectric detection circuit are shown.

[0139] The pixel circuit 1300 may include a driving transistor, which may include a gate 1311, a source 1313, and a drain 1314. The driving transistor may also include an active layer 1312 located on a substrate 701, with the gate 1311 located on the side of the active layer 1312 away from the substrate 701. The driving transistor may also include a first gate insulating layer 703 located between the active layer 1312 and the gate 1311, a second gate insulating layer 704 located on the side of the gate 1311 away from the substrate 701, and an interlayer dielectric layer 705 located on the side of the second gate insulating layer 704 away from the substrate 701. The source 1313 and drain 1314 of the driving transistor are located on the side of the interlayer dielectric layer 705 away from the substrate 701.

[0140] In some embodiments, the pixel circuit further includes a light-emitting unit, which includes an anode 1315, a cathode 1316, and a light-emitting layer 1317 located between the anode 1315 and the cathode 1316. A planarization layer 708 is disposed on the side of the interlayer dielectric layer 705 away from the substrate 701. The anode 1315 is located on the side of the planarization layer 708 away from the substrate 701 and passes through the planarization layer 708 to connect to the source 1313 or drain 1314 of the driving transistor.

[0141] The detection sub-circuit of the photoelectric detection circuit includes a fourth transistor T4, and the control sub-circuit of the photoelectric detection circuit includes a fifth transistor T5. The gate 7101 of the fourth transistor T4 is located between the first gate insulating layer 703 and the substrate 701. The first electrode 7104 and the second electrode 7103 of the fourth transistor T4 are disposed on the same layer as at least one of the source electrode 1313 and the drain electrode 1314 of the driving transistor. The active layer 7102 of the fourth transistor T4 is disposed on the same layer as the active layer 1312 of the driving transistor. The gate 7121 of the fifth transistor T5 is disposed on the same layer as the gate 1311 of the driving transistor. The first electrode 7124 and the second electrode 7123 of the fifth transistor T5 are disposed on the same layer as at least one of the source electrode 1313 and the drain electrode 1314 of the driving transistor. The active layer 7122 of the fifth transistor T5 is disposed on the same layer as the active layer 1312 of the driving transistor.

[0142] The storage sub-circuit of the photoelectric detection circuit includes a first capacitor C. The first electrode 7111 of the first capacitor C is disposed on the same layer as the anode 1315 of the light-emitting unit, and the second electrode 7112 of the first capacitor C is located on the side of the planarization layer 708 facing the substrate 701.

[0143] In some embodiments, a first passivation layer 706 and a second passivation layer 707 are further disposed between the planarization layer 708 and the interlayer dielectric layer 705, wherein the source 1313 and the drain 1314 of the driving transistor are located between the first passivation layer 706 and the interlayer dielectric layer 705, and the second electrode 7112 of the first capacitor C is located between the second passivation layer 707 and the first passivation layer 706.

[0144] In some embodiments, an encapsulation layer 709 is provided on the side of the planarization layer 708 facing away from the substrate 701. The first electrode 7111 of the light-emitting unit and the first capacitor may be disposed between the encapsulation layer 709 and the planarization layer 708.

[0145] Figure 14 This is an operation timing diagram of a photoelectric detection circuit according to an embodiment of the present disclosure. The following will describe the operation of the photoelectric detection circuit 200 in conjunction with the above-described photoelectric detection circuit 200. Figure 14 The operation sequence will be explained. For example... Figure 14 As shown, a periodic signal is applied to the control signal terminal GATE, a constant voltage is applied to the detection voltage signal terminal V_S, for example, between -3V and -6V, and a constant voltage is applied to the bias voltage signal terminal V_B, for example, between -4V and -10V.

[0146] During time period t1, the control signal terminal GATE is at a high level, and the fifth transistor T5 is turned off, thereby electrically isolating the input node PD from the first input terminal V_IN. The potentials of the detection voltage signal terminal V_S and the bias voltage signal terminal V_B cause the fourth transistor T4 to be in reverse conduction, enabling it to generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to the light signal. The first capacitor C stores the charge generated by the fourth transistor T4.

[0147] During time period t2, the control signal terminal GATE is at a low level, turning on the fifth transistor T5, which in turn electrically connects the input node PD to the first input terminal V_IN. The fifth transistor T5 provides the potential of the input node PD to the first input terminal V_IN, thereby allowing the charge stored in the first capacitor C to be discharged into the capacitor in the downstream integrator circuit. The operational amplifier AMP in the integrator circuit generates an integrated signal based on the reference level of the second input terminal V_R and the signal at the first input terminal V_IN, and outputs it at the output terminal V_OUT.

[0148] Figure 15 This is a timing diagram of the operation of a photoelectric detection circuit according to another embodiment of this disclosure. The following will describe the operation of the photoelectric detection circuit 300 in conjunction with the above-described photoelectric detection circuit 300. Figure 15 The operation sequence will be explained. For example... Figure 15 As shown, each detection cycle includes a detection period and a reset period, wherein the detection period includes periods t11, t12 and t13.

[0149] During time period t11, the reset auxiliary signal terminal L_RST is low, the detection voltage signal terminal V_S is high, and the control signal terminal GATE is high. The low level of the reset auxiliary signal terminal L_RST turns on the first transistor T1, thereby providing the bias voltage of the bias voltage signal terminal V_B to the fourth transistor T4. The potentials of the detection voltage signal terminal V_S and the bias voltage signal terminal V_B cause the fourth transistor T4 to be in reverse conduction, causing it to generate charge in response to the light signal, thus generating a current flowing between the bias voltage signal terminal V_B and the input node PD. The first capacitor C stores the charge generated by the fourth transistor T4. The high level of the control signal terminal GATE turns off the fifth transistor T5, thereby electrically isolating the input node PD from the integrator circuit 330.

[0150] During time period t12, the reset auxiliary signal terminal L_RST is at a high level, turning off the first transistor T1. The presence of the first capacitor C keeps the first terminal of the fourth transistor T4 at the bias voltage. During this process, the potentials of the detection voltage signal terminal V_S and the bias voltage signal terminal V_B remain unchanged, allowing the fourth transistor T4 to continue responding to the light signal to generate charge and store it in the first capacitor C.

[0151] During time period t13, the control signal terminal GATE is at a low level, turning on the fifth transistor T5, which in turn electrically connects the input node PD to the first input terminal V_IN, thereby providing the potential of the input node PD to the first input terminal V_IN. The charge stored in the first capacitor C is discharged to the back-end integrator circuit, thereby generating an output signal at the output terminal V_OUT.

[0152] During the reset period, the reset auxiliary signal terminal L_RST is high, the detection voltage signal terminal V_S is low, and the control signal terminal GATE is low. The high level of the reset auxiliary signal terminal L_RST turns off the first transistor T1, thereby electrically isolating the fourth transistor T4 and the fifth transistor T5 from the bias voltage signal terminal V_B. The low level of the detection voltage signal terminal V_S turns on the fourth transistor T4, and the low level of the control signal terminal GATE turns on the fifth transistor T5, thus resetting the potential of the input node PD to the voltage of the second input terminal V_R.

[0153] Figure 16 This is a timing diagram of the operation of a photoelectric detection circuit according to another embodiment of this disclosure. The following will describe the operation of the photoelectric detection circuit 400 in conjunction with the above-described photoelectric detection circuit 400. Figure 15 The operation sequence will be explained.

[0154] During the detection period, the reset signal terminal RST is high, turning off the fifth transistor T5 and thus electrically isolating the input node PD from the first input terminal V_IN. The potentials of the detection voltage signal terminal V_S and the bias voltage signal terminal V_B cause the fourth transistor T4 to generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to the light signal. The first capacitor C stores the charge generated by the fourth transistor T4. When the control signal terminal GATE goes low, the fifth transistor T5 turns on, electrically connecting the input node PD to the first input terminal V_IN, thereby providing the potential of the input node PD to the first input terminal V_IN. The charge stored in the first capacitor C is discharged to the capacitor in the downstream integrator circuit, thus generating a low-level output signal at the output terminal V_OUT.

[0155] During the reset period, the reset signal terminal RST is at a low level, and the control signal terminal GATE is at a high level. The low level of the reset signal terminal RST turns on the second transistor T2, and the reset voltage terminal V_RST is electrically connected to the input node PD, thereby providing the potential of the reset voltage terminal V_RST to the input node PD to achieve the reset of the input node PD.

[0156] Figure 17 This is a timing diagram of the operation of a photoelectric detection circuit according to another embodiment of this disclosure. The following will describe the operation of the photoelectric detection circuit 500 in conjunction with the above-described photoelectric detection circuit 500. Figure 16 The operation sequence will be explained.

[0157] During the detection period, the potentials of the bias voltage signal terminal V_B and the detection voltage signal terminal V_S cause the fourth transistor T4 to generate a current flowing between the bias voltage signal terminal V_B and the input node PD in response to the light signal. The first capacitor C stores the charge generated by the fourth transistor T4. When the control signal terminal GATE goes low, the fifth transistor T5 turns on, electrically connecting the input node PD to the first input terminal V_IN, thereby providing the potential of the input node PD to the first input terminal V_IN. The charge stored in the first capacitor C is discharged to the capacitor in the downstream integrator circuit, thus generating the output signal at the output terminal V_OUT.

[0158] During the reset period, the detection voltage signal terminal V_S is at a low level, and the potential of the bias voltage signal terminal V_B can change from the potential during the detection period (e.g., -4V) to the reference voltage, for example, it can be equal to the reference voltage at the second input terminal V_R of the integrator circuit, i.e., 1.4V. The potentials of the bias voltage signal terminal V_B and the detection voltage signal terminal V_S cause the fourth transistor T4 to be forward-biased, thereby providing the reference voltage of the bias voltage signal terminal V_B to the input node PD, completing the reset of the input node PD.

[0159] In some embodiments, the operating timing of the photoelectric detection circuit 600 is similar to that of the photoelectric detection circuit 200, and can be referred to the foregoing description. Figure 14 The operation sequence will not be elaborated here.

[0160] Figure 18 This is a flowchart of a control method for a photoelectric detection circuit according to an embodiment of the present disclosure.

[0161] The control method 1800 may include operations S1801 to S1804.

[0162] In operation S1801, the detection sub-circuit responds to the optical signal to generate a current flowing between the bias voltage signal terminal and the input node.

[0163] In operation 1802, the storage sub-circuit stores energy based on the current generated by the detection sub-circuit.

[0164] In operation 1803, the control sub-circuit, under the control of the control signal terminal, provides the potential of the input node to the first input terminal of the integrator circuit.

[0165] In operation 1804, the integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal, which is then output at the output terminal.

[0166] In some embodiments, the photoelectric detection circuit further includes a reset auxiliary sub-circuit, and the method includes a detection period and a reset period.

[0167] During the detection period, the reset auxiliary sub-circuit, under the control of the reset auxiliary signal terminal, electrically connects the detection sub-circuit to the bias voltage signal terminal. The detection sub-circuit responds to the optical signal to generate a current flowing between the bias voltage signal terminal and the input node. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. Under the control of the control signal terminal, the control sub-circuit provides the potential of the input node to the first input terminal of the integrator circuit. The integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal.

[0168] During the reset period, the reset auxiliary sub-circuit electrically isolates the detection sub-circuit from the bias voltage signal terminal under the control of the reset auxiliary signal terminal. The detection sub-circuit electrically connects the bias voltage signal terminal to the input node under the control of the potential of the detection voltage signal terminal. The control sub-circuit electrically connects the input node to the first input terminal of the integrator circuit under the control of the control signal terminal.

[0169] In some embodiments, the photoelectric detection circuit further includes a reset sub-circuit, and the method includes a detection period and a reset period.

[0170] During the detection period, the reset sub-circuit electrically isolates the reset voltage terminal from the input node under the control of the reset signal terminal. The detection sub-circuit generates a current flowing between the bias voltage signal terminal and the input node in response to the optical signal. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. Under the control of the control signal terminal, the control sub-circuit provides the potential of the input node to the first input terminal of the integrator circuit. The integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal.

[0171] During the reset period, the reset sub-circuit connects the reset voltage terminal to the input node under the control of the reset signal terminal, and the control sub-circuit electrically isolates the input node from the first input terminal of the integrator circuit under the control of the control signal terminal.

[0172] In some embodiments, the photoelectric detection circuit further includes an amplification sub-circuit, and the method includes a detection period and a reset period.

[0173] During the detection period, the detection sub-circuit, under the control of the potential at the detection voltage signal terminal, responds to the optical signal to generate a current flowing between the bias voltage signal terminal and the input node. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. The amplification sub-circuit, under the control of the potential at the input node, generates a current flowing between the reference signal terminal and the control sub-circuit. Under the control of the control signal terminal, the control sub-circuit provides the current generated by the amplification sub-circuit to the first input terminal of the integrator circuit. The integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal, which is then output at the output terminal.

[0174] During the reset period, the detection sub-circuit connects the bias voltage signal terminal to the input node under the control of the potential of the detection voltage signal terminal. The potential of the bias voltage signal terminal during the reset period is different from the potential during the detection period.

[0175] It should be noted that the technical solutions of the embodiments of this disclosure are shown by way of example only in the above description, and do not mean that the embodiments of this disclosure are limited to the above steps and structures. Where possible, the steps and structures can be adjusted and omitted as needed. Therefore, some steps and units are not essential elements for implementing the overall inventive concept of the embodiments of this disclosure.

[0176] The present disclosure has now been described in conjunction with preferred embodiments. It should be understood that those skilled in the art can make various other changes, substitutions, and additions without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of the embodiments of the present disclosure is not limited to the specific embodiments described above, but should be defined by the appended claims.

Claims

1. A photoelectric detection circuit, comprising: The detection sub-circuit connects the detection voltage signal terminal, the bias voltage signal terminal, and the input node, and is configured to generate a current flowing between the bias voltage signal terminal and the input node in response to a light signal under the control of the potential of the detection voltage signal terminal. A storage subcircuit is connected between the bias voltage signal terminal and the input node and is configured to store energy based on the current generated by the detection subcircuit. An integrator circuit has a first input terminal, a second input terminal, and an output terminal, and is configured to integrate the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal; A control subcircuit is connected to a control signal terminal, an input node, and a first input terminal of the integrator subcircuit, and is configured to provide the potential of the input node to the first input terminal of the integrator subcircuit under the control of the control signal terminal.

2. The photoelectric detection circuit according to claim 1, wherein, The storage sub-circuit includes a first capacitor, the first electrode of which is connected to the bias voltage signal terminal, and the second electrode of which is connected to the input node.

3. The photoelectric detection circuit according to claim 1 further includes: A reset auxiliary sub-circuit is provided, wherein the detection sub-circuit is connected to the bias voltage signal terminal through the reset auxiliary sub-circuit. The reset auxiliary sub-circuit is configured to electrically connect the detection sub-circuit to the bias voltage signal terminal during the detection period under the control of the reset auxiliary signal terminal, and electrically isolate the detection sub-circuit from the bias voltage signal terminal during the reset period.

4. The photoelectric detection circuit according to claim 3, wherein, The reset auxiliary sub-circuit includes a first transistor, the gate of which is connected to the reset auxiliary signal terminal, the first terminal of which is connected to the bias voltage signal terminal, and the second terminal of which is connected to the detection sub-circuit.

5. The photoelectric detection circuit according to any one of claims 1, further comprising: A reset sub-circuit is connected to a reset signal terminal, the input node, and a reset voltage terminal, and is configured to provide the potential of the reset voltage terminal to the input node under the control of a signal from the reset signal terminal, wherein the potential of the reset voltage terminal is equal to the potential of the second input terminal of the integrator sub-circuit.

6. The photoelectric detection circuit according to claim 5, wherein, The reset sub-circuit includes a second transistor, the gate of which is connected to the reset signal terminal, the first terminal of which is connected to the reset voltage terminal, and the second terminal of which is connected to the input node.

7. The photoelectric detection circuit according to claim 1 further includes an amplification sub-circuit connected between the input node and the control sub-circuit, and connected to a reference voltage terminal, the amplification sub-circuit being configured to generate a current flowing between the reference voltage terminal and the control sub-circuit under the control of the potential of the input node.

8. The photoelectric detection circuit according to claim 7, wherein, The amplification sub-circuit includes a third transistor, the gate of which is connected to the input node, the first terminal of which is connected to the reference voltage terminal, and the second terminal of which is connected to the control sub-circuit.

9. The photoelectric detection circuit according to any one of claims 1 to 8, wherein, The detection sub-circuit includes a fourth transistor, the gate of which is connected to the detection voltage signal terminal, the first terminal of which is connected to the bias voltage signal terminal, and the second terminal of which is connected to the input node.

10. The photoelectric detection circuit according to any one of claims 1 to 8, comprising a plurality of the detection sub-circuits.

11. The photoelectric detection circuit according to any one of claims 1 to 8, wherein, The control sub-circuit includes a fifth transistor, the gate of which is connected to the control signal terminal, the first terminal of which is connected to the input node, and the second terminal of which is connected to the first input terminal of the integrator sub-circuit.

12. The photoelectric detection circuit according to any one of claims 1 to 8, wherein, The integrator circuit includes: An operational amplifier, wherein the first input terminal of the operational amplifier is connected to the first input terminal of the integrator circuit, the second input terminal of the operational amplifier is connected to the second input terminal of the integrator circuit, and the output terminal of the operational amplifier is connected to the output terminal of the integrator circuit; The second capacitor has its first electrode connected to the first input terminal of the operational amplifier, and its second electrode connected to the second input terminal of the operational amplifier.

13. The photoelectric detection circuit according to any one of claims 1 to 8, wherein, The detection sub-circuit includes a fourth transistor, and the control sub-circuit includes a fifth transistor. The fourth and fifth transistors are disposed on a substrate. The first and second terminals of the fourth transistor are disposed on the same layer as the first and second terminals of the fifth transistor. The active layer of the fourth transistor is disposed on the same layer as the active layer of the fifth transistor. The gate of the fourth transistor is disposed on the side of the active layer of the fourth transistor facing the substrate, and the gate of the fifth transistor is disposed on the side of the active layer of the fifth transistor away from the substrate.

14. The photoelectric detection circuit according to claim 13, wherein, The storage sub-circuit includes a first capacitor, and a planarization layer is disposed on the side of the fourth transistor and the fifth transistor away from the substrate. The first electrode of the first capacitor is located on the side of the planarization layer away from the substrate, and the second electrode of the first capacitor is located on the side of the planarization layer facing the substrate.

15. A pixel unit, comprising: At least one pixel circuit, each pixel circuit being configured to emit light based on a data voltage; as well as The photoelectric detection circuit according to any one of claims 1 to 14.

16. The pixel unit according to claim 15, wherein, The pixel circuit includes a driving transistor, which includes an active layer on a substrate, a gate on the side of the active layer away from the substrate, a first gate insulating layer between the active layer and the gate, a second gate insulating layer on the side of the gate away from the substrate, an interlayer dielectric layer on the side of the second gate insulating layer away from the substrate, and a source and a drain on the side of the interlayer dielectric layer away from the substrate. The detection sub-circuit of the photoelectric detection circuit includes a fourth transistor, and the control sub-circuit of the photoelectric detection circuit includes a fifth transistor. The gate of the fourth transistor is located between the first gate insulating layer and the substrate. The first and second terminals of the fourth transistor are disposed on the same layer as at least one of the source and drain terminals of the driving transistor. The active layer of the fourth transistor is disposed on the same layer as the active layer of the driving transistor. The gate of the fifth transistor is disposed on the same layer as the gate of the driving transistor. The first and second terminals of the fifth transistor are disposed on the same layer as at least one of the source and drain terminals of the driving transistor. The active layer of the fifth transistor is disposed on the same layer as the active layer of the driving transistor.

17. The pixel unit according to claim 16, wherein, The pixel circuit further includes a light-emitting unit, which includes an anode, a cathode, and a light-emitting layer located between the anode and the cathode. A planarization layer is disposed on the side of the interlayer dielectric layer away from the substrate. The anode is located on the side of the planarization layer away from the substrate and passes through the planarization layer to be connected to the source or drain of the driving transistor. The storage sub-circuit of the photoelectric detection circuit includes a first capacitor, the first electrode of the first capacitor is disposed on the same layer as the anode, and the second electrode of the first capacitor is located on the side of the planar surface facing the substrate.

18. The pixel unit according to claim 17, wherein, A first passivation layer and a second passivation layer are further disposed between the planarization layer and the interlayer dielectric layer, wherein the source and drain of the driving transistor are located between the first passivation layer and the interlayer dielectric layer, and the second electrode of the first capacitor is located between the second passivation layer and the first passivation layer.

19. A control method for a photoelectric detection circuit as described in any one of claims 1 to 14, comprising: The detection sub-circuit responds to the optical signal to generate a current flowing between the bias voltage signal terminal and the input node; The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. Under the control of the control signal terminal, the control sub-circuit provides the potential of the input node to the first input terminal of the integrator sub-circuit; The integrator circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal, which is then output at the output terminal.

20. The method according to claim 19, wherein, The photoelectric detection circuit further includes a reset auxiliary sub-circuit, and the method includes: During the detection period, the reset auxiliary sub-circuit, under the control of the reset auxiliary signal terminal, electrically connects the detection sub-circuit to the bias voltage signal terminal. The detection sub-circuit generates a current flowing between the bias voltage signal terminal and the input node in response to the optical signal. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. Under the control of the control signal terminal, the control sub-circuit provides the potential of the input node to the first input terminal of the integrating sub-circuit. The integrating sub-circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal. During the reset period, the reset auxiliary sub-circuit electrically isolates the detection sub-circuit from the bias voltage signal terminal under the control of the reset auxiliary signal terminal. The detection sub-circuit electrically connects the bias voltage signal terminal to the input node under the control of the potential of the detection voltage signal terminal. The control sub-circuit electrically connects the input node to the first input terminal of the integrator sub-circuit under the control of the control signal terminal.

21. The method according to claim 19, wherein, The photoelectric detection circuit further includes a reset sub-circuit, and the method includes: During the detection period, the reset sub-circuit electrically isolates the reset voltage terminal from the input node under the control of the reset signal terminal. The detection sub-circuit generates a current flowing between the bias voltage signal terminal and the input node in response to the optical signal. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. The control sub-circuit provides the potential of the input node to the first input terminal of the integrator under the control of the control signal terminal. The integrator integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal. During the reset period, the reset sub-circuit connects the reset voltage terminal to the input node under the control of the reset signal terminal, and the control sub-circuit electrically isolates the input node from the first input terminal of the integrator sub-circuit under the control of the control signal terminal.

22. The method according to claim 19, wherein, The photoelectric detection circuit further includes an amplification sub-circuit, and the method includes: During the detection period, the detection sub-circuit, under the control of the potential at the detection voltage signal terminal, responds to the optical signal to generate a current flowing between the bias voltage signal terminal and the input node. The storage sub-circuit stores energy based on the current generated by the detection sub-circuit. The amplification sub-circuit, under the control of the potential at the input node, generates a current flowing between the reference voltage terminal and the control sub-circuit. Under the control of the control signal terminal, the control sub-circuit provides the current generated by the amplification sub-circuit to the first input terminal of the integrator sub-circuit. The integrator sub-circuit integrates the signal at the first input terminal based on the potential at the second input terminal to generate an integrated signal and output it at the output terminal. During the reset period, the detection sub-circuit electrically connects the bias voltage signal terminal to the input node under the control of the potential of the detection voltage signal terminal, wherein the potential of the bias voltage signal terminal during the reset period is different from the potential during the detection phase.

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