A high-precision self-calibration magnetic switch chip

Abstract

The application discloses a high-precision self-calibration magnetic switch chip, which is used for improving the precision of chip magnetic field detection work. The application comprises the following steps: VCC pins are connected with a band gap reference and current bias module and a debugging calibration module respectively; the band gap reference and current bias module are connected with a power supply voltage module and a reference voltage module respectively; a digital module is connected with the debugging calibration module and the reference voltage module VREF_COMP respectively; a Wheatstone bridge is connected with the power supply voltage module, a GND pin and a low-offset comparator; the low-offset comparator is connected with the reference voltage module, the digital module and a first transistor NMOS; the first transistor NMOS is connected with the GND pin and an OUT pin; a multiplexing output module is connected with the digital module, the debugging calibration module and the OUT pin; the debugging calibration module is connected with the OUT pin and a Test pin.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the field of magnetic sensor, in particular to a high-precision self-calibration magnetic switch chip. BACKGROUND

[0002] The magnetic sensor is a kind of electronic device for converting magnetic field into corresponding electric signal, and the magnetic switch belongs to an important kind of magnetic sensor, which is a kind of component controlled by magnetic signal. The magnetic signal has strong penetrating power, and can easily penetrate common obstacles such as plastic, metal, wood, rock and other non-magnetic materials, and realize complete signal transmission, and is not affected by dust, oil stains, smoke, background light in the environment. The magnetic sensor is widely used in various non-contact control systems due to its unique advantages, and is applied to many fields such as military defense, medical electronics, industrial control and consumer electronics.

[0003] At present, the magnetic switch can be divided into two categories: one is the traditional non-integrated magnetic switch represented by dry reed and electromagnetic induction coil, and the other is the integrated magnetic switch developed by combining the magnetic sensitive element represented by Hall effect device and magnetoresistance effect device with microelectronic technology. The traditional non-integrated magnetic switch is gradually replaced by the integrated magnetic switch due to its disadvantages such as large size, short service life and low sensitivity. The present application mainly describes the integrated magnetic switch. For a completely ideal magnetic sensitive element, the magnetic induction voltage of the Wheatstone bridge is 0 under zero magnetic field. However, in actual situation, due to problems such as mismatching of contact holes, uneven doping concentration injection, material anisotropy, geometric structure asymmetry and packaging stress in the manufacturing process of the magnetic sensitive element, the magnetic sensitive element will be mismatched, resulting in the generation of offset voltage. That is, when the external magnetic field intensity is 0, the magnetic induction voltage is not 0, but there is an offset voltage Vos. The offset voltage Vos generated by the Wheatstone bridge composed of actual magnetic sensitive elements is generally between several millivolts and tens of millivolts, which is in the same order of magnitude as the magnetic induction voltage. Compared with the magnetic induction voltage related to the external magnetic field intensity, the offset voltage Vos is not proportional to the magnetic field size, and it is difficult to predict the accurate value. If the magnetic induction voltage and the offset voltage cannot be separated, the interface circuit will be difficult to identify, resulting in deviation of the result, and the chip magnetic field detection precision and reliability will be greatly affected. At this time, the offset voltage needs to be eliminated to ensure the precision and reliability of the chip magnetic field detection.

[0004] At present, the following several technologies are used to eliminate the offset voltage in the industry: double Wheatstone bridge offset technology, 4 Wheatstone bridge offset elimination technology and rotating current offset elimination technology. The present application mainly points out the defects of the double Wheatstone bridge offset technology and the 4 Wheatstone bridge offset elimination technology.

[0005] The magnetosensitive element integrated in the Wheatstone bridge can be a Hall, AMR, GMR or TMR magnetoresistance. The Hall, AMR, GMR or TMR magnetoresistance will change its own characteristics with the change of the external temperature, thereby affecting the magnetic induction voltage output of the Wheatstone bridge. The stability of the chip working in a wide temperature range will be reduced, thereby reducing the accuracy of the entire chip magnetic field detection. SUMMARY

[0006] The application discloses a high-precision self-calibration magnetic switch chip for improving the accuracy of chip magnetic field detection.

[0007] The first aspect of the application provides a high-precision self-calibration magnetic switch chip, comprising:

[0008] The Wheatstone bridge, the power supply voltage module Regulator, the bandgap reference and current bias module BG&Ibias, the low-offset comparator COMP, the reference voltage module VREF_COMP, the digital module Digital TOP, the debugging and calibration module Debug DUT&Cali, the multiplexing output module MUX and the first transistor NMOS.

[0009] The VCC pin is connected with the bandgap reference and current bias module BG&Ibias and the debugging and calibration module Debug DUT&Cali respectively;

[0010] The bandgap reference and current bias module BG&Ibias is connected with the power supply voltage module Regulator and the reference voltage module VREF_COMP respectively;

[0011] The digital module Digital TOP is connected with the debugging and calibration module Debug DUT&Cali and the reference voltage module VREF_COMP respectively;

[0012] The Wheatstone bridge is connected with the power supply voltage module Regulator, the GND pin and the low-offset comparator COMP respectively;

[0013] The low-offset comparator COMP is connected with the reference voltage module VREF_COMP, the digital module Digital TOP and the first transistor NMOS respectively;

[0014] The first transistor NMOS is connected with the GND pin and the OUT pin respectively;

[0015] The multiplexing output module MUX is connected with the digital module Digital TOP, the debugging and calibration module Debug DUT&Cali and the OUT pin respectively;

[0016] Debug DUT&Cali is connected with OUT pin and Test pin respectively.

[0017] Optionally, the reference voltage module VREF_COMP comprises a zero-temperature coefficient current module, a positive-temperature coefficient current module, a zero-temperature coefficient resistor R5, a PNP transistor, a buffer A1, a buffer A2, a second transistor NMOS, a third transistor NMOS, a resistor R6, a reference voltage VREF output, a resistor RREF and a 7-bit current steering type DAC;

[0018] The zero-temperature coefficient current module and the positive-temperature coefficient current module are connected with the first end of the zero-temperature coefficient resistor R5.

[0019] The first end of the zero-temperature coefficient resistor R5 is connected with the negative electrode of the buffer A1, and the second end of the zero-temperature coefficient resistor R5 is connected with the emitter of the PNP transistor.

[0020] The base and the collector of the PNP transistor are grounded.

[0021] The first end of the resistor R6 is connected with the positive electrode of the buffer A1 and the second transistor NMOS respectively, and the second end of the resistor R6 is grounded.

[0022] The output of the buffer A1 is connected with the second transistor NMOS and the third transistor NMOS respectively.

[0023] The second transistor NMOS and the third transistor NMOS are further connected with a power supply.

[0024] The reference voltage VREF output is divided into a reference voltage VREFN and a reference voltage VREFP, the reference voltage VREFP is connected with the third transistor NMOS, the first end of the resistor RREF and the 7-bit current steering type DAC respectively.

[0025] The reference voltage VREFN is connected with the second end of the resistor RREF, the output and the negative electrode of the buffer A2 respectively.

[0026] The positive electrode of the buffer A2 is connected with the voltage VBG_div.

[0027] Optionally, the Wheatstone bridge is composed of a magnetic sensitive element R1, a magnetic sensitive element R2, a magnetic sensitive element R3 and a magnetic sensitive element R4.

[0028] The magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R4 and the magnetic sensitive element R3 are sequentially connected to form the bridge.

[0029] Optionally, the interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R2 are connected with a low-offset comparator COMP.

[0030] The interfaces of the magnetic sensitive element R3 and the magnetic sensitive element R4 are connected with the low-offset comparator COMP;

[0031] The interfaces of the magnetic sensitive element R2 and the magnetic sensitive element R4 are connected with the GND pin;

[0032] The interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R2 are connected with the power supply voltage module Regulator.

[0033] Optionally, the magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3 and the magnetic sensitive element R4 are Hall magnetoresistance, AMR magnetoresistance, GMR magnetoresistance or TMR magnetoresistance.

[0034] Optionally, the low-offset comparator COMP comprises a first switch pair RST, a second switch pair RST, a switch pair Φ1, a switch pair Φ1d, a switch pair Φ2, a sampling capacitor CA / CB, a first-stage offset storage capacitor C1A / C1B, a second-stage offset storage capacitor C2A / C2B, a first-stage preamplifier A3, a second-stage preamplifier A4, a dynamic latch comparator Latch and a D flip-flop DFF;

[0035] The switch pair Φ2 is connected with the sampling capacitor CA / CB;

[0036] The switch pair Φ1d is connected with the sampling capacitor CA / CB;

[0037] The sampling capacitor CA / CB is respectively connected with the switch pair Φ1 and the first-stage preamplifier A3;

[0038] The first-stage offset storage capacitor C1A / C1B is respectively connected with the first-stage preamplifier A3, the second-stage preamplifier A4 and the first switch pair RST;

[0039] The second-stage offset storage capacitor C2A / C2B is respectively connected with the second-stage preamplifier A4, the second switch pair RST and the dynamic latch comparator Latch;

[0040] The dynamic latch comparator Latch is connected with the D flip-flop DFF.

[0041] Optionally, the switch pair Φ2 is connected with the Wheatstone bridge;

[0042] The switch pair Φ1d is connected with the reference voltage module VREF_COMP.

[0043] Optionally, the high-precision self-calibration magnetic switch chip further comprises a low-power clock OSC;

[0044] The low-power clock OSC is respectively connected with the VCC pin and the bandgap reference and current bias module BG&Ibias.

[0045] Optionally, the high-precision self-calibration magnetic switch chip further comprises a Timer module which is a timer.

[0046] The Timer module is connected with a low-power clock OSC.

[0047] Optionally, the high-precision self-calibration magnetic switch chip further comprises an under-voltage protection and over-temperature protection module UVLO&OTP.

[0048] The under-voltage protection and over-temperature protection module UVLO&OTP is connected with a VCC pin, a bandgap reference and current bias module BG&Ibias, and a digital module Digital TOP respectively.

[0049] From the above technical solutions, the present application has the following advantages:

[0050] In the present application, the high-precision self-calibration magnetic switch chip comprises a Wheatstone bridge, a power supply voltage module Regulator, a bandgap reference and current bias module BG&Ibias, a low-offset comparator COMP, a reference voltage module VREF_COMP, a digital module Digital TOP, a debugging and calibration module Debug DUT&Cali, a multiplexing output module MUX, and a first transistor NMOS. The connection modes are as follows: the VCC pin is connected with the bandgap reference and current bias module BG&Ibias and the debugging and calibration module Debug DUT&Cali respectively. The bandgap reference and current bias module BG&Ibias is connected with the power supply voltage module Regulator and the reference voltage module VREF_COMP respectively. The digital module Digital TOP is connected with the debugging and calibration module Debug DUT&Cali and the reference voltage module VREF_COMP respectively. The Wheatstone bridge is connected with the power supply voltage module Regulator, a GND pin, and the low-offset comparator COMP respectively. The low-offset comparator COMP is connected with the reference voltage module VREF_COMP, the digital module Digital TOP, and the first transistor NMOS respectively. The first transistor NMOS is connected with the GND pin and an OUT pin respectively. The multiplexing output module MUX is connected with the digital module Digital TOP, the debugging and calibration module Debug DUT&Cali, and the OUT pin respectively. The debugging and calibration module Debug DUT&Cali is connected with the OUT pin and a Test pin respectively.

[0051] Wherein, the bandgap reference and current bias module BG&Ibias provides the required bias voltage and bias current for the self-calibration magnetic switch chip in the application. The power supply voltage module Regulator supplies power for the Wheatstone bridge. The reference voltage module VREF_COMP provides voltage VREF and Vcm for the low-offset comparator COMP, wherein VREF is the reference voltage for comparison with the VIN induced by the Wheatstone bridge, and Vcm is the common-mode potential of the low-offset comparator COMP. The digital module Digital Top processes the digital functions of the entire self-calibration magnetic switch chip, including sending and receiving the trimming code value, the VREF calibration code value, etc. The debugging and calibration module Debug DUT&cali functions to realize the debug function and undertake the external calibration function, that is, in addition to the automatic calibration of the self-calibration magnetic switch chip, the calibration code can also be manually input according to the multiplexing result to manually configure. The multiplexing module MUX multiplexes the important signals in the debug mode. When the magnetic sensitive element integrated in the Wheatstone bridge changes its own characteristics with the change of the external temperature, thereby affecting the magnetic induction voltage output of the Wheatstone bridge, the reference voltage module VREF_COMP is used to calibrate the magnetic induction voltage output, and the high-precision self-calibration magnetic switch chip integrates a low-offset comparator COMP based on the automatic zero (AZ) technology, and has the functions of magnetic bridge offset automatic calibration and temperature compensation, realizes high-precision detection of the external magnetic field at full temperature (-40-125℃), and finally stabilizes the magnetic induction voltage output of the Wheatstone bridge in the chip, and improves the precision of the entire self-calibration magnetic switch chip in the external magnetic field detection. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0053] Figure 1 It is a chip system architecture schematic diagram of the high-precision self-calibration magnetic switch chip in the present application.

[0054] Figure 2 It is another chip system architecture schematic diagram of the high-precision self-calibration magnetic switch chip in the present application.

[0055] Figure 3 It is a circuit structure schematic diagram of the reference voltage module VREF_COMP of the high-precision self-calibration magnetic switch chip in the present application.

[0056] Figure 4A circuit structure diagram of a low-offset comparator COMP of a high-precision self-calibration magnetic switch chip in the present application;

[0057] Figure 5 A switch control timing diagram of a low-offset comparator COMP of a high-precision self-calibration magnetic switch chip in the present application. DETAILED DESCRIPTION

[0058] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0059] It is to be understood that the terminology "includes", "has", "holds", "contains" or "comprising", "comprised of", "comprising", or grammatical variants thereof when used in this specification and / or the appended claims, specifies the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0060] It is also to be understood that the terminology "and / or" when used in this specification and / or the appended claims, that the conjunction of the associated listed items, means any combination of one or more of the associated listed items and all possible combinations thereof.

[0061] As used in this specification and the appended claims, the term "if" can be interpreted as meaning "when", or "once", or "in response to a determination", or "in response to detecting", as appropriate, depending on the context. Similarly, the phrase "if determined", or "if detected [the described condition or event]" can be interpreted as meaning "once determined", or "in response to a determination", or "upon detecting [the described condition or event]", or "in response to detecting [the described condition or event]", as appropriate, depending on the context.

[0062] In addition, in the description of the present application and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0063] Reference to "one embodiment" or "some embodiments" or "one implementation" or "some implementations" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" or "in some embodiments" or "in other embodiments" or "in still other embodiments" or other similar phrases in the specification are not necessarily all referring to the same embodiment.

[0064] In the prior art, for a Wheatstone bridge composed of completely ideal magnetic sensitive elements, the magnetic induction voltage is 0 at zero magnetic field. However, in actual situations, due to problems such as mismatched contact holes, uneven doping concentration injection, material anisotropy, geometric structure asymmetry, packaging stress, etc. in the manufacturing process of the magnetic sensitive elements, the magnetic sensitive elements will be mismatched, resulting in the generation of an offset voltage. That is, when the external magnetic field strength is 0, the magnetic induction voltage is not 0, but there is an offset voltage Vos. The offset voltage Vos generated by a Wheatstone bridge composed of actual magnetic sensitive elements is generally between several millivolts and tens of millivolts, which is in the same order of magnitude as the magnetic induction voltage. Compared with the magnetic induction voltage related to the external magnetic field strength, the offset voltage Vos is not proportional to the magnetic field size and it is difficult to predict its accurate value. If the magnetic induction voltage and the offset voltage cannot be separated, the interface circuit will be difficult to identify, resulting in deviation of the result, and the chip magnetic field detection accuracy and reliability will be greatly affected. At this time, it is necessary to eliminate the offset voltage to ensure the accuracy and reliability of the chip magnetic field detection.

[0065] Currently, there are the following three kinds of technologies to eliminate the offset voltage in the industry: double Wheatstone bridge offset technology, 4 Wheatstone bridge offset elimination technology, and rotating current offset elimination technology. However, each has its own shortcomings:

[0066] (1) The double Wheatstone bridge offset technology is difficult to manufacture two bridges with completely identical parameters due to process limitations, so it cannot guarantee that the two bridges generate the same magnetic induction voltage and offset voltage, and the offset elimination effect is not obvious.

[0067] (2) The 4 Wheatstone bridge offset elimination technology can reduce the offset voltage by 10 to 25 times, but the Wheatstone bridge used must have completely identical parameters, which is extremely strict for the manufacturing process. In addition, the use of multiple Wheatstone bridges will sacrifice more layout area and increase the cost of the chip.

[0068] (3) Rotating current offset cancellation technique is similar to chopper technique, and has transient spikes due to switching charge injection, clock feedthrough, etc. Therefore, the dynamic offset cancellation technique is not ideal, and usually has a residual offset of 1 mT (10 Gs). The use of multi-phase rotating current technique can improve the offset voltage cancellation efficiency and accuracy, but at the same time, the circuit complexity is increased, which limits the processing speed of the sensor chip, and the circuit complexity, area and cost are also increased.

[0069] The present application mainly aims at the defects of double Wheatstone bridge offset technique and 4 Wheatstone bridge offset cancellation technique.

[0070] The magnetically sensitive element integrated in the Wheatstone bridge can be a Hall, AMR, GMR or TMR magnetoresistance. These four kinds of magnetically sensitive elements have their own characteristics.

[0071] (1) The device essence of Hall element is a Hall sheet with N-well as the sensing material. The N-type semiconductor material is affected by carrier concentration, resistivity and mobility, and its characteristics will have temperature drift phenomenon in a wide temperature range.

[0072] (2) The device essence of AMR element and GMR element is a magnetic thin film material, and its temperature characteristics mainly reflect in lattice thermal vibration and inelastic scattering: with the increase of temperature, the lattice thermal vibration and inelastic scattering are enhanced, the effective path of conduction electrons is increased, the probability of scattering is increased, and the external performance is that the resistance value is increased.

[0073] (3) The temperature characteristics of TMR element are better than those of Hall element, AMR element and GMR element. However, to realize a high-sensitivity TMR element, the commonly used method is to connect multiple magnetic tunnel junctions in series to increase the cross-sectional area, which results in more serious process deviation and deteriorates the temperature characteristics of TMR element.

[0074] Hall, AMR, GMR or TMR magnetoresistance will change its own characteristics with the change of external temperature, which will further affect the magnetic induction voltage output of the Wheatstone bridge. The stability of working in a wide temperature range will be reduced, which further reduces the accuracy of the whole chip magnetic field detection.

[0075] Based on this, the present application discloses a high-precision self-calibration magnetic switch chip for improving the accuracy of chip magnetic field detection.

[0076] The technical solutions in the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0077] Referring to Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 , the application provides an embodiment of a high-precision self-calibration magnetic switch chip, comprising:

[0078] a Wheatstone bridge, a regulator, a bandgap reference and current bias module BG&Ibias, a low-offset comparator COMP, a reference voltage module VREF_COMP, a digital module Digital TOP, a debug calibration module Debug DUT&Cali, a multiplexing output module MUX and a first transistor NMOS;

[0079] The VCC pin is connected with the bandgap reference and current bias module BG&Ibias and the debug calibration module Debug DUT&Cali respectively;

[0080] The bandgap reference and current bias module BG&Ibias are connected with the regulator and the reference voltage module VREF_COMP respectively;

[0081] The digital module Digital TOP is connected with the debug calibration module Debug DUT&Cali and the reference voltage module VREF_COMP respectively;

[0082] The Wheatstone bridge is connected with the regulator, the GND pin and the low-offset comparator COMP respectively;

[0083] The low-offset comparator COMP is connected with the reference voltage module VREF_COMP, the digital module Digital TOP and the first transistor NMOS respectively;

[0084] The first transistor NMOS is connected with the GND pin and the OUT pin respectively;

[0085] The multiplexing output module MUX is connected with the digital module Digital TOP, the debug calibration module Debug DUT&Cali and the OUT pin respectively;

[0086] The debug calibration module Debug DUT&Cali is connected with the OUT pin and the Test pin respectively.

[0087] In this embodiment, the bandgap reference and current bias module BG&Ibias provides the required bias voltage and bias current for the self-calibration magnetic switch chip in the application. The power supply voltage module Regulator supplies power to the Wheatstone bridge. The reference voltage module VREF_COMP provides the voltage VREF and Vcm for the low-offset comparator COMP, where VREF is the reference voltage for comparison with the VIN induced by the Wheatstone bridge, and Vcm is the common-mode potential of the low-offset comparator COMP. The Digital Top is a digital module that processes the digital functions of the entire self-calibration magnetic switch chip, including sending and receiving trim code values, VREF calibration code values, etc. The debug calibration module Debug DUT&cali functions to implement the debug function and undertake external calibration functions, i.e., in addition to the automatic calibration of the self-calibration magnetic switch chip, calibration codes can also be manually input to manually configure according to the multiplexing results. The MUX is a multiplexing module that multiplexes important signals in the debug mode. When the magnetically sensitive elements integrated in the Wheatstone bridge change their own characteristics with changes in the external temperature, thereby affecting the magnetic induction voltage output of the Wheatstone bridge, the reference voltage module VREF_COMP is used to calibrate the magnetic induction voltage output. Moreover, the high-precision self-calibration magnetic switch chip integrates a low-offset comparator COMP based on the automatic zeroing (AZ) technology inside, and has a magnetic bridge offset automatic calibration function and a temperature compensation function, achieving high-precision detection of the external magnetic field at all temperatures (-40-125°C). Finally, the magnetic induction voltage output of the Wheatstone bridge in the chip is stabilized, and the precision of the entire self-calibration magnetic switch chip in the external magnetic field detection is improved.

[0088] In this embodiment, the self-calibration magnetic switch chip has two working states, i.e., a normal working state and a factory configuration state. The self-calibration magnetic switch chip in the normal working state starts the self-circulation wake-up-sleep detection of the external magnetic field. The factory configuration state of the self-calibration magnetic switch chip includes the multiplexing (Debug) mode, the trimming (Trim) mode, the Offset automatic calibration mode, the burn-in mode, etc. The corresponding mode needs to be run according to the actual situation. When the self-calibration magnetic switch chip enters the Offset automatic calibration mode, all internal modules are enabled. The digital module Digital Top sends the enable signals Offset_en and Cali_trim<6:0> to the analog, which is all modules except the digital module Digital Top and the multiplexing output module MUX. The low-offset comparator COMP compares the current magnetic bridge reference voltage V REF with the size of the Wheatstone bridge output voltage V IN , obtains the comparison result, and modifies Cali_trim<6:0> according to the comparison result. The reference voltage module VREF_COMP internally integrates the magnetic bridge offset automatic calibration module and the Cali_trim<6:0> calibration magnetic bridge reference voltage VREF to equal the magnetic bridge output voltage V IN After the calibration is completed, the final Cali_trim<6:0> is registered, and the Offset auto-calibration mode is exited, and the debug multiplexing pin Test will listen to external commands again. In addition to determining the specific size of VREF in the Offset auto-calibration mode, it can also be directly configured according to the multiplexing output results in the Debug mode.

[0089] In this embodiment, the reference voltage module VREF_COMP sends the reference voltage V REF (V REFN , V REFP ) and V cm to the low-offset comparator COMP. The Wheatstone bridge sends V IN (V INN , V INP ) to the low-offset comparator COMP. The low-offset comparator COMP sends Comp_out to the digital module Digital. The digital module Digital sends the Cali_trim<6:0> signal, the Offset_en signal and the T<2:0> signal to the reference voltage module VREF_COMP. The digital module Digital sends MUX<3:0> to the multiplexing output module MUX. The debug calibration module Debug DUT&Cali sends the Debug_en signal, the Debug_trigger signal, the Cali_clk signal and the Cali_data signal to the digital module Digital. The debug calibration module Debug DUT&Cali sends the Debug_en signal to the multiplexing output module MUX, so that the entire chip runs.

[0090] Please refer to Figure 3 In this embodiment, the reference voltage module VREF_COMP includes a zero-temperature-coefficient current module, a positive-temperature-coefficient current module, a zero-temperature-coefficient resistor R5, a PNP transistor, a buffer A1, a buffer A2, a second transistor NMOS, a third transistor NMOS, a resistor R6, a reference voltage VREF output, a resistor RREF and a 7-bit current steering type DAC.

[0091] The zero-temperature-coefficient current module and the positive-temperature-coefficient current module are connected to the first end of the zero-temperature-coefficient resistor R5.

[0092] The first end of the zero-temperature-coefficient resistor R5 is connected to the negative electrode of the buffer A1, and the second end of the zero-temperature-coefficient resistor R5 is connected to the emitter of the PNP transistor.

[0093] The base and the collector of the PNP transistor are grounded.

[0094] The first end of the resistor R6 is connected with the positive pole of the second transistor NMOS and the buffer A1 respectively, and the second end of the resistor R6 is grounded.

[0095] The output of the buffer A1 is connected with the second transistor NMOS and the third transistor NMOS respectively.

[0096] The second transistor NMOS and the third transistor NMOS are also connected with the power supply.

[0097] The reference voltage VREF is divided into the reference voltage VREFN and the reference voltage VREFP, the reference voltage VREFP is connected with the third transistor NMOS, the first end of the resistor RREF and the 7-bit current steering type DAC respectively.

[0098] The reference voltage VREFN is connected with the second end of the resistor RREF, the output of the buffer A2 and the negative pole respectively.

[0099] The positive pole of the buffer A2 is connected with the voltage VBG_div.

[0100] In the embodiment, the internal reference voltage module VREF_COMP in the self-calibration magnetic switch chip is internally integrated with a temperature compensation module, which is specifically a zero-temperature-coefficient current module I0 and a positive-temperature-coefficient current module I ptat The superposition is constant, but the proportion of the two current parts can be configured by the signal T<2:0>. The superposition current flows through the zero-temperature-coefficient resistor R5 and the PNP transistor, and a voltage V1 with a negative temperature coefficient and a configurable temperature coefficient is generated.

[0101] V1=(I0-I ptat )R5+V BE =aR5+V BE

[0102] Wherein, V BE is the base-emitter voltage of the transistor, and a is a coefficient.

[0103] The voltage V1 passes through the buffer A1 to obtain a current I1 with a negative temperature coefficient and a configurable temperature coefficient:

[0104]

[0105] After the current mirror, the current I1 flows through the zero-temperature-coefficient resistor R REF , and the required reference voltage V REF is generated:

[0106]

[0107] The temperature T is differentiated, and the temperature coefficient of the reference voltage V REF is:

[0108]

[0109]

[0110] The two-part current ratio is configured by the signal T<2:0> so that the temperature coefficient of the reference voltage V REF matches the temperature coefficient of the magnetic bridge output voltage VIN, achieving temperature compensation. Among them, V BE0 is the average base-emitter voltage of the triode in the full temperature range.

[0111] The zero-temperature-coefficient current can be obtained by passing the bandgap reference voltage through the buffer, and the positive-temperature-coefficient current can be obtained by ΔV GS or ΔV BE , ΔV GS is the difference between the gate-source voltage V GS of the transistor, and ΔV BE is the difference between V BE and V BE0 .

[0112] Optionally, the Wheatstone bridge is composed of a magnetic sensitive element R1, a magnetic sensitive element R2, a magnetic sensitive element R3, and a magnetic sensitive element R4.

[0113] The magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R4, and the magnetic sensitive element R3 are connected in sequence to form the bridge.

[0114] Optionally, the interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R2 are connected with the low-offset comparator COMP.

[0115] The interfaces of the magnetic sensitive element R3 and the magnetic sensitive element R4 are connected with the low-offset comparator COMP.

[0116] The interfaces of the magnetic sensitive element R2 and the magnetic sensitive element R4 are connected with the GND pin.

[0117] The interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R2 are connected with the power supply voltage module Regulator.

[0118] Optionally, the magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3, and the magnetic sensitive element R4 are Hall magnetoresistance, AMR magnetoresistance, GMR magnetoresistance, or TMR magnetoresistance.

[0119] Please refer to Figure 4 and Figure 5The low-offset comparator COMP includes a first switch pair RST, a second switch pair RST, a switch pair Φ1, a switch pair Φ1d, a switch pair Φ2, a sampling capacitor CA / CB, a first-stage offset storage capacitor C1A / C1B, a second-stage offset storage capacitor C2A / C2B, a first-stage preamplifier A3, a second-stage preamplifier A4, a dynamic latch comparator Latch, and a D flip-flop DFF.

[0120] The switch pair Φ2 is connected with the sampling capacitor CA / CB.

[0121] The switch pair Φ1d is connected with the sampling capacitor CA / CB.

[0122] The sampling capacitor CA / CB is respectively connected with the switch pair Φ1 and the first-stage preamplifier A3.

[0123] The first-stage offset storage capacitor C1A / C1B is respectively connected with the first-stage preamplifier A3, the second-stage preamplifier A4, and the first switch pair RST.

[0124] The second-stage offset storage capacitor C2A / C2B is respectively connected with the second-stage preamplifier A4, the second switch pair RST, and the dynamic latch comparator Latch.

[0125] The dynamic latch comparator Latch is connected with the D flip-flop DFF.

[0126] Optionally, the switch pair Φ2 is connected with the Wheatstone bridge.

[0127] The switch pair Φ1d is connected with the reference voltage module VREF_COMP.

[0128] In the embodiment, the low-offset comparator in the high-precision self-calibration magnetic switch chip includes an input sampling capacitor CA / CB, a first-stage preamplifier A1, a first-stage offset storage capacitor C1A / C1B, a second-stage preamplifier A2, a second-stage offset storage capacitor C2A / C2B, a dynamic latch comparator Latch, a D flip-flop DFF, a switch pair RST, Φ1, Φ1d, and Φ2.

[0129] In this embodiment, the low-offset comparator COMP in the self-calibration magnetic switch chip is based on the automatic zeroing technology of offset, and has two working states of sampling offset storage and signal comparison amplification. When the high level of the control clock CLK is in the sampling offset storage state, the RST switch, the Φ1 switch, the Φ1d switch are closed, and the Φ2 switch is opened. At this time, the input sampling capacitor CA / CB samples the threshold reference voltage VREFP and VREFN, and the offset storage capacitors C1A / C1B and C2A / C2B store the offset voltages of the first pre-amplifier A1 and the second pre-amplifier A2 respectively. When the low level of the control clock CLK is in the signal comparison amplification state, the input sampling capacitor CA / CB samples the output voltage VINP and VINN of the magnetic bridge and compares it with the threshold reference voltage VREFP and VREFN at the previous moment. The obtained result is input to the dynamic latch comparator Latch after passing through the two pre-amplifiers A1 and A2, and is quickly amplified and latched by the D flip-flop DFF.

[0130] In this embodiment, the low-offset comparator COMP in the self-calibration magnetic switch chip is based on the automatic zeroing technology of offset, and has two working states of sampling offset storage and signal comparison amplification. When the high level of the control clock CLK is in the sampling offset storage state, the RST switch, the Φ1 switch, the Φ1d switch are closed, and the Φ2 switch is opened. At this time, the input sampling capacitor CA / CB samples the threshold reference voltage VREFP and VREFN, and the offset storage capacitors C1A / C1B and C2A / C2B store the offset voltages of the first pre-amplifier A1 and the second pre-amplifier A2 respectively. When the low level of the control clock CLK is in the signal comparison amplification state, the input sampling capacitor CA / CB samples the output voltage VINP and VINN of the magnetic bridge and compares it with the threshold reference voltage VREFP and VREFN at the previous moment. The obtained result is input to the dynamic latch comparator Latch after passing through the two pre-amplifiers A1 and A2, and is quickly amplified and latched by the D flip-flop DFF. Figure 5

[0131] Optionally, the high-precision self-calibration magnetic switch chip further comprises a low-power clock OSC.

[0132] The low-power clock OSC is connected with the VCC pin and the bandgap reference and current bias module BG&Ibias respectively.

[0133] Optionally, the high-precision self-calibration magnetic switch chip further comprises a Timer module as a timer.

[0134] The Timer module as a timer is connected with the low-power clock OSC.

[0135] Optionally, the high-precision self-calibration magnetic switch chip further comprises an under-voltage protection and over-temperature protection module UVLO&OTP.

[0136] The under-voltage protection and over-temperature protection module UVLO&OTP is connected with the VCC pin, the bandgap reference and current bias module BG&Ibias, and the digital module Digital TOP respectively.

[0137] In this embodiment, the OSC is an oscillator module, which provides a clock signal for the chip. The Timer module is a timer, which determines the sleep-wake cycle of the chip.

[0138] ​The under-voltage protection and over-temperature protection module UVLO&OTP is mainly used for protecting the circuit.

[0139] In this embodiment, the low-power clock OSC sends an OSC_ok signal to the band-gap reference and current bias module BG&Ibias. The under-voltage protection and over-temperature protection module UVLO&OTP sends a System_ok signal to the digital module Digital TOP.

[0140] In this application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to illustrate the relative positional relationship between the components or constituent parts, and do not particularly limit the specific installation orientation of the components or constituent parts.

[0141] In addition, in addition to being used to indicate the orientation or positional relationship, the above-mentioned partial terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in this application can be understood according to the specific circumstances.

[0142] In addition, the terms "mounting", "setting", "provided with", "connection", "connected" should be broadly understood. For example, it can be fixedly connected, detachably connected, or integrally configured; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication between two devices, elements or constituent parts. For those skilled in the art, the specific meaning of the above-mentioned terms in this application can be understood according to the specific circumstances.

[0143] In addition, the structure, proportion, size, etc. shown in the drawings attached in this application are only used to cooperate with the content disclosed in the specification, so that those skilled in the art can understand and read, and are not used to limit the defined conditions under which this application can be implemented, and therefore do not have technical substantive significance. Any modification of the structure, change of the proportion relationship, or adjustment of the size, without affecting the effect that can be produced by this application and the purpose that can be achieved, should still fall within the scope of the technical content disclosed by this application.

Claims

1. A high-precision self-calibrating magnetic switch chip, characterized in that, include: Wheatstone bridge, power supply voltage module Regulator, bandgap reference and current bias module BG&Ibias, low offset comparator COMP, reference voltage module VREF_COMP, digital module Digital TOP, debug and calibration module Debug DUT&Cali, multiplexed output module MUX and first transistor NMOS; The VCC pin is connected to the bandgap reference and current bias module BG&Ibias and the debugging and calibration module DebugDUT&Cali, respectively. The bandgap reference and current bias module BG&Ibias is connected to the power supply voltage module Regulator and the reference voltage module VREF_COMP, respectively. The digital module Digital TOP is connected to the debug and calibration module Debug DUT&Cali and the reference voltage module VREF_COMP, respectively. The Wheatstone bridge is connected to the power supply voltage module Regulator, the GND pin and the low offset comparator COMP respectively; The low offset comparator COMP is connected to the reference voltage module VREF_COMP, the digital module DigitalTOP, and the first transistor NMOS, respectively. The first transistor NMOS is connected to the GND pin and the OUT pin respectively; The multiplexed output module MUX is connected to the digital module Digital TOP, the debug and calibration module DebugDUT&Cali, and the OUT pin, respectively. The debug and calibration modules Debug DUT&Cali are connected to the OUT pin and Test pin, respectively. The reference voltage module VREF_COMP includes a zero temperature coefficient current module, a positive temperature coefficient current module, a zero temperature coefficient resistor R5, a PNP transistor, a buffer A1, a buffer A2, a second NMOS transistor, a third NMOS transistor, a resistor R6, a reference voltage VREF output, a resistor RREF, and a 7-bit current-controlled DAC. The zero temperature coefficient current module and the positive temperature coefficient current module are superimposed and connected to the first end of the zero temperature coefficient resistor R5. The first end of the zero temperature coefficient resistor R5 is connected to the negative terminal of the buffer A1, and the second end of the zero temperature coefficient resistor R5 is connected to the emitter of the PNP transistor. The base and collector of the PNP transistor are grounded; The first terminal of the resistor R6 is connected to the positive terminal of the second transistor NMOS and the buffer A1, respectively, and the second terminal of the resistor R6 is grounded. The output of the buffer A1 is connected to the second transistor NMOS and the third transistor NMOS, respectively; The second NMOS transistor and the third NMOS transistor are also connected to a power supply; The reference voltage VREF output is divided into a reference voltage VREFN and a reference voltage VREFP. The reference voltage VREFP is connected to the third transistor NMOS, the first terminal of the resistor RREF, and the 7-bit current-controlled DAC, respectively. The reference voltage VREFN is connected to the second terminal of the resistor RREF, the output of the buffer A2, and the negative terminal, respectively. The positive terminal of the buffer A2 is connected to the voltage VBG_div; The low offset comparator COMP includes a first switch pair RST, a second switch pair RST, a switch pair Φ1, a switch pair Φ1d, a switch pair Φ2, a sampling capacitor CA / CB, a first-stage offset storage capacitor C1A / C1B, a second-stage offset storage capacitor C2A / C2B, a first-stage preamplifier A3, a second-stage preamplifier A4, a dynamic latch comparator Latch, and a D flip-flop DFF; The switch pair Φ2 is connected to the sampling capacitor CA / CB; The switch pair Φ1d is connected to the sampling capacitor CA / CB; The sampling capacitors CA / CB are connected to the switch pair Φ1 and the first-stage pre-amplifier A3, respectively. The first-stage offset storage capacitors C1A / C1B are respectively connected to the first-stage pre-amplifier A3, the second-stage pre-amplifier A4, and the first switch pair RST; The second-stage offset storage capacitors C2A / C2B are connected to the second-stage pre-amplifier A4, the second switch pair RST, and the dynamic latch comparator Latch, respectively. The dynamic latch comparator (Latch) is connected to the D flip-flop (DFF). The switch pair Φ2 is connected to the Wheatstone bridge; The switch pair Φ1d is connected to the reference voltage module VREF_COMP; The high-precision self-calibrating magnetic switch chip also includes an undervoltage protection and overtemperature protection module UVLO&OTP. The undervoltage protection and overtemperature protection modules UVLO&OTP are connected to the VCC pin, the bandgap reference and current bias module BG&Ibias, and the digital module Digital TOP, respectively.

2. The high-precision self-calibrating magnetic switch chip according to claim 1, characterized in that, The Wheatstone bridge is composed of magnetic sensitive elements R1, R2, R3, and R4. The magnetic sensitive elements R1, R2, R4, and R3 are connected in sequence to form a bridge circuit.

3. The high-precision self-calibrating magnetic switch chip according to claim 2, characterized in that, The interfaces of the magnetic sensitive elements R1 and R2 are connected to the low offset comparator COMP. The interfaces of the magnetic sensitive elements R3 and R4 are connected to the low offset comparator COMP. The interfaces of the magnetic sensitive elements R2 and R4 are connected to the GND pin; The interfaces of the magnetic sensitive elements R1 and R2 are connected to the power supply voltage module Regulator.

4. The high-precision self-calibrating magnetic switch chip according to claim 3, characterized in that, The magnetic sensing elements R1, R2, R3, and R4 are Hall magnetoresistive, AMR magnetoresistive, GMR magnetoresistive, or TMR magnetoresistive.

5. The high-precision self-calibrating magnetic switch chip according to any one of claims 1 to 4, characterized in that, The high-precision self-calibrating magnetic switch chip also includes a low-power clock OSC. The low-power clock OSC is connected to the VCC pin and the bandgap reference and current bias module BG&Ibias, respectively.

6. The high-precision self-calibrating magnetic switch chip according to claim 5, characterized in that, The high-precision self-calibrating magnetic switch chip also includes a Timer module for timers; The Timer module is a timer connected to the low-power clock OSC.

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