Fast common-mode detection circuit for fully differential amplifiers

Abstract

The present invention provides a fast common-mode detection circuit for a fully differential amplifier, comprising: a switch circuit, a comparator circuit, and an operational amplifier; the non-inverting input of the operational amplifier is connected to the differential output of the fully differential amplifier and the comparator circuit, the inverting input of the operational amplifier is connected to a first reference voltage, and the output of the operational amplifier is connected to the common-mode control terminal of the fully differential amplifier; the switch circuit is connected to the comparator circuit and the differential output of the fully differential amplifier. Through the above-described method, the present invention can quickly start the fully differential amplifier and reduce the stabilization time of the common-mode voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a fast common-mode detection circuit of a fully differential amplifier. Background Art

[0002] Compared to single-ended output amplifiers, fully differential amplifiers offer advantages such as larger output swing, no image poles, and higher common-mode rejection and power supply rejection ratios. Consequently, fully differential amplifiers are increasingly used in mixed analog circuits. However, the output common-mode error of high-gain fully differential amplifiers is highly sensitive to component characteristics and mismatches. The high gain of the amplifier can amplify this error, causing the output voltage to reach the power supply or ground rails, causing the amplifier to operate incorrectly and fail to perform its basic function.

[0003] For a fully differential amplifier to function properly, all components must be operating correctly, and maintaining the common-mode voltage within the appropriate range is a fundamental prerequisite. This means the amplifier can only function properly after the common-mode voltage reaches the correct value. In some applications, the amplifier's startup speed must be very fast, requiring it to begin operating within a certain timeframe after power is applied. This requirement can be difficult to achieve if the amplifier's common-mode feedback loop bandwidth is too narrow.

[0004] In a traditional fully differential amplifier, such as Figure 1 As shown in Figure 1, the time it takes for the common-mode voltage to stabilize is related to the bandwidth of the common-mode feedback loop. To achieve high gain, the common-mode feedback loop typically incorporates an additional amplifier stage. This creates a two-pole system. To ensure stability, the secondary point must be pushed outside the loop bandwidth or reduced. Therefore, in traditional common-mode feedback designs, a large bandwidth comes at the expense of power consumption. Summary of the Invention

[0005] The present invention provides a fast common-mode detection circuit for a fully differential amplifier, which solves the problem of low startup speed of the existing fully differential amplifier.

[0006] Based on the above objectives, the present invention proposes a fast common-mode detection circuit for a fully differential amplifier, comprising: a switch circuit, a comparator circuit, and an operational amplifier; the non-inverting input terminal of the operational amplifier is connected to the differential output terminal of the fully differential amplifier and the comparator circuit, the inverting input terminal of the operational amplifier is connected to a first reference voltage, and the output terminal of the operational amplifier is connected to the common-mode control terminal of the fully differential amplifier; the switch circuit is connected to the comparator circuit and the differential output terminal of the fully differential amplifier.

[0007] Optionally, the comparator circuit includes: a first comparator and a second comparator; the inverting input of the first comparator and the inverting input of the second comparator are connected to the non-inverting input of the operational amplifier, the non-inverting input of the first comparator is connected to a second reference voltage, the non-inverting input of the second comparator is connected to a third reference voltage, and the output of the first comparator and the output of the second comparator are connected to the switching circuit.

[0008] Optionally, the second reference voltage is less than the third reference voltage, and the second reference voltage and the third reference voltage are set according to a normal common mode voltage range and voltage fluctuation.

[0009] Optionally, the switch circuit includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first MOS transistor, and a second MOS transistor; a first end of the first switch sw1a, a first end of the second switch sw1b, and a first end of the fifth switch sw3 are connected to the output end of the first comparator, a second end of the first switch and a second end of the second switch are connected to a first reference current source and to the gate and drain of the first MOS transistor, and a source of the first MOS transistor is connected to a power supply voltage; a first end of the third switch sw2a and a first end of the fourth switch sw2b are connected to the output end of the second comparator, a second end of the third switch and a second end of the fourth switch are connected to a second reference current source and to the gate and drain of the second MOS transistor and the second end of the fifth switch; a third end of the first switch is connected to the third end of the third switch and to the negative output end of the fully differential amplifier, a third end of the second switch is connected to the third end of the fourth switch and to the positive output end of the fully differential amplifier; and a third end of the fifth switch and the source of the second MOS transistor are grounded.

[0010] Optionally, the first switch, the third switch and the fifth switch are NMOS tubes, the second switch and the fourth switch are PMOS tubes; the first end is a gate, the second end is a drain, and the third end is a source.

[0011] Optionally, if the output common-mode voltage is higher than the third reference voltage, the third switch and the fourth switch are turned on, the first comparator and the second comparator output a low level, the positive output terminal and the negative output terminal of the fully differential amplifier are connected to the second reference current source, the second MOS transistor is turned on, and the output voltage of the fully differential amplifier is pulled down; if the output common-mode voltage is lower than the third reference voltage Vth and higher than the second reference voltage Vtl, the first comparator outputs a low level, the second comparator outputs a high level, the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are turned off, and the output of the fully differential amplifier is controlled by the common-mode loop; if the output common-mode voltage is lower than the second reference voltage Vtl, the first comparator and the second comparator output a high level, the first switch, the second switch, and the fifth switch are turned on, the positive output terminal and the negative output terminal of the fully differential amplifier are connected to the first reference current source, the second reference current source is connected to ground through the fifth switch, and the first MOS transistor is turned on to pull up the output voltage of the fully differential amplifier.

[0012] Optionally, the fast common-mode detection circuit further includes: a first resistor and a second resistor; the first resistor is connected between the positive output terminal of the fully differential amplifier and the non-inverting input terminal of the operational amplifier; the second resistor is connected between the negative output terminal of the fully differential amplifier and the non-inverting input terminal of the operational amplifier.

[0013] Optionally, the fast common-mode detection circuit further includes: a first capacitor and a second capacitor; the first capacitor is connected in parallel across the first resistor, and the second capacitor is connected in parallel across the second resistor.

[0014] Optionally, the fully differential amplifier includes: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; the gates of the third MOS transistor and the fourth MOS transistor are connected to a first reference current source, the sources are connected to a power supply voltage, the drains serve as differential output terminals of the fully differential amplifier, and are connected to the switch circuit and the non-inverting input terminal of the operational amplifier; the drain of the third MOS transistor is also connected to the drain of the fifth MOS transistor, and the drain of the fourth MOS transistor is connected to the drain of the sixth MOS transistor; the gates of the fifth MOS transistor and the sixth MOS transistor are connected to a differential input signal, the source of the fifth MOS transistor is connected to the drain of the seventh MOS transistor, the source of the sixth MOS transistor is connected to the drain of the eighth MOS transistor, the gate of the seventh MOS transistor is connected to the switch circuit, the gate of the eighth MOS transistor is connected to the output terminal of the operational amplifier, and the sources of the seventh MOS transistor and the eighth MOS transistor are grounded.

[0015] Optionally, the third MOS transistor and the fourth MOS transistor are PMOS transistors, the drain of the third MOS transistor is the negative output end of the fully differential amplifier, and the drain of the fourth MOS transistor is the positive output end of the fully differential amplifier; the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are NMOS transistors.

[0016] As can be seen from the above description, the beneficial effects of the technical solution provided by the present invention are as follows: a fast common-mode detection circuit for a fully differential amplifier provided by the present invention includes: a switching circuit, a comparator circuit, and an operational amplifier; the non-inverting input terminal of the operational amplifier is connected to the differential output terminal of the fully differential amplifier and the comparator circuit, the inverting input terminal of the operational amplifier is connected to a first reference voltage, and the output terminal of the operational amplifier is connected to the common-mode control terminal of the fully differential amplifier; the switching circuit is connected to the comparator circuit and the differential output terminal of the fully differential amplifier, which can quickly start the fully differential amplifier and reduce the stabilization time of the common-mode voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 Schematic diagram of the structure of a fast common-mode detection circuit of a fully differential amplifier in the prior art;

[0019] Figure 2 FIG. 4 is a circuit diagram of a fast common-mode detection circuit of a fully differential amplifier according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] The embodiment of the present invention implements a fast common-mode detection circuit of a fully differential amplifier, such as Figure 1 As shown, the system includes a switch circuit 11, a comparator circuit 12, and an operational amplifier 13. The non-inverting input of the operational amplifier 13 is connected to the differential output of the fully differential amplifier 14 and the comparator circuit 12, the inverting input of the operational amplifier 13 is connected to the first reference voltage Vcm_ref, and the output of the operational amplifier 13 is connected to the common-mode control terminal of the fully differential amplifier 14. The switch circuit 11 is connected to the comparator circuit 12 and the differential output of the fully differential amplifier 14. The comparator circuit 12 controls the on / off state of the switch circuit 11 according to the differential output of the fully differential amplifier 14, so that the fully differential amplifier 14 quickly stabilizes to the common-mode voltage, achieving fast startup.

[0023] In the embodiment of the present invention, Figure 2 As shown, the comparator circuit 12 includes a first comparator C1 and a second comparator C2. The inverting input of the first comparator C1 and the inverting input of the second comparator C2 are connected to the non-inverting input of the operational amplifier 13. The non-inverting input of the first comparator C1 is connected to a second reference voltage Vt1, and the non-inverting input of the second comparator C2 is connected to a third reference voltage Vth. The outputs of the first comparator C1 and the second comparator C2 are connected to the switching circuit 11. The second reference voltage Vt1 is lower than the third reference voltage Vth. The second reference voltage Vt1 and the third reference voltage Vth are set based on a normal common-mode voltage range and voltage fluctuation.

[0024] The switch circuit 11 includes: a first switch sw1a, a second switch sw1b, a third switch sw2a, a fourth switch sw2b, a fifth switch sw3, a first MOS transistor M0r, and a second MOS transistor M2r. The first end of the first switch sw1a, the first end of the second switch sw1b, and the first end of the fifth switch sw3 are connected to the output end of the first comparator C1. The second end of the first switch sw1a and the second end of the second switch sw1b are connected to the first reference current source ibp and to the gate and drain of the first MOS transistor M0r. The source of the first MOS transistor M0r is connected to the power supply voltage. The first end of the third switch sw2a and the first end of the fourth switch sw2b are connected to the output end of the second comparator C2. The second end of the third switch sw2a and the second end of the fourth switch sw2b are connected to the output end of the second comparator C2. A second end of the switch sw2b is connected to the second reference current source ibn, and is connected to the gate and drain of the second MOS transistor M2r, and the second end of the fifth switch sw3. A third end of the first switch sw1a is connected to the third end of the third switch sw2a, and is connected to the negative output terminal Vout- of the fully differential amplifier 14. A third end of the second switch sw1b is connected to the third end of the fourth switch sw2b, and is connected to the positive output terminal Vout+ of the fully differential amplifier 14. A third end of the fifth switch sw3 and the source of the second MOS transistor M2r are grounded GND.

[0025] The first switch sw1a, the third switch sw2a and the fifth switch sw3 are NMOS transistors, the second switch sw1b and the fourth switch sw2b are PMOS transistors; the first end is a gate, the second end is a drain, and the third end is a source.

[0026] In an embodiment of the present invention, the fast common-mode detection circuit further includes: a first resistor R1a and a second resistor R1b; the first resistor R1a is connected between the positive output terminal Vout+ of the fully differential amplifier 14 and the non-inverting input terminal of the operational amplifier 13; and the second resistor R1b is connected between the negative output terminal Vout- of the fully differential amplifier 14 and the non-inverting input terminal of the operational amplifier 13. The fast common-mode detection circuit may further include: a first capacitor C1a and a second capacitor C1b; the first capacitor C1a is connected in parallel across the first resistor R1a, and the second capacitor C1b is connected in parallel across the second resistor R1b. The differential output of the fully differential amplifier 14 is transmitted to the non-inverting input terminal of the operational amplifier and the comparator circuit 12 via the parallel first resistor R1a and first capacitor C1a, and the parallel second resistor R1b and second capacitor C1b, for subsequent feedback processing.

[0027] The fully differential amplifier 14 includes: a third MOS transistor M0a, a fourth MOS transistor M0b, a fifth MOS transistor M1a, a sixth MOS transistor M1b, a seventh MOS transistor M2a, and an eighth MOS transistor M3; the gates of the third MOS transistor M0a and the fourth MOS transistor M0b are connected to the first reference current source ibp, the sources are connected to the power supply voltage VCC, and the drains serve as the differential output terminals of the fully differential amplifier 14 and are connected to the switch circuit 11 and the non-inverting input terminal of the operational amplifier 13. The drain of the third MOS transistor M0a is also connected to the drain of the fifth MOS transistor M1a, and the fourth MOS transistor M0b is connected to the drain of the fifth MOS transistor M1a. The drain of the S transistor M0b is connected to the drain of the sixth MOS transistor M1b; the gates of the fifth MOS transistor M1a and the sixth MOS transistor M1b are connected to a differential input signal, the source of the fifth MOS transistor M1a is connected to the drain of the seventh MOS transistor M2a, the source of the sixth MOS transistor M1b is connected to the drain of the eighth MOS transistor M3, the gate of the seventh MOS transistor M2a is connected to the switch circuit 11, the gate of the eighth MOS transistor M3 is connected to the output end of the operational amplifier 13, and the sources of the seventh MOS transistor M2a and the eighth MOS transistor M3 are grounded GND.

[0028] The third MOS transistor M0a and the fourth MOS transistor M0b are PMOS transistors. The drain of the third MOS transistor M0a is the negative output terminal Vout- of the fully differential amplifier 14, and the drain of the fourth MOS transistor M0b is the positive output terminal Vout+ of the fully differential amplifier 14. The fifth MOS transistor M1a, the sixth MOS transistor M1b, the seventh MOS transistor M2a, and the eighth MOS transistor M3 are NMOS transistors.

[0029] In traditional fully differential amplifiers, the common-mode voltage stabilization time is related to the bandwidth of the common-mode feedback loop. To achieve high gain, the common-mode feedback loop typically incorporates an additional amplifier stage. This creates a two-pole system. To ensure common-mode feedback loop stability, the secondary point must be pushed outside the loop bandwidth or the loop bandwidth must be reduced. Therefore, in traditional common-mode feedback designs, a large bandwidth comes at the expense of power consumption. Existing SC-CMFB circuits offer a larger common-mode feedback loop bandwidth, but their bandwidth is still limited to the differential mode circuit and cannot exceed the differential mode bandwidth. Therefore, their common-mode voltage stabilization time is still limited by the common-mode loop bandwidth.

[0030] The fast common-mode detection circuit for a fully differential amplifier according to an embodiment of the present invention adds a portion of circuitry to a conventional common-mode feedback circuit to achieve fast startup of the fully differential amplifier. The following is the operating principle of the fast common-mode detection circuit for a fully differential amplifier:

[0031] If the output common-mode voltage is higher than the third reference voltage Vth, the third switch sw2a and the fourth switch sw2b are turned on, the first comparator C1 and the second comparator C2 output a low level, the positive output terminal Vout+ and the negative output terminal Vout- of the fully differential amplifier 14 are connected to the second reference current source ibn, and the second MOS transistor M2r is turned on to pull down the output voltage of the fully differential amplifier 14. The current of the second MOS transistor M2r increases, causing the current of the seventh MOS transistor M2a to increase, which also reduces the output voltage.

[0032] If the output common-mode voltage is lower than the third reference voltage Vth and higher than the second reference voltage Vtl, the first comparator C1 outputs a low level, the second comparator C2 outputs a high level, the first switch sw1a, the second switch sw1b, the third switch sw2a, the fourth switch sw2b and the fifth switch sw3 are turned off, and the output of the fully differential amplifier 14 is controlled by the common-mode loop.

[0033] If the output common-mode voltage is lower than the second reference voltage Vt1, the first comparator C1 and the second comparator C2 output a high level. The first switch sw1a, the second switch sw1b, and the fifth switch sw3 are turned on. The positive output terminal Vout+ and the negative output terminal Vout- of the fully differential amplifier 14 are connected to the first reference current source ibp. The second reference current source ibn is connected to ground GND via the fifth switch sw3. The first MOS transistor M0r is turned on, pulling up the output voltage of the fully differential amplifier 14. The current in the first MOS transistor M0r increases, causing the current in the third and fourth MOS transistors M0a and M0b to increase, which also increases the output voltage. Subsequently, the fifth switch sw3 is turned on, and the current in the second reference current source ibn flows to ground GND through the fifth switch sw3. The current in the second MOS transistor M2r decreases, causing the current in the seventh MOS transistor M2a to decrease, and the output voltage to increase.

[0034] The fast common-mode detection circuit of the fully differential amplifier according to the embodiment of the present invention sets three voltage ranges. For the two ranges higher than the third reference voltage Vth and lower than the second reference voltage Vtl, the output common-mode voltage can be quickly pulled to a suitable voltage range through the fast common-mode detection circuit. However, the circuit state is incorrect at this time and can only be used for the fast establishment process. When the output common voltage Vcm reaches the appropriate range, that is, Vtl < Vcm < Vth, the fast common-mode detection circuit stops working, and the common-mode feedback circuit is used to control the establishment of the common-mode voltage. The fast establishment circuit does not affect the normal operation of the circuit. Therefore, the settings of the two voltages, the third reference voltage Vth and the second reference voltage Vtl, need to be reasonable and should be set according to the normal common-mode voltage range and voltage fluctuation of the circuit. If the range is set smaller, the common-mode fluctuation during normal operation will cause the fast common-mode monitoring circuit to start, resulting in circuit anomalies. If the range is set too large, the purpose of fast establishment cannot be achieved.

[0035] In summary, the fast common-mode detection circuit of the fully differential amplifier according to the embodiment of the present invention includes: a switch circuit, a comparator circuit, and an operational amplifier; the non-inverting input terminal of the operational amplifier is connected to the differential output terminal of the fully differential amplifier and the comparator circuit, the inverting input terminal of the operational amplifier is connected to the first reference voltage, and the output terminal of the operational amplifier is connected to the common-mode control terminal of the fully differential amplifier; the switch circuit is connected to the comparator circuit and the differential output terminal of the fully differential amplifier, and can quickly start the fully differential amplifier and reduce the settling time of the common-mode voltage.

[0036] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present disclosure is limited to these examples; under the concept of the present disclosure, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present invention as described above, which are not provided in detail for the sake of brevity.

[0037] The embodiments of the present invention aim to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of the present invention shall be included within the protection scope of the present disclosure.

Claims

1. A fast common-mode detection circuit for a fully differential amplifier, characterized in that: The fast common-mode detection circuit includes: a switch circuit, a comparator circuit, and an operational amplifier; the non-inverting input terminal of the operational amplifier is connected to the differential output terminal of the fully differential amplifier and the comparator circuit, the inverting input terminal of the operational amplifier is connected to a first reference voltage, and the output terminal of the operational amplifier is connected to the common-mode control terminal of the fully differential amplifier; the switch circuit is connected to the comparator circuit and the differential output terminal of the fully differential amplifier; The comparator circuit includes: a first comparator and a second comparator; an inverting input terminal of the first comparator and an inverting input terminal of the second comparator are connected to a non-inverting input terminal of the operational amplifier, the non-inverting input terminal of the first comparator is connected to a second reference voltage, the non-inverting input terminal of the second comparator is connected to a third reference voltage, and an output terminal of the first comparator and an output terminal of the second comparator are connected to the switch circuit; The second reference voltage is less than the third reference voltage, and the second reference voltage and the third reference voltage are set according to a normal common mode voltage range and voltage fluctuation; The switch circuit includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first MOS transistor, and a second MOS transistor; the first end of the first switch, the first end of the second switch, and the first end of the fifth switch are connected to the output end of the first comparator, the second end of the first switch and the second end of the second switch are connected to a first reference current source and to the gate and drain of the first MOS transistor, and the source of the first MOS transistor is connected to a power supply voltage; the first end of the third switch and the first end of the fourth switch are connected to the output end of the second comparator, the second end of the third switch and the second end of the fourth switch are connected to a second reference current source and to the gate and drain of the second MOS transistor and the second end of the fifth switch; the third end of the first switch is connected to the third end of the third switch and to the negative output end of the fully differential amplifier, the third end of the second switch is connected to the third end of the fourth switch and to the positive output end of the fully differential amplifier; the third end of the fifth switch and the source of the second MOS transistor are grounded.

2. The fast common-mode detection circuit according to claim 1, wherein: The first switch, the third switch, and the fifth switch are NMOS transistors, the second switch and the fourth switch are PMOS transistors; the first end is a gate, the second end is a drain, and the third end is a source.

3. The fast common-mode detection circuit according to claim 1, wherein: If the output common-mode voltage is higher than the third reference voltage, the third switch and the fourth switch are turned on, the first comparator and the second comparator output a low level, the positive output terminal and the negative output terminal of the fully differential amplifier are connected to the second reference current source, and the second MOS transistor is turned on to pull down the output voltage of the fully differential amplifier; If the output common-mode voltage is lower than the third reference voltage and higher than the second reference voltage, the first comparator outputs a low level, the second comparator outputs a high level, the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are turned off, and the output of the fully differential amplifier is controlled by the common-mode loop; If the output common-mode voltage is lower than the second reference voltage, the first comparator and the second comparator output a high level, the first switch, the second switch, and the fifth switch are turned on, the positive output terminal and the negative output terminal of the fully differential amplifier are connected to the first reference current source, the second reference current source is connected to the ground through the fifth switch, and the first MOS transistor is turned on to pull up the output voltage of the fully differential amplifier.

4. The fast common mode detection circuit according to claim 1, wherein: The fast common-mode detection circuit also includes: a first resistor and a second resistor; the first resistor is connected between the positive output terminal of the fully differential amplifier and the non-inverting input terminal of the operational amplifier; the second resistor is connected between the negative output terminal of the fully differential amplifier and the non-inverting input terminal of the operational amplifier.

5. The fast common mode detection circuit according to claim 4, wherein: The fast common-mode detection circuit further includes: a first capacitor and a second capacitor; the first capacitor is connected in parallel to both ends of the first resistor, and the second capacitor is connected in parallel to both ends of the second resistor.

6. The fast common mode detection circuit according to claim 1, wherein: The fully differential amplifier includes: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; the gates of the third MOS transistor and the fourth MOS transistor are connected to a first reference current source, the sources are connected to a power supply voltage, the drains serve as differential output terminals of the fully differential amplifier and are connected to the switch circuit and the non-inverting input terminal of the operational amplifier; the drain of the third MOS transistor is also connected to the drain of the fifth MOS transistor, and the drain of the fourth MOS transistor is connected to the drain of the sixth MOS transistor; the gates of the fifth MOS transistor and the sixth MOS transistor are connected to a differential input signal, the source of the fifth MOS transistor is connected to the drain of the seventh MOS transistor, the source of the sixth MOS transistor is connected to the drain of the eighth MOS transistor, the gate of the seventh MOS transistor is connected to the switch circuit, the gate of the eighth MOS transistor is connected to the output terminal of the operational amplifier, and the sources of the seventh and eighth MOS transistors are grounded.

7. The fast common mode detection circuit according to claim 6, wherein: The third MOS transistor and the fourth MOS transistor are PMOS transistors, the drain of the third MOS transistor is the negative output end of the fully differential amplifier, and the drain of the fourth MOS transistor is the positive output end of the fully differential amplifier; the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor are NMOS transistors.

Images