Surface Plasmon Lithography Mask Pattern Optimization Method, Apparatus, System and Medium

Abstract

The present application provides a method, apparatus, system and medium for optimizing surface plasmon lithography mask patterns. The training set includes: the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns; the mapping relationship between the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns is learned using the training set; the feature size of the current target photoresist pattern is input into a pre-trained neural network model to output the feature size of the current simulated photoresist pattern; the first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern is calculated; a multivariate optimization algorithm is used to determine the optimization step size of the current mask pattern; and the feature size of the optimized mask pattern is obtained according to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern. The neural network model can quickly optimize the lithography mask pattern, reducing the pattern error in an efficient manner.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a method, device, system, and medium for optimizing a surface plasmon lithography mask pattern. Background Art

[0002] Lithography technology is a key technology in integrated circuit manufacturing. Its core purpose is to transfer the designed pattern onto a silicon wafer and various layers of materials.

[0003] The current mainstream lithography technology relies on a light source irradiating a mask (with the circuit pattern to be transferred on the mask), passing through a projection system, projecting the image onto a photoresist, then the photoresist undergoes a photochemical reaction, and after steps such as baking and developing and cleaning, a photoresist pattern is formed.

[0004] The minimum size that the entire integrated circuit manufacturing process can achieve is determined by lithography technology. In the currently used lithography technology, restricted by the optical diffraction limit, the resolution of traditional lithography can only reach the level of half a wavelength. For example, a lithography machine with a wavelength of 248 nm is usually used for the exposure of patterns with a period greater than 260 nm.

[0005] With the development of near-field optics, methods that break through the diffraction limit, represented by surface plasmons (SPs), have gradually been realized. The structure of lithography technology based on surface plasmons is different from that of traditional projection lithography. It does not require the use of complex lenses, but instead uses various film layer structures. Using surface plasmon lithography, it is possible to achieve a lithography image with a size much smaller than the light source wavelength at a large wavelength. For example, there are literature reports of using a light source with a wavelength of 365 nm to achieve a line pattern with a period less than 200 nm.

[0006] However, like projection lithography, when the pattern on the mask is transferred to the photoresist pattern through lithography, errors will also occur, and even the errors are larger. The error is defined as the difference between the target pattern and the photoresist pattern. When there is no mask pattern optimization scheme, it can be considered that the target pattern is equal to the mask pattern. For example, when we draw a pattern with CD = 190 nm and SPACE = 190 nm on the mask (i.e., the target pattern), we cannot obtain the pattern we drew (the target pattern) on the photoresist. Due to various factors, the CD of the photoresist pattern after exposure is 208.2 nm, and the error from the target pattern is 18.2 nm.

[0007] Therefore, the mask pattern needs to be corrected and optimized in order to obtain the target pattern we want on the photoresist. Summary of the Invention

[0008] In view of this, the present invention content is provided to introduce the concepts in a concise form, which will be described in detail in the following detailed implementation section. The present invention content is not intended to identify the key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0009] The purpose of this application is to provide a method, device, system, and medium for optimizing the pattern of a surface plasmon lithography mask, which can quickly optimize the lithography mask pattern and reduce the pattern error in an efficient manner.

[0010] To achieve the above purpose, this application has the following technical solutions:

[0011] In a first aspect, an embodiment of this application provides a method for optimizing the pattern of a surface plasmon lithography mask, including:

[0012] Obtain the feature size of the current target photoresist pattern;

[0013] Obtain the training set of the initial neural network model, where the training set includes: the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns;

[0014] Use the training set to learn the mapping relationship between the feature sizes of the historical target photoresist pattern and the feature sizes of the historical actual photoresist pattern;

[0015] Determine the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model;

[0016] Input the feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern;

[0017] Calculate the first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern;

[0018] According to the first error value, use a multi-optimization algorithm to determine the optimization step size of the current mask pattern;

[0019] Calculate the feature size of the optimized mask pattern according to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern.

[0020] In a possible implementation, it further includes:

[0021] Input the feature size of the optimized mask pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the optimized simulated photoresist pattern;

[0022] Calculate a second error value between the feature size of the optimized mask pattern and the feature size of the optimized simulated photoresist pattern;

[0023] Compare the magnitudes of the first error value and the second error value;

[0024] When the second error value is small, determine a re-optimization step size of the optimized mask pattern according to the second error value by using a multi-variable optimization algorithm;

[0025] Calculate the feature size of the re-optimized mask pattern according to the feature size of the optimized mask pattern and the re-optimization step size of the optimized mask pattern.

[0026] In a possible implementation manner, calculating the first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern includes:

[0027] cost = error1 2 + error2 2 + …… + error n 2 ;

[0028] The cost is the first error value; error1, error2 …… error n are the differences between the feature sizes of the respective patterns in the current target photoresist pattern and the feature sizes of the respective patterns in the current simulated photoresist pattern; the n is a positive integer.

[0029] In a possible implementation manner, the type of the neural network model includes a convolutional neural network model.

[0030] In a second aspect, an embodiment of the present application provides a surface plasmon lithography mask pattern optimization device, including:

[0031] An acquisition unit, configured to acquire the feature size of a current target photoresist pattern;

[0032] A training set unit, configured to acquire a training set of an initial neural network model, where the training set includes: the feature size of a historical target photoresist pattern and the feature size of a historical actual photoresist pattern;

[0033] A learning unit, configured to learn a mapping relationship between the feature size of the historical target photoresist pattern and the feature size of the historical actual photoresist pattern by using the training set;

[0034] A determination unit, configured to determine model parameters of the initial neural network model according to the mapping relationship, so as to obtain a pre-trained neural network model;

[0035] A first input unit, configured to input a feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs a feature size of a current simulated photoresist pattern;

[0036] A first calculation unit, configured to calculate a first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern;

[0037] A first step size unit, configured to determine an optimization step size of the current mask pattern according to the first error value by using a multi-variable optimization algorithm;

[0038] A first optimization unit, configured to calculate a feature size of an optimized mask pattern according to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern.

[0039] In a possible implementation manner, it further includes:

[0040] A second input unit, configured to input the feature size of the optimized mask pattern into the pre-trained neural network model, and the pre-trained neural network model outputs a feature size of an optimized simulated photoresist pattern;

[0041] A second calculation unit, configured to calculate a second error value between the feature size of the optimized mask pattern and the feature size of the optimized simulated photoresist pattern;

[0042] A comparison unit, configured to compare magnitudes of the first error value and the second error value;

[0043] A second step size unit, configured to, when the second error value is small, determine a re-optimization step size of the optimized mask pattern according to the second error value by using a multi-variable optimization algorithm;

[0044] A second optimization unit, configured to calculate a feature size of a re-optimized mask pattern according to the feature size of the optimized mask pattern and the re-optimization step size of the optimized mask pattern.

[0045] In a possible implementation manner, the first calculation unit is specifically configured to calculate the first error value cost:

[0046] cost = error1 2 + error2 2 + …… + error n 2 ;

[0047] The cost is the first error value; the error1, error2... error n is the difference between the feature sizes of each pattern in the current target photoresist pattern and the feature sizes of each pattern in the current simulated photoresist pattern; n is a positive integer.

[0048] In a possible implementation, the type of the neural network model includes a convolutional neural network model.

[0049] In a third aspect, an embodiment of the present application provides a surface plasmon lithography mask pattern optimization system, including:

[0050] A memory for storing a computer program;

[0051] A processor for implementing the steps of the surface plasmon lithography mask pattern optimization method as described above when executing the computer program.

[0052] In a fourth aspect, an embodiment of the present application provides a computer-readable medium, on which a computer program is stored, and when the computer program is processed and executed, the steps of the surface plasmon lithography mask pattern optimization method as described above are implemented.

[0053] Compared with the related art, the embodiments of the present application have the following beneficial effects:

[0054] The embodiments of the present application provide a surface plasmon lithography mask pattern optimization method, device, system and medium. The method includes: obtaining the feature size of the current target photoresist pattern; obtaining the training set of the initial neural network model, where the training set includes: the feature size of the historical target photoresist pattern and the feature size of the historical actual photoresist pattern; using the training set to learn the mapping relationship between the feature size of the historical target photoresist pattern and the feature size of the historical actual photoresist pattern; determining the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model; inputting the feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern; calculating the first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern; determining the optimization step size of the current mask pattern according to the first error value by using a multi-variable optimization algorithm; calculating the feature size of the optimized mask pattern according to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern. Accordingly, the present application can quickly optimize the lithography mask pattern by using the neural network model, and reduce the pattern error in an efficient manner. Description of the Drawings

[0055] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0056] Combined with the drawings and referring to the following specific embodiments, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic, and the original components and elements are not necessarily drawn to scale.

[0057] Figure 1 Fig. shows a schematic diagram of a traditional typical non - extreme ultraviolet exposure system provided by an embodiment of the present application;

[0058] Figure 2 Fig. shows a schematic diagram of a lithography technology structure based on surface plasmon provided by an embodiment of the present application;

[0059] Figure 3 Fig. shows a schematic diagram of an original pattern and a photoresist pattern before correction provided by an embodiment of the present application;

[0060] Figure 4 Fig. shows a schematic diagram of an original pattern and a photoresist pattern after correction provided by an embodiment of the present application;

[0061] Figure 5 Fig. shows a flowchart of a method for optimizing a surface plasmon lithography mask pattern provided by an embodiment of the present application;

[0062] Figure 6 Fig. shows a schematic diagram of a photoresist pattern provided by an embodiment of the present application;

[0063] Figure 7 Fig. shows a schematic diagram of another photoresist pattern provided by an embodiment of the present application;

[0064] Figure 8 Fig. shows a schematic diagram of a layout provided by an embodiment of the present application;

[0065] Figure 9 Fig. shows a schematic diagram of another layout provided by an embodiment of the present application;

[0066] Figure 10 Fig. shows a schematic diagram of mask optimization provided by an embodiment of the present application;

[0067] Figure 11 Fig. shows a schematic diagram of yet another layout provided by an embodiment of the present application;

[0068] Figure 12 Shows a schematic diagram of another layout provided by an embodiment of the present application;

[0069] Figure 13 Shows a schematic diagram of a surface plasmon lithography mask pattern optimization device provided by an embodiment of the present application. Detailed implementation manners

[0070] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed implementation manners of the present application in conjunction with the accompanying drawings.

[0071] In the following description, many specific details are set forth to facilitate a thorough understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0072] As described in the background art, through research by the applicant, it is found that lithography technology is a key technology in integrated circuit manufacturing, and its core purpose is to transfer the designed pattern onto the silicon wafer and various layers of materials.

[0073] The current mainstream lithography technology relies on a light source irradiating a mask (with the circuit pattern to be transferred on the mask), passing through a projection system, projecting the image onto the photoresist, then the photoresist undergoes a photochemical reaction, and then through steps such as baking and developing and cleaning, thereby forming a photoresist pattern.

[0074] See Figure 1 As shown, it is a schematic diagram of a traditional typical non-extreme ultraviolet exposure system, which sequentially includes a light source, a lens, a mask, a lens, a lens, a photoresist (film stack), and a wafer from top to bottom, respectively constituting a light source system and a projection system.

[0075] The minimum size that the entire integrated circuit manufacturing process can achieve is determined by lithography technology. In the currently used lithography technology, restricted by the optical diffraction limit, the resolution of traditional lithography can only reach the level of half a wavelength. For example, a lithography machine with a wavelength of 248nm is usually used for the exposure of patterns with a period greater than 260nm.

[0076] With the development of near-field optics, methods that break through the diffraction limit, represented by surface plasmons (SPs), have gradually been realized. The structure of lithography technology based on surface plasmons is different from that of traditional projection lithography. It does not require the use of complex lenses, but instead various film layer structures. Using surface plasmon lithography, it is possible to achieve a lithography image with a size much smaller than the light source wavelength at a large wavelength. For example, some literature reports using a light source with a wavelength of 365 nm to achieve line patterns with a period of less than 200 nm.

[0077] See Figure 2 As shown, it is a schematic diagram of the structure of lithography technology based on surface plasmons, where PR (photoresist), Ag is the silver layer, PMMA (polymethyl methacrylate) is the polymer material layer, and Cr and Quartz form the mask layer. A light source with a wavelength of 365 nm is used for illumination.

[0078] However, like projection lithography, when the pattern on the mask is transferred to the photoresist pattern through lithography, errors will also occur, and even the errors are larger. The error is defined as the difference between the target pattern and the photoresist pattern. When there is no mask pattern optimization scheme, it can be considered that the target pattern is equal to the mask pattern. For example, when we draw a pattern with CD = 190 nm and SPACE = 190 nm on the mask (i.e., the target pattern), we cannot obtain the pattern we drew (the target pattern) on the photoresist. Due to various factors, the CD of the photoresist pattern after exposure is 208.2 nm, and the error from the target pattern is 18.2 nm.

[0079] Therefore, the mask pattern needs to be corrected and optimized in order to obtain the target pattern we want on the photoresist.

[0080] In addition, the applicant's research found that in projection lithography, model-based optical proximity correction (OPC) is often used to optimize the mask pattern to reduce errors. First, the specific lithography conditions are modeled, and an optical model is used to describe the physical process from the light source to the mask and then to the photoresist surface. Then, a photoresist model is used to describe the physical process of photoresist development and imaging. Through the OPC model (optical model + photoresist model), it is possible to use the gds pattern (i.e., the pattern on the mask, stored in a file with the.gds format) as the input and simulate and calculate to obtain the photoresist pattern. Usually, in order to make the model more accurate, actual exposure data is also required to calibrate the model.

[0081] Taking the photoresist pattern after actual exposure with a CD of 208.2 nm as an example, when the model is relatively accurate, its CD value should be around 208.2 nm, that is, the error from the actual measurement value is not large.

[0082] The core is that the exposure process can be simulated through the model. (After the model is accurately calibrated, the simulation result is not much different from the actual measurement result).

[0083] With the model, the pattern can be corrected. Usually, each side of the mask pattern is moved. After the movement, the photoresist pattern is calculated through the model. When the error between the photoresist pattern and the target pattern is minimized, the movement ends. This process can be understood as model-based OPC. The moved mask pattern is the corrected pattern. After its exposure, the error between the photoresist pattern and the target pattern is minimized.

[0084] For example, see Figure 3 As shown, it is a schematic diagram of an original pattern and a photoresist pattern before correction. Before correction, the CD of the original gds pattern (target pattern) is 180 nm, and the CD (Critical Dimension) of the photoresist pattern of the original gds pattern obtained by model simulation is 141 nm, and the error = |141 nm - 180 nm| = 39 nm.

[0085] See Figure 4 As shown, it is a schematic diagram of an original pattern and a photoresist pattern after correction. After the original gds pattern is corrected, for example, 30 nm is corrected on each side. The CD of the photoresist pattern of the corrected mask pattern obtained by model simulation is 173 nm, and the error = |173 nm - 180 nm| = 7 nm. The error is significantly reduced compared to before correction.

[0086] The lithography technology based on surface plasmon is different from traditional projection lithography. It does not require the use of complex lenses. Instead, various film layer structures are used. Therefore, the model describing surface plasmon lithography is also different from the model of projection lithography (such as the Abbe model and Hopkins model widely used in projection lithography OPC). A rigorous electromagnetic field simulation model needs to be used, usually using methods such as FDTD (Finite Difference Time Domain), RCWA (Rigorous Coupled Wave Analysis), and finite element. The common feature is that the amount of calculation is huge and the simulation result cannot be obtained quickly.

[0087] To solve the above technical problems, an embodiment of the present application provides a method, device, system, and medium for optimizing a surface plasmon lithography mask pattern. The method includes: obtaining the feature size of the current target photoresist pattern; obtaining the training set of the initial neural network model, where the training set includes the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns; using the training set to learn the mapping relationship between the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns; determining the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model; inputting the feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern; calculating the first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern; determining the optimization step size of the current mask pattern according to the first error value using a multi-optimization algorithm; calculating the feature size of the optimized mask pattern according to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern. Thus, the present application can quickly optimize the lithography mask pattern using a neural network model, reducing the pattern error in an efficient manner.

[0088] Exemplary method

[0089] See Figure 5 As shown, it is a flowchart of a method for optimizing a surface plasmon lithography mask pattern provided by an embodiment of the present application, including:

[0090] S101: Obtain the feature size of the current target photoresist pattern;

[0091] S102: Obtain the training set of the initial neural network model, where the training set includes the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns;

[0092] S103: Use the training set to learn the mapping relationship between the feature sizes of the historical target photoresist pattern and the historical actual photoresist pattern;

[0093] S104: Determine the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model.

[0094] In an embodiment of the present application, first, the feature size of the current target photoresist pattern can be obtained. Since the layout range is very large in actual lithography, in order to save computing resources, the layout segmentation can be corrected and optimized separately.

[0095] Specifically, the embodiment of the present application is directed to a square hole pattern, that is, the pattern of the interconnect layer or the via layer (via, contact).

[0096] First, a range r needs to be determined. In projection lithography, the optical diameter is used to represent this range. That is, a pattern outside this range will have no impact on the imaging of other patterns. This range r can be obtained through theoretical calculations, and more importantly, it should be measured by designing test patterns and performing actual surface plasmon lithography.

[0097] For example, refer to Figure 6 As shown, it is a schematic diagram of a photoresist pattern provided by an embodiment of the present application. When the side length of the square hole is CD = 65nm and the pitch of the surrounding square holes is 75nm, the photoresist pattern is about 65nm. Refer to Figure 7 As shown, it is another schematic diagram of a photoresist pattern provided by an embodiment of the present application. When the pitch of the surrounding square holes is 105nm, the photoresist pattern is less than 65nm. And so on. When the pitch of the square holes >= r, the photoresist pattern no longer changes. At this time, r is considered the optical diameter. The "optical diameter" at this time is broad and applicable to surface plasmon lithography.

[0098] In the embodiment of the present application, a square with a side length of 3*r can be selected as the restricted area. All the data in the training set come from this area, and the layout segmentation during the final correction is also based on the size of this area. That is, in a possible implementation manner, the initial layout can be cut according to the optical diameter r to obtain the current target photoresist pattern, thereby reducing the computational amount of the subsequent model, saving resources, and achieving rapid optimization of the photomask pattern.

[0099] To train the initial neural network model, first, the training set of the initial neural network model can be obtained. The training set can include: the feature sizes of the historical target photoresist patterns and the feature sizes of the historical actual photoresist patterns.

[0100] Since the feature sizes of the historical target photoresist patterns and the historical mask patterns are the same, except that there will be errors after actual development and exposure. Therefore, the data in the training set are all corresponding to the original layout and the actual photoresist pattern.

[0101] For the via layer of a specific node, such as the 130nm node, the minimum size of the square hole is 130nm, and most of the squares in the layout are of a single size (i.e., 130nm). According to the following four points, design the original layout (approximate exhaustive search) within the restricted area: (1) the size of the square hole; (2) the design rules; (3) symmetry (because an annular or circular light source is usually selected during via layer exposure, and patterns with symmetric arrangements have the same exposure performance); (4) the step size.

[0102] For example, refer to Figure 8As shown, when there is only one square hole in the area, regardless of the position of the square hole, the photoresist pattern after exposure is the same, and it can be obtained by only one strict simulation (using methods such as FDTD or RCWA) or actual test pattern exposure.

[0103] At this time, divide it with 3*r = 6000nm, CD = 130nm, minimum SPACE = 130nm. The layout of this embodiment of the present application is designed based on central symmetry and axial symmetry, the step size = 10nm, and the characteristic dimensions of the photoresist pattern obtained by actual test exposure are CD_x = 100nm and CD_y = 100nm.

[0104] That is, in this embodiment of the present application, the input of the training set, that is, the historical target photoresist pattern, can be distributed in central symmetry and axial symmetry. In this way, inputting symmetric patterns results in the same photoresist pattern, which can effectively reduce the computational amount of the model and save resources.

[0105] For example, see Figure 9 As shown, when there are two square holes in the area, similarly, according to the above four limiting conditions, draw the test pattern and simulate to obtain the corresponding photoresist pattern. By analogy, all the graphic arrangements within the design rules can be drawn, and the photoresist pattern can be obtained by simulating or actually testing the pattern exposure. Establish a one-to-one correspondence between the mask pattern and the photoresist pattern, that is, a one-to-one correspondence between the characteristic dimensions of the historical target photoresist pattern and the characteristic dimensions of the historical actual photoresist pattern can be established.

[0106] Then change the CD of the square hole. For example, CD = 150nm, CD = 140nm, CD = 130nm should be determined according to the characteristics of the actual layout of the current node. In this way, a training set is established. The validation set and the test set are selected from the above test patterns and simulation results. Use the training set to learn the mapping relationship between the characteristic dimensions of the historical target photoresist pattern and the characteristic dimensions of the historical actual photoresist pattern.

[0107] Determine the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model. Optionally, the type of the neural network model provided in this embodiment of the present application may include a convolutional neural network model (Convolutional Neural Networks, CNN).

[0108] Specifically, the initial neural network model can be a typical 9-layer classification network, including an input layer, a convolutional layer 1, an activation function layer 1, a normalization layer, a convolutional layer 2, an activation function layer 2, a fully connected layer, a de-maximum layer, and a classification layer. Use the training set to train the model, and a fast model capable of predicting the photoresist pattern is obtained, that is, a pre-trained neural network model is obtained.

[0109] S105: Input the feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern;

[0110] S106: Calculate a first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern;

[0111] S107: Determine the optimization step size of the current mask pattern according to the first error value by using a multi-variable optimization algorithm;

[0112] S108: Calculate the feature size of the optimized mask pattern according to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern.

[0113] In the embodiments of the present application, in order to quickly optimize the photolithography mask pattern and reduce the pattern error in an efficient manner, the feature size of the current target photoresist pattern can be input into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern.

[0114] Then, a first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern can be calculated. According to the first error value, the optimization step size of the current mask pattern is determined by using a multi-variable optimization algorithm; according to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern, the feature size of the optimized mask pattern is calculated.

[0115] In a possible implementation manner, the first error value cost can be obtained through the following calculation method:

[0116] cost = error1 2 + error2 2 +... + error n 2 ;

[0117] cost is the first error value; error1, error2... error n are the differences between the feature sizes of the respective patterns in the current target photoresist pattern and the feature sizes of the respective patterns in the current simulated photoresist pattern; n is a positive integer.

[0118] For example, for the feature size of the first pattern in the current target photoresist pattern being 200 nm and the feature size of the corresponding pattern in the current simulated photoresist pattern being 180 nm, then error1 = 20 nm.

[0119] According to the first error value, the optimization step size of the current mask pattern is determined using a multi - variable optimization algorithm, that is, the CD change amounts d1, d2, …… dn of the current mask pattern can be obtained. According to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern, the feature size of the optimized mask pattern is calculated.

[0120] For example, referring to Figure 10 As shown, it is a schematic diagram of mask optimization provided by an embodiment of the present application. The feature size of the first pattern in the current target photoresist pattern is 200 nm, and the optimization step size d1 = 5 nm. Then the feature size of the optimized mask pattern is 205 nm, so as to minimize the error value of the final photoresist pattern, that is, Cost = minimum.

[0121] In a possible implementation manner, the surface plasmon lithography mask pattern optimization method provided by an embodiment of the present application may further include: inputting the feature size of the optimized mask pattern into a pre - trained neural network model, and the pre - trained neural network model outputs the feature size of the optimized simulated photoresist pattern;

[0122] Calculate the second error value between the feature size of the optimized mask pattern and the feature size of the optimized simulated photoresist pattern;

[0123] Compare the magnitudes of the first error value and the second error value;

[0124] When the second error value is small, then according to the second error value, use a multi - variable optimization algorithm to determine the re - optimization step size of the optimized mask pattern;

[0125] According to the feature size of the optimized mask pattern and the re - optimization step size of the optimized mask pattern, calculate the feature size of the re - optimized mask pattern.

[0126] Specifically, in an embodiment of the present application, a single optimization of the current mask pattern may not achieve an ideal optimization effect. Therefore, the current mask pattern can be optimized multiple times to achieve the optimal optimization effect.

[0127] For example, if the feature size of the optimized mask pattern is 205 nm, and the corresponding photoresist pattern after exposure is 185 nm, which still has a large difference from the feature size of the current target photoresist pattern of 200 nm, then optimization can be performed again at this time to obtain the feature size of the re - optimized mask pattern, which can be, for example, 218 nm, to further reduce the error, thereby quickly optimizing the lithography mask pattern and reducing the pattern error in an efficient manner.

[0128] Furthermore, all of the above is performed within the constraints of the "optical diameter." The actual layout to be processed is much larger than the constraints. Therefore, when the actual layout is cut, if the side length of the constraint is 3*r, the cut range is r. Assume that the actual layout is l long and w wide.

[0129] For example, see Figure 11 , which is a schematic diagram of another layout provided in an embodiment of the present application, the area of the graphic is: area = l*w, l = 1000nm, w = 1400nm.

[0130] Assuming r = 300 nm, the pattern area can be cut into 4*5=20 pieces, which ensures that the cut areas can completely cover the original pattern area.

[0131] See also Figure 12 As shown, it is a schematic diagram of another layout provided in an embodiment of the present application. The box can be translated as a whole by a movement amount (dx=dy=d) to avoid overlap at the junction as much as possible.

[0132] Calculations should be performed based on a 3*r region. For example, the area in the lower left corner should be expanded to a 3*r region. The calculation results are then truncated and all regions are calculated sequentially. The optimized full layout reduces the error between the exposed photoresist pattern and the target pattern, thus achieving the goal of mask pattern optimization.

[0133] The present invention provides a surface plasma lithography mask pattern optimization method, which includes: obtaining the characteristic size of the current target photoresist pattern; obtaining a training set of an initial neural network model, the training set including the characteristic size of the historical target photoresist pattern and the characteristic size of the historical actual photoresist pattern; using the training set to learn the mapping relationship between the characteristic size of the historical target photoresist pattern and the characteristic size of the historical actual photoresist pattern; determining the model parameters of the initial neural network model based on the mapping relationship to obtain a pre-trained neural network model; inputting the characteristic size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputting the characteristic size of the current simulated photoresist pattern; calculating a first error value between the characteristic size of the current target photoresist pattern and the characteristic size of the current simulated photoresist pattern; determining the optimization step size of the current mask pattern based on the first error value using a multivariate optimization algorithm; and calculating the characteristic size of the optimized mask pattern based on the characteristic size of the current target photoresist pattern and the optimization step size of the current mask pattern. Thus, the present invention can use the neural network model to quickly optimize the lithography mask pattern and reduce the pattern error in an efficient manner.

[0134] Exemplary device

[0135] See Figure 13 As shown in Figure 13 , it is a schematic diagram of an apparatus for optimizing a surface plasmon lithography mask pattern provided by an embodiment of the present application, including:

[0136] An acquisition unit 201, configured to acquire the feature size of the current target photoresist pattern;

[0137] A training set unit 202, configured to acquire a training set of an initial neural network model, where the training set includes: the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns;

[0138] A learning unit 203, configured to learn the mapping relationship between the feature size of the historical target photoresist pattern and the feature size of the historical actual photoresist pattern by using the training set;

[0139] A determination unit 204, configured to determine the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model;

[0140] A first input unit 205, configured to input the feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern;

[0141] A first calculation unit 206, configured to calculate a first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern;

[0142] A first step length unit 207, configured to determine the optimization step length of the current mask pattern according to the first error value by using a multi-variable optimization algorithm;

[0143] A first optimization unit 208, configured to calculate the feature size of the optimized mask pattern according to the feature size of the current target photoresist pattern and the optimization step length of the current mask pattern.

[0144] In a possible implementation manner, it further includes:

[0145] A second input unit, configured to input the feature size of the optimized mask pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the optimized simulated photoresist pattern;

[0146] A second calculation unit, configured to calculate a second error value between the feature size of the optimized mask pattern and the feature size of the optimized simulated photoresist pattern;

[0147] A comparison unit, configured to compare the magnitudes of the first error value and the second error value;

[0148] The second step length unit is configured to, when the second error value is small, determine a re-optimization step length of the optimized mask pattern according to the second error value by using a multi-variable optimization algorithm;

[0149] The second optimization unit is configured to calculate a feature size of the re-optimized mask pattern according to the feature size of the optimized mask pattern and the re-optimization step length of the optimized mask pattern.

[0150] In a possible implementation manner, the first calculation unit is specifically configured to calculate the first error value cost:

[0151] cost = error1 2 + error2 2 +... + error n 2 ;

[0152] The cost is the first error value; the error1, error2... error n is the difference between the feature sizes of the respective patterns in the current target photoresist pattern and the feature sizes of the respective patterns in the current simulated photoresist pattern; the n is a positive integer.

[0153] [[ID=2,4]]In a possible implementation manner, the type of the neural network model includes a convolutional neural network model.

[0154] The embodiments of the present application provide a surface plasmon lithography mask pattern optimization device. The method applied to the device includes: obtaining the feature size of the current target photoresist pattern; obtaining a training set of an initial neural network model, where the training set includes: the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns; learning the mapping relationship between the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns by using the training set; determining the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model; inputting the feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern; calculating a first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern; determining an optimization step length of the current mask pattern according to the first error value by using a multi-variable optimization algorithm; calculating a feature size of the optimized mask pattern according to the feature size of the current target photoresist pattern and the optimization step length of the current mask pattern. Thus, the present application can quickly optimize the lithography mask pattern by using the neural network model, and reduce the pattern error in an efficient manner.

[0155] Based on the above embodiments, an embodiment of the present application provides a surface plasmon lithography mask pattern optimization system, including:

[0156] A memory for storing a computer program;

[0157] A processor for implementing the steps of the surface plasmon lithography mask pattern optimization method as described above when executing the computer program.

[0158] Based on the above embodiments, an embodiment of the present application further provides a computer-readable medium, on which a computer program is stored, and when the computer program is processed and executed, it implements the steps of the surface plasmon lithography mask pattern optimization method as described above.

[0159] It should be noted that the computer-readable medium in the present disclosure may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two above. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which computer-readable program code is carried. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, and this computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0160] The above computer-readable medium may be included in the above system; or it may exist separately and not be assembled into the system.

[0161] In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowchart can be implemented as computer software programs. For example, an embodiment of the present disclosure includes a computer program product that includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for performing the method shown in the flowchart.

[0162] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments.

[0163] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the protection of the technical solution of the present application.

Claims

1. A method for optimizing a surface plasmon lithography mask pattern, characterized in that Including: Obtain the feature size of the current target photoresist pattern; Obtain the training set of the initial neural network model, where the training set includes: the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns; Use the training set to learn the mapping relationship between the feature sizes of the historical target photoresist pattern and the historical actual photoresist pattern; Determine the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model; Input the feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern; Calculate the first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern; According to the first error value, use a multi-variable optimization algorithm to determine the optimization step size of the current mask pattern; According to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern, calculate the feature size of the optimized mask pattern.

2. The method according to claim 1, wherein Also including: Input the feature size of the optimized mask pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the optimized simulated photoresist pattern; Calculate the second error value between the feature size of the optimized mask pattern and the feature size of the optimized simulated photoresist pattern; Compare the magnitudes of the first error value and the second error value; When the second error value is small, then according to the second error value, use a multi-variable optimization algorithm to determine the re-optimization step size of the optimized mask pattern; According to the feature size of the optimized mask pattern and the re-optimization step size of the optimized mask pattern, calculate the feature size of the re-optimized mask pattern.

3. The method according to claim 1, characterized in that The calculating the first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern includes: cost = error1 2 + error2 2 + …… + error n 2 ; The cost is the first error value; the error1, error2... error n is the difference between the feature sizes of the respective patterns in the current target photoresist pattern and the feature sizes of the respective patterns in the current simulated photoresist pattern; n is a positive integer.

4. The method according to claim 1, characterized in that, Also including: Cut the initial layout according to the optical diameter to obtain the current target photoresist pattern.

5. The method according to claim 1, characterized in that, The historical target photoresist patterns are centrosymmetric and axially symmetrically distributed.

6. A surface plasmon lithography mask pattern optimization device, characterized in that, Including: An acquisition unit for obtaining the feature size of the current target photoresist pattern; A training set unit for obtaining the training set of the initial neural network model, where the training set includes: the feature sizes of historical target photoresist patterns and the feature sizes of historical actual photoresist patterns; A learning unit for using the training set to learn the mapping relationship between the feature sizes of the historical target photoresist pattern and the historical actual photoresist pattern; A determination unit for determining the model parameters of the initial neural network model according to the mapping relationship to obtain a pre-trained neural network model; A first input unit for inputting the feature size of the current target photoresist pattern into the pre-trained neural network model, and the pre-trained neural network model outputs the feature size of the current simulated photoresist pattern; A first calculation unit for calculating a first error value between the feature size of the current target photoresist pattern and the feature size of the current simulated photoresist pattern; A first step size unit for determining an optimization step size of the current mask pattern according to the first error value by using a multi - variable optimization algorithm; A first optimization unit for calculating the feature size of the optimized mask pattern according to the feature size of the current target photoresist pattern and the optimization step size of the current mask pattern.

7. The device according to claim 6, characterized in that, It further includes: A second input unit for inputting the feature size of the optimized mask pattern into the pre - trained neural network model, and the pre - trained neural network model outputs the feature size of the optimized simulated photoresist pattern; A second calculation unit for calculating a second error value between the feature size of the optimized mask pattern and the feature size of the optimized simulated photoresist pattern; A comparison unit for comparing the magnitudes of the first error value and the second error value; A second step size unit for, when the second error value is small, determining a re - optimization step size of the optimized mask pattern according to the second error value by using a multi - variable optimization algorithm; A second optimization unit for calculating the feature size of the re - optimized mask pattern according to the feature size of the optimized mask pattern and the re - optimization step size of the optimized mask pattern.

8. The device according to claim 6, characterized in that, The first calculation unit is specifically used for calculating the first error value cost: cost = error1 2 + error2 2 + …… + error n 2 ; The cost is the first error value; the error1, error2... error n is the difference between the feature sizes of the respective patterns in the current target photoresist pattern and the feature sizes of the respective patterns in the current simulated photoresist pattern; Where n is a positive integer.

9. A surface plasmon lithography mask pattern optimization system, characterized in that, It includes: A memory for storing a computer program; A processor for implementing the steps of the surface plasmon lithography mask pattern optimization method as described in any one of claims 1 - 4 when executing the computer program.

10. A computer-readable medium, characterized in that, A computer program is stored on the computer - readable medium, and when the computer program is processed and executed, the steps of the surface plasmon lithography mask pattern optimization method as described in any one of claims 1 - 4 are implemented.

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