Chip and power consumption management method thereof, and electronic device

Abstract

A chip and a power consumption management method and an electronic device thereof. The chip comprises: a data bus and a control bus; a plurality of functional modules, respectively configured to be connected to the data bus and the control bus, and to transmit data through the data bus; a distributed power consumption and temperature monitoring network, distributed in the chip and configured to collect activity data and temperature data of the chip; a power consumption management processing unit, configured to receive activity data and temperature data through the control bus, calculate the power consumption data of the chip based on the activity data and temperature data, and output a control signal for adjusting the data transmission bandwidth between the plurality of functional modules and the data bus based on the power consumption data; and a plurality of throttling switches, configured to respectively adjust the data transmission bandwidth between the plurality of functional modules and the data bus based on the control signal. The chip has improved power consumption management performance.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a chip, a power consumption management method thereof, and an electronic device. Background Art

[0002] With the improvement of chip manufacturing technology, for example, the scale of CPU processor chips is getting larger and the frequency of operation is getting faster, power consumption and temperature have become key factors that cannot be ignored. When the current consumption of the CPU chip is too large or the current fluctuation is too large and exceeds the upper limit of the power supply capacity of the motherboard and package, it will cause voltage instability, which will cause the CPU chip to work incorrectly; if the high current lasts too long and exceeds the upper limit of the heat dissipation capacity of the motherboard and package, it will cause the temperature to rise and may even cause the CPU chip to burn out. Current CPU chips usually implement an adaptive power management system on the chip, which monitors the current chip active events through the collaboration of the firmware and hardware inside the CPU chip, and automatically adjusts the chip current, power consumption and temperature. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a chip, which includes: a data bus and a control bus; multiple functional modules, respectively configured to be connected to the data bus and the control bus, and to transmit data through the data bus; a distributed power consumption and temperature monitoring network, distributed in the chip and configured to collect activity data and temperature data of the chip; a power consumption management processing unit, configured to receive the activity data and the temperature data through the control bus, calculate the power consumption data of the chip based on the activity data and the temperature data, and output a control signal for adjusting the data transmission bandwidth between the multiple functional modules and the data bus based on the power consumption data; and multiple throttling switches, configured to respectively adjust the data transmission bandwidth between the multiple functional modules and the data bus based on the control signal.

[0004] For example, in the chip of at least one embodiment, the multiple functional modules include one or more of a processor core, a main memory controller, a peripheral controller, and a chip connector.

[0005] For example, in the chip of at least one embodiment, the activity data includes a plurality of counts of the number of operations of each of the plurality of functional modules.

[0006] For example, in at least one embodiment of the chip, the distributed power consumption and temperature monitoring network includes multiple counters distributed in the multiple functional modules, and is further configured to count the operations of each of the multiple functional modules through the multiple counters, and to collect and count the count values ​​of the operations of each of the multiple functional modules through the control bus.

[0007] For example, in the chip of at least one embodiment, the distributed power consumption and temperature monitoring network further includes one or more temperature sensors disposed in the chip to collect temperature data of the chip.

[0008] For example, in at least one embodiment of the chip, the power consumption management processing unit is also configured to configure the distributed power consumption and temperature detection network, including: specifying the functional modules that need to be detected; specifying the counters that need to be enabled; and specifying the temperature sensors that need to be detected.

[0009] For example, in at least one embodiment of the chip, the power consumption management processing unit is further configured to count the types and numbers of activities of the chip in a period of time before the current time and the real-time temperature, and calculate the current power consumption value of the chip based on the power consumption weights of different types of activities of the chip at the real-time temperature.

[0010] For example, in the chip of at least one embodiment, the plurality of throttling switches are respectively arranged between the plurality of functional modules and the data bus.

[0011] For example, in at least one embodiment of the chip, each of the multiple throttling switches includes an enable register, a throttling number register and a throttling control valve, the enable register is enabled or disabled based on the power consumption data, the throttling number register sends a throttling control number signal to the throttling control valve based on whether the enable register is enabled, and the throttling control valve respectively adjusts the data transmission bandwidth between the multiple functional modules and the data bus based on the throttling control number signal.

[0012] For example, in at least one embodiment of the chip, the power management processing unit is further configured to perform the following operations on the selected throttle switch: configure the throttle number register, wherein the throttle number register includes a first register for the throttle number when the power consumption is not exceeded and a second register for the throttle number when the power consumption is exceeded; when the chip power consumption is not exceeded, configure the enable register to be disabled, and the throttle control number N received by the throttle control valve is equal to the configuration value of the first register; and when the chip power consumption is exceeded, configure the enable register to be enabled, and the throttle control number N received by the throttle control valve is equal to the configuration value of the second register. The throttle control valve is configured to adjust the data transmission bandwidth through the selected throttle switch based on the throttle control number N, where N is an integer greater than or equal to 0.

[0013] For example, in a chip of at least one embodiment, when the functional module is a processing core, for the throttling switch used for the processing core, the throttling control number is the throttling number of memory access instructions, the number of memory access instructions received by the throttling control valve from the processing core is M, and the number of memory access instructions released by the throttling control valve to the data bus is MN, wherein N is an integer greater than or equal to 0, and M is an integer greater than or equal to 0, and when N is greater than or equal to M, the number of memory access instructions is 0.

[0014] For example, in at least one embodiment of the chip, when the functional module is a main memory controller, for the throttling switch used for the main memory controller, the throttling control number is the throttling number of memory access instructions, the number of memory access requests received by the throttling control valve from the data bus is M, and the number of memory access requests allowed by the throttling control valve from the data bus to the main memory controller is MN, wherein N is an integer greater than or equal to 0, and M is an integer greater than or equal to 0, and when N is greater than or equal to M, the number of memory access requests is 0.

[0015] For example, in a chip of at least one embodiment, when the functional module is a chip connector, for the throttling switch used for the chip connector, the throttling control number is the cross-chip data request throttling number, the number of data requests received by the throttling control valve from the chip connector is M, and the number of data requests released by the throttling control valve to the data bus is MN, wherein N is an integer greater than or equal to 0, and M is an integer greater than or equal to 0, and when N is greater than or equal to M, the number of data requests is 0.

[0016] For example, in a chip of at least one embodiment, the value of the first register and the value of the second register are the same or different.

[0017] For example, in the chip of at least one embodiment, the power consumption management processing unit is further configured to configure different bandwidths based on the priorities of data paths between different functional modules and the data bus.

[0018] At least one embodiment of the present disclosure provides an electronic device, which includes the chip as described in any of the above embodiments.

[0019] At least one embodiment of the present disclosure provides a power consumption management method for a chip, comprising: a distributed power consumption and temperature monitoring network distributed in the chip collects activity data and temperature data of the chip, and sends the activity data and the temperature data to a power consumption management processing unit through a control bus; the power consumption management processing unit calculates the power consumption data of the chip based on the activity data and the temperature data, and outputs a control signal for adjusting the data transmission bandwidth between multiple functional modules and a data bus based on the power consumption data; and multiple throttling switches respectively adjust the data transmission bandwidth between the multiple functional modules and the data bus based on the control signal.

[0020] For example, in at least one embodiment of the power consumption management method, the power consumption management method further includes: the distributed power consumption and temperature monitoring network counts the operations of each of the multiple functional modules through multiple counters, and collects and counts the count values ​​of the operations of each of the multiple functional modules through the control bus, wherein the multiple functional modules include one or more of a processor core, a main memory controller, a peripheral controller, and a chip connector, the activity data includes multiple counts of the various operation times of the multiple functional modules, and the distributed power consumption and temperature monitoring network includes multiple counters distributed among the multiple functional modules.

[0021] For example, in at least one embodiment of the power consumption management method, the power consumption management method also includes: the power consumption management processing unit counts the types and numbers of activities of the chip in a period of time before the current time and the real-time temperature, and calculates the current power consumption value of the chip based on the power consumption weights of different types of activities of the chip at the real-time temperature.

[0022] For example, in at least one embodiment of the power consumption management method, a plurality of throttle switches are used to adjust the data transmission bandwidth between the plurality of functional modules and the data bus based on the control signal, including: the power consumption management processing unit performs the following operations on the throttle switch selected from the plurality of throttle switches respectively provided in the plurality of functional modules and the data bus:

[0023] The throttling number register of the selected throttling switch is configured, wherein the throttling number register includes a first register for the throttling number when the power consumption is not exceeded and a second register for the throttling number when the power consumption is exceeded, and the value of the first register is the same as or different from the value of the second register.

[0024] When the power consumption of the chip does not exceed the standard, the enable register of the selected throttle switch is configured to be disabled, and the throttle control number N received by the throttle control valve of the selected throttle switch is equal to the configuration value of the first register,

[0025] When the power consumption of the chip exceeds the standard, the enable register is configured to be enabled, and the throttling control number N received by the throttling control valve of the selected throttling switch is equal to the configuration value of the second register,

[0026] The throttle control valve is enabled to adjust a data transmission bandwidth through the selected throttle switch based on the throttle control number N, where N is an integer greater than or equal to 0.

[0027] For example, in at least one embodiment of the power consumption management method, the power consumption management method further includes: the power consumption management processing unit configures different bandwidths based on priorities of data paths between different functional modules and the data bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0029] Figure 1 An exemplary chip architecture diagram is shown.

[0030] Figure 2 An architectural diagram of a throttle switch located at the core-to-data bus interface is shown.

[0031] Figure 3 An architectural diagram of a throttle switch located at the interface between the main memory controller and the data bus is shown.

[0032] Figure 4 An architectural diagram of a throttle switch located at the chip connector and data bus interface is shown.

[0033] Figure 5 A power consumption management method for a chip provided by at least one embodiment of the present disclosure is shown.

[0034] Figure 6 A schematic diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0036] At present, when the system performance and power consumption are reduced by adjusting the frequency, the clock frequency in the chip circuit is usually generated by an analog circuit such as a phase-locked loop (PLL). When the phase-locked loop reduces the frequency, it takes a long adjustment time (for example, microseconds) to stabilize the frequency output, and various data caches and asynchronous interface designs in the chip often have specific requirements for the clock frequency. Before adjusting its clock frequency, a variety of preparations and configuration changes are required to ensure that its normal function does not fail due to frequency changes. In order to leave enough adjustment time for frequency adjustment, it is often necessary to set a lower adjustment threshold. It is necessary to start reducing the chip frequency and performance long before the current consumption exceeds the power supply capacity or the power consumption exceeds the heat dissipation capacity, leaving more redundant safety margins for the power supply capacity and heat dissipation capacity. However, this causes performance waste. When the power supply peak is relieved and the CPU chip needs to restore performance, the PLL frequency increase also requires a long adjustment time (for example, microseconds) to stabilize the frequency output. Because the frequency adjustment time is long, the use of the frequency modulation mechanism to reduce power consumption and stabilize power supply is suitable for scenarios where the CPU load does not change drastically, so it is not suitable as an emergency mechanism in scenarios where the voltage suddenly fluctuates drastically.

[0037] In addition, some system clocks, such as data bus clocks, are often global clocks. Slowing down their clock speed will indiscriminately affect the bandwidth and throughput of all data paths, so that both high-priority data transmission and low-priority data transmission will be affected at the same time, making it impossible to allocate power consumption to high-priority data transmission tasks in a targeted manner.

[0038] The inventor of the present disclosure proposed in the research that in order to improve the response speed of current regulation, the bandwidth of the data path specified in the CPU chip can be limited, and throttling switches can be set at the data bus entrance and exit to reduce the data throughput of the data path specified in the SOC, thereby quickly reducing the power consumption and heat dissipation of the SOC. This technical solution does not require adjusting the clock frequency, has a simple configuration and takes effect quickly, and the response time and exit time can both be in the nanosecond level. It is suitable as an emergency mechanism in the scenario of sudden and drastic voltage fluctuations, and different thresholds can be set for the throttling switches of different data transmission paths, and different power consumption proportions can be allocated to data paths of different priorities.

[0039] Based on the above understanding, at least one embodiment of the present disclosure provides a chip, which includes: a data bus and a control bus, multiple functional modules, a distributed power consumption and temperature monitoring network, a power consumption management processing unit, and multiple throttling switches. Multiple functional modules are respectively configured to be connected to the data bus and the control bus, and data is transmitted through the data bus; the distributed power consumption and temperature monitoring network is distributed in the chip and is configured to collect the activity data and temperature data of the chip; the power consumption management processing unit is configured to receive the activity data and temperature data through the control bus, calculate the power consumption data of the chip based on the activity data and the temperature data, and output a control signal for adjusting the data transmission bandwidth between the multiple functional modules and the data bus based on the power consumption data; multiple throttling switches are configured to adjust the data transmission bandwidth between the multiple functional modules and the data bus respectively based on the control signal.

[0040] The chip provided by the above-mentioned embodiments of the present disclosure can specifically adjust the bandwidth for different data paths, thereby quickly adjusting the chip power consumption while giving priority to ensuring the performance and delay of high-priority data transmission.

[0041] At least one embodiment of the present disclosure further provides a power consumption management method corresponding to the above chip and an electronic device including the above chip.

[0042] The technical effects of the power consumption management method and the electronic device of the above embodiments are the same as the technical effects of the above chip.

[0043] Various embodiments of the present disclosure will be described below with reference to specific examples.

[0044] Figure 1 FIG. 1 shows an exemplary chip architecture diagram according to at least one embodiment of the present disclosure. Figure 1 As shown, the chip may include a data bus 101 and a control bus 102, multiple functional modules, a distributed power consumption and temperature monitoring network 103, a power consumption management processing unit 104 and multiple throttling switches.

[0045] like Figure 1 As shown, for example, the plurality of throttle switches may include throttle switches 201, 202, 203, and 204, and the plurality of functional modules may include a core 108, a chip connector 105, a main memory controller 106, and a peripheral controller 107, etc., wherein the core 108, the chip connector 105, the main memory controller 106, or the peripheral controller 107 may be any suitable number. At the same time, the system, for example, provides private caches (e.g., first level (L1) caches) for the plurality of cores 108 respectively, and may also provide a shared cache (last level cache (LLC)) that can be shared by the plurality of cores 108.

[0046] like Figure 1As shown, the chip may have N (N is an integer greater than or equal to 1) cores 108, a chip connector 105, a main memory controller 106 or a peripheral controller 107. Here, the core 108 refers to the processor core in the chip as the computing core. For example, the core 108 may have a variety of possible architectures, such as X86, ARM, RISC-V, etc.; a die refers to a small chip bare chip with different functions or different processes, which can be interconnected and packaged together to form a chip system; a chip connector 105 refers to a connection technology used to interconnect the chips together, usually using a high-speed serial-to-parallel converter (Serdes) PHY, and follows a set of specific data transmission protocols. Common standards in the industry include UCIE (Universal Chiplet Interconnect Express); the main memory controller 106 is used to mount the system memory, that is, the system memory is connected to the chip through the main memory controller 106; the peripheral controller 107 can be used to mount storage media, such as hard disks, network interfaces, etc.

[0047] like Figure 1 As shown, multiple functional modules are respectively connected to the data bus 101 and the control bus 102, and data and the like are transmitted through the data bus 101, and addresses and control information and the like are transmitted through the control bus 102. For example, the core 108, the chip connector 105, the main memory controller 106, and the peripheral controller 107 are respectively connected to the data bus 101 and the control bus 102, and the core 108, the chip connector 105, the main memory controller 106, and the peripheral controller 107 can communicate with each other through the data bus 101 and the control bus 102, and perform transmission of a large amount of data, addresses, and control signals.

[0048] For example, in at least one embodiment, the distributed power consumption and temperature monitoring network 103 is distributed in the chip and configured to collect the activity data and temperature data of the chip. For example, the distributed power consumption and temperature monitoring network 103 also includes one or more temperature sensors arranged in the chip to collect the temperature data of the chip. For example, for the distributed power consumption and temperature monitoring network 103, one or more temperature sensors corresponding to each of the multiple functional modules can be arranged, the one or more temperature sensors can be coupled to the control bus 102, and the one or more temperature sensors send the measured temperature information to, for example, the power consumption management processing unit 104 through the control bus 102. In at least one example, the power consumption management processing unit can be a power consumption management microprocessor, for example, the power consumption management microprocessor includes a configured firmware. The embodiments of the present disclosure do not limit the type, structure, etc. of the temperature sensor.

[0049] For example, in at least one embodiment, the distributed power consumption and temperature monitoring network 103 also includes multiple counters distributed in multiple functional modules. For example, each functional module may be arranged with one or more counters, and the counter automatically counts when the chip is active to obtain the activity data of the chip, and the activity data is regularly collected through the control bus. For example, the counter can count the types and times of different activities in the chip. For example, the "activity" mentioned here refers to any operation in the chip, and different IPs or modules have different functions, and their "activities" are also different. For example, the operation or activity of the kernel 108 can be addition, subtraction, multiplication, division, instruction fetching, decoding operations, etc., and the operation or activity of the main memory is usually various commands to read and write data. The operation of the bus is data transmission in various directions. For example, the power consumption generated by different operations at a time may be the same or different, that is, at a specific chip temperature, different operations performed by different modules in the chip may have the same or different power consumption, and different operations of different functional modules or different operations in the same functional module may have the same or different power consumption weight values. The embodiments of the present disclosure do not limit the type, structure, etc. of the counter.

[0050] For example, in at least one embodiment, the distributed power consumption and temperature monitoring network 103 is further configured to count the operations of the multiple functional modules respectively through multiple counters, and collect and count the count values ​​of the operations of the multiple functional modules respectively through the control bus 102.

[0051] For example, in at least one embodiment, the power consumption management processing unit 104 is configured to receive activity data and temperature data through a control bus, calculate the power consumption data of the chip based on the activity data and the temperature data, and output a control signal for adjusting the data transmission bandwidth between multiple functional modules and the data bus based on the power consumption data.

[0052] For example, in at least one embodiment, the power consumption value within a period of time at different temperatures can be obtained when simulating and testing the above-mentioned chip, and the types and numbers of chip activities within a period of time corresponding to the power consumption value can be counted, and the power consumption weight corresponding to each activity is calculated and stored in the chip's non-volatile storage space, for example. During the actual use of the chip, the power consumption management processing unit 104 can count the types and numbers of different activities in a recent period of time, combined with their power consumption weights, to calculate the current power consumption value of the chip.

[0053] For example, in at least one embodiment, the power consumption of the chip can be estimated by an EDA tool, or it can be measured on the chip, and the number of various activities can be obtained by an on-chip counter. For example, different power consumption values ​​of the chip are measured for different scenarios (e.g., different applications), and the counts of different types of activities may be different. A multivariate linear equation can be established through the power consumption values, activity types, and activity counts of the chip in different scenarios, and the multivariate linear equation can be solved, and the solved value can be normalized to obtain the power consumption weight of each activity.

[0054] For example, in at least one embodiment, a plurality of throttle switches are respectively disposed between a plurality of functional modules and a data bus. For example, a plurality of throttle switches are configured to adjust the data transmission bandwidth between a plurality of functional modules and the data bus 101 based on a control signal. For example, when the power consumption exceeds a specific threshold, the power consumption management processing unit 104 takes adjustment measures to limit the data transmission rate of different paths through different throttle switches, thereby achieving the purpose of controlling power consumption.

[0055] For example, in at least one embodiment, the power management processing unit 104 is further configured to configure the distributed power consumption and temperature detection network 103, for example, these configuration operations include: specifying the functional modules to be detected; specifying the counters to be enabled; and specifying the temperature sensors to be detected. For example, the power management processing unit 104 can select one or more specific functional modules for detection according to actual needs, and enable the counters of the functional modules to be detected, so as to obtain the count values ​​of various operations of the functional modules to be detected. For example, the power management processing unit 104 can select one or more specific temperature sensors for temperature detection according to actual needs to obtain, for example, the real-time temperature value of the chip.

[0056] Figure 2 An architectural diagram of a throttle switch 201 at the interface between the core 108 and the data bus 101 is shown according to at least one example. Figure 3 An architectural diagram of a throttle switch 203 located at the interface between the main memory controller 106 and the data bus 101 is shown according to at least one example. Figure 4 An architectural diagram of a throttle switch 202 located at the interface of a chip connector 105 and a data bus 101 is shown according to at least one example.

[0057] For example, in at least one embodiment, each of the plurality of throttling switches includes an enable register, a throttling number register, and a throttling control valve. The enable register is enabled or disabled based on the power consumption data, the throttling number register sends a throttling control number signal to the throttling control valve based on whether the enable register is enabled, and the throttling control valve adjusts the data transmission bandwidth between the plurality of functional modules and the data bus based on the throttling control number signal, wherein the throttling number register includes a first register for the throttling number when the power consumption is not exceeded and a second register for the throttling number when the power consumption is exceeded.

[0058] For example, Figure 2 In the exemplary structure of the throttling switch 201 shown, the enable register may be an enable register 301 for triggering throttling when power consumption exceeds the standard, the first register may be a throttling number register 302 when power consumption does not exceed the standard, the second register may be a throttling number register 303 when power consumption exceeds the standard, and the throttling control valve may be a memory access instruction emission threshold gate 304. The enable register 301 for triggering throttling when power consumption exceeds the standard may be enabled or disabled based on power consumption data, and the throttling number register 303 when power consumption exceeds the standard or the throttling number register 302 when power consumption does not exceed the standard may send a throttling control number signal to the memory access instruction emission threshold gate 304 based on whether the enable register 301 for triggering throttling when power consumption exceeds the standard is enabled. The memory access instruction emission threshold gate 304 adjusts the data transmission bandwidth between the core and the data bus 101 based on the throttling control number signal.

[0059] Although Figure 2 2 shows that the throttle switch 201 is located at the periphery of the core 108 , but the embodiments of the present disclosure are not limited thereto. For example, the throttle switch 201 may also be located inside the core 108 .

[0060] For example, Figure 3 In the exemplary structure of the throttling switch 203 shown, the enable register may be an enable register 401 for triggering throttling when power consumption exceeds the standard, the first register may be a throttling number register 402 when power consumption does not exceed the standard, the second register may be a throttling number register 403 when power consumption exceeds the standard, and the throttling control valve may be a memory access command receiving threshold gate 404. The enable register 401 for triggering throttling when power consumption exceeds the standard may be enabled or disabled based on power consumption data, and the throttling number register 403 when power consumption exceeds the standard or the throttling number register 402 when power consumption does not exceed the standard may send a throttling control number signal to the memory access command receiving threshold gate 404 based on whether the enable register 401 for triggering throttling when power consumption exceeds the standard is enabled. The memory access command receiving threshold gate 404 adjusts the data transmission bandwidth between the main memory controller 106 and the data bus 101 based on the throttling control number signal.

[0061] Although Figure 3FIG. 2 shows that the throttle switch 203 is located outside the main memory controller 106 , but the embodiments of the present disclosure are not limited thereto. For example, the throttle switch 203 may also be located inside the main memory controller 106 .

[0062] For example, Figure 4 In the exemplary structure of the throttling switch 202 shown, the enable register may be an enable register 501 for triggering throttling when power consumption exceeds the standard, the first register may be a throttling number register 502 when power consumption does not exceed the standard, the second register may be a throttling number register 503 when power consumption exceeds the standard, and the throttling control valve may be a data request receiving threshold gate 504. The enable register 501 for triggering throttling when power consumption exceeds the standard may be enabled or disabled based on power consumption data, and the throttling number register 503 when power consumption exceeds the standard or the throttling number register 502 when power consumption does not exceed the standard may send a throttling control number signal to the data request receiving threshold gate 504 based on whether the enable register 501 for triggering throttling when power consumption exceeds the standard is enabled. The data request receiving threshold gate 504 adjusts the data transmission bandwidth between the chip connector 105 and the data bus 101 based on the throttling control number signal.

[0063] Although Figure 4 2 shows that the throttle switch 202 is located at the periphery of the chip connector 105 , but the embodiments of the present disclosure are not limited thereto. For example, the throttle switch 202 may also be located inside the chip connector 105 .

[0064] For example, in at least one embodiment, the power consumption management processing unit 104 is further configured to perform the following operations on the selected throttling switch: configure the throttling number register, and when the chip power consumption does not exceed the standard, configure the enable register to be disabled (for example, the value of the enable register is 0), and the throttling control number N received by the throttling control valve is equal to the configuration value of the first register; and when the chip power consumption exceeds the standard, configure the enable register to be enabled (for example, the value of the enable register is 1), and the throttling control number N received by the throttling control valve is equal to the configuration value of the second register.

[0065] For example, Figure 2 As shown, after the chip is powered on, the power consumption management processing unit can configure the throttling number register 302 when the power consumption is not exceeded and the throttling number register 303 when the power consumption exceeds the standard to have the same or different values ​​through the control bus 102, and then collect chip activity data and temperature data from the distributed power consumption and temperature monitoring network 103 through the control bus 102, and use this to calculate the real-time power consumption of the chip.

[0066] For example, Figure 3As shown, after the chip is powered on, the power management processing unit 104 can configure the throttling number register 402 when the power consumption is not exceeded and the throttling number register 403 when the power consumption exceeds the standard to have the same or different values ​​through the control bus 102, and then collect chip activity data and temperature data from the distributed power consumption and temperature monitoring network 103 through the control bus 102, and use this to calculate the real-time power consumption of the chip.

[0067] For example, Figure 4 As shown, after the chip is powered on, the power management processing unit 104 can configure the throttling number register 502 when the power consumption is not exceeded and the throttling number register 503 when the power consumption exceeds the standard to have the same or different values ​​through the control bus 102, and then collect chip activity data and temperature data from the distributed power consumption and temperature monitoring network 103 through the control bus 102, and use this to calculate the real-time power consumption of the chip.

[0068] For example, when the real-time power consumption of the chip does not exceed the standard, the power consumption management processing unit 104 configures the enable register for triggering throttling due to excessive power consumption to be disabled. At this time, the throttling control number N received by the throttling control valve is equal to the configuration value of the throttling number register when the power consumption does not exceed the standard; when the real-time power consumption of the chip exceeds the standard, the power consumption management processing unit 104 configures the enable register for triggering throttling due to excessive power consumption to be enabled. At this time, the throttling control number N received by the throttling control valve is equal to the configuration value of the throttling number register when the power consumption exceeds the standard.

[0069] For example, the throttle control valve is configured to adjust a data transmission bandwidth through a selected throttle switch based on a throttle control number N, where N is an integer greater than or equal to zero.

[0070] For example, Figure 2 As shown, in at least one embodiment, for example, when the functional module is the core 108, for the throttling switch 201 for the core 108, the throttling control number is the throttling number of memory access instructions, the number of memory access instructions received by the memory access instruction transmitting valve 304 from the core 108 is M, and the number of memory access instructions released by the memory access instruction transmitting valve 304 to the data bus 101 is MN, wherein N is an integer greater than or equal to 0, and M is an integer greater than or equal to zero, and when N is greater than or equal to M, MN is 0, that is, the throttling control valve does not release any memory access instructions to the data bus.

[0071] For example, Figure 3As shown, in at least one embodiment, for example, when the functional module is the main memory controller 106, for the throttling switch 203 for the main memory controller 106, the throttling control number is the throttling number of memory access instructions, the number of memory access requests received by the memory access instruction receiving valve 404 from the data bus 101 is M, and the number of memory access requests allowed by the memory access instruction receiving valve 404 from the data bus 101 to the main memory controller 106 is MN, wherein N is an integer greater than or equal to 0, and M is an integer greater than or equal to zero, and when N is greater than or equal to M, MN is 0, that is, the throttling control valve does not release any memory access instructions to the main memory controller.

[0072] For example, Figure 4 As shown, in at least one embodiment, for example, when the functional module is a chip connector 105, for the throttling switch 202 for the chip connector 105, the throttling control number is the cross-chip data request throttling number, the number of data requests received by the data request receiving valve 504 from the chip connector 105 is M, and the number of data requests released by the data request receiving valve 504 to the data bus 101 is MN, wherein N is an integer greater than or equal to 0, and M is an integer greater than or equal to zero, and when N is greater than or equal to M, MN is 0, that is, the throttling control valve does not release any request from the chip connector to enter the current chip.

[0073] For example, in at least one embodiment, the power management processing unit 104 is further configured to configure different bandwidths based on the priorities of the data paths between different functional modules and the data bus 101. For example, the performance of the core 108 is very sensitive to the memory access latency, and a larger bandwidth is usually reserved for the path of the core 108; for example, the importance of peripherals in the system is usually low, and the latency is originally large, and the system performance is not very sensitive to the peripheral latency. When the power consumption is too high, it is usually prioritized to limit the memory access bandwidth of the peripherals and allocate a lower power consumption ratio to the peripherals.

[0074] For example, the power management unit 104 limits the bandwidth of the corresponding functional module and the data bus 101 through a pre-configured throttling control number N. The value of the throttling control number N can be dynamically adjusted through firmware. The firmware can define different chip power consumption states P0, P1 and P2, etc. The combination of throttling control number N values ​​of different modules in different states is different, triggering different state jumps at different temperatures.

[0075] For example, in the P0 state, the throttling control number N of all modules can be configured to 0, and the bandwidth of any module is not limited, performance is prioritized, and power consumption is maximized. For example, in the P1 state, the bandwidth of some peripherals can be limited, and the throttling control number N can be configured to a positive number. At this time, the kernel and main memory have higher priority than peripherals. When the temperature is too high in the P0 state, the firmware triggers the CPU chip to enter the P1 state, and the bandwidth of the peripherals is reduced, thereby saving some power consumption and reducing the temperature. For example, in the P2 state, the bandwidth of peripherals, kernels, and main memory can be limited at the same time, which has the greatest impact on performance, but also the smallest power consumption.

[0076] One or more embodiments of the present disclosure are not limited to the above-mentioned setting method, and the definitions of various state combinations and throttling control number N values ​​are not limited to the above-mentioned ones. On the basis of the present disclosure, the bandwidth of specific functional modules can be limited or not according to actual conditions, and the bandwidth of specific functional modules can be restricted to different degrees according to different power consumption states of the chip.

[0077] For example, in at least one embodiment, a power consumption management method corresponding to the above chip is provided. As described above, the chip includes multiple functional modules, a distributed power consumption and temperature monitoring network 103, a power consumption management processing unit 104 and multiple throttling switches.

[0078] Figure 5 FIG. 1 is a flow chart of a method for managing power consumption of a chip according to at least one embodiment of the present disclosure. Figure 5 As shown, the power consumption management method 100 includes the following steps S101 to S103:

[0079] Step S101: The distributed power consumption and temperature monitoring network distributed in the chip collects the activity data and temperature data of the chip, and sends the activity data and temperature data to the power consumption management processing unit through the control bus;

[0080] Step S102: the power management processing unit calculates power consumption data of the chip based on the activity data and the temperature data, and outputs a control signal for adjusting the data transmission bandwidth between the plurality of functional modules and the data bus based on the power consumption data; and

[0081] Step S103: the plurality of throttling switches respectively adjust the data transmission bandwidth between the plurality of functional modules and the data bus based on the control signal.

[0082] For example, refer to Figures 1 to 5For the above step S101, the distributed power consumption and temperature monitoring network 103 distributed in the chip collects the activity data and temperature data of the chip, and sends the activity data and temperature data to the power management processing unit 104 through the control bus 102. Step S101 can be implemented by the above chip, and for specific instructions, reference can be made to the description of the distributed power consumption and temperature monitoring network 103, the control bus 102, the power management processing unit 104, etc. in the embodiment of the above chip.

[0083] For example, refer to Figures 1 to 5 For the above step S102, the power management processing unit 104 calculates the power consumption data of the chip based on the activity data and the temperature data, and outputs a control signal for adjusting the data transmission bandwidth between the multiple functional modules and the data bus 101 based on the power consumption data. Step S102 can be implemented by the above chip, and for specific descriptions, reference can be made to the description of the power management processing unit 104, multiple functional modules, data bus 101, etc. in the embodiment of the above chip.

[0084] For example, refer to Figures 1 to 5 For the above step S103, multiple throttling switches respectively adjust the data transmission bandwidth between multiple functional modules and the data bus 101 based on the control signal. Step S103 can be implemented by the above chip, and the specific description can refer to the description of multiple throttling switches, multiple functional modules, data bus 101, etc. in the embodiment of the above chip.

[0085] For example, in at least one embodiment of the power consumption management method, the power consumption management method further includes: the distributed power consumption and temperature monitoring network 103 counts the operations of the multiple functional modules respectively through multiple counters, and collects and counts the count values ​​of the operations of the multiple functional modules respectively through the control bus 102. The method can be implemented by the above chip, and the specific description can refer to the description of the distributed power consumption and temperature monitoring network 103, multiple counters, multiple functional modules, control bus 102, etc. in the embodiment of the above chip.

[0086] For example, in at least one embodiment of the power management method, the power management processing unit 104 performs the following operations: specifying a functional module to be detected; specifying a counter to be enabled; and specifying a temperature sensor to be detected. The above operations can be implemented by the above chip, and for specific descriptions, reference can be made to the description of the power management processing unit 104, etc. in the embodiment of the above chip.

[0087] For example, in at least one embodiment of the power consumption management method, the power consumption management method further includes: the power consumption management processing unit 104 counts the types and number of activities of the chip in a period of time before the current time and the real-time temperature, and calculates the current power consumption value of the chip based on the power consumption weights of different types of activities of the chip at the real-time temperature. The method can be implemented by the above chip, and the specific description can refer to the description of the power consumption management processing unit 104, etc. in the embodiment of the above chip.

[0088] For example, in at least one embodiment of the power management method, the power management method further includes: the power management processing unit 104 configures different bandwidths based on the priorities of the data paths between different functional modules and the data bus 101. The method can be implemented by the above chip, and for specific descriptions, reference can be made to the description of the power management processing unit 104, functional modules, data bus 101, etc. in the embodiments of the above chip.

[0089] The power consumption management method provided by the above-mentioned embodiments of the present disclosure can adjust the bandwidth in a targeted manner for different data paths, thereby quickly adjusting the chip power consumption while giving priority to ensuring the performance and delay of high-priority data transmission.

[0090] For example, in at least one embodiment, the present disclosure further provides an electronic device, which includes a chip according to any of the embodiments described above.

[0091] Figure 6 A schematic diagram of an electronic device provided for at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may be, but is not limited to, a mobile terminal such as a notebook computer, a PDA (personal digital assistant), a PAD (tablet computer), etc., and a fixed terminal such as a desktop computer.

[0092] Figure 6 The electronic device 1000 shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure. Figure 6 As shown, in some examples, the electronic device 1000 includes a processing device 1001, which includes a chip according to any embodiment of the present disclosure, and the processing device 1001 can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 to a random access memory (RAM) 1003, such as the power consumption management method of at least one embodiment of the present disclosure. In RAM 1003, various programs and data required for the operation of the computer system are also stored. The processing device 1001, ROM 1002 and RAM 1003 are connected to each other through a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0093] For example, the following peripherals may be connected to the I / O interface 1005: input devices 1006 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1008 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009 including, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. A removable storage medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that the computer program read therefrom is installed into the storage device 1008 as needed.

[0094] Although Figure 6 The electronic device 1000 is shown to include various devices, but it should be understood that it is not required to implement or include all of the devices shown, and for example, more or fewer devices may be implemented or included instead.

[0095] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0096] The technical effects of the chip, electronic device and chip power consumption management method provided by the above-mentioned embodiments of the present disclosure can all be achieved by adjusting the bandwidth of the transmission channel connecting the functional modules and the data bus in the chip through a throttling switch, adjusting the data throughput of the data bus in the chip and with different functional modules, thereby quickly adjusting the power consumption and heat dissipation of the chip.

[0097] There are a few points to note about this disclosure:

[0098] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0099] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0100] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A chip, comprising: Data bus and control bus; A plurality of functional modules are respectively configured to be connected to the data bus and the control bus and to perform data transmission via the data bus; a distributed power consumption and temperature monitoring network distributed in the chip and configured to collect activity data and temperature data of the chip; a power management processing unit configured to receive the activity data and the temperature data through the control bus, calculate the power consumption data of the chip based on the activity data and the temperature data, and output a control signal for adjusting the data transmission bandwidth between the plurality of functional modules and the data bus based on the power consumption data; as well as a plurality of throttling switches, configured to directly adjust the data transmission bandwidth between the plurality of functional modules and the data bus respectively based on the control signal, Wherein, different throttle switches are configured to adjust different functional modules, and Wherein, the multiple throttling switches are respectively arranged between the multiple functional modules and the data bus.

2. The chip according to claim 1, wherein: The multiple functional modules include one or more of a processor core, a main memory controller, a peripheral controller, and a chip connector.

3. The chip according to claim 1, wherein: The activity data includes a plurality of counts of the number of operations of each of the plurality of functional modules.

4. The chip according to claim 3, wherein: The distributed power consumption and temperature monitoring network includes multiple counters distributed in the multiple functional modules, and is further configured to count the operations of each of the multiple functional modules through the multiple counters, and to collect and count the count values ​​of the operations of each of the multiple functional modules through the control bus.

5. The chip according to claim 4, wherein: The distributed power consumption and temperature monitoring network further includes one or more temperature sensors disposed in the chip to collect temperature data of the chip.

6. The chip according to claim 5, wherein: The power consumption management processing unit is further configured to configure the distributed power consumption and temperature monitoring network, including: Specify the functional modules that need to be tested; Specify the counters to be enabled; and Specifies the temperature sensor to be detected.

7. The chip according to claim 1, wherein: The power consumption management processing unit is further configured to count the types and numbers of activities of the chip in a period of time before the current time and the real-time temperature, and calculate the current power consumption value of the chip based on the power consumption weights of different types of activities of the chip at the real-time temperature.

8. The chip according to claim 1, wherein: Each of the multiple throttling switches includes an enable register, a throttling number register and a throttling control valve, the enable register is enabled or disabled based on the power consumption data, the throttling number register sends a throttling control number signal to the throttling control valve based on whether the enable register is enabled, and the throttling control valve respectively adjusts the data transmission bandwidth between the multiple functional modules and the data bus based on the throttling control number signal.

9. The chip according to claim 8, wherein: The power consumption management processing unit is further configured to perform the following operations on the selected throttling switch: The throttling number register is configured, wherein the throttling number register includes a first register for the throttling number when the power consumption does not exceed the standard and a second register for the throttling number when the power consumption exceeds the standard, When the power consumption of the chip does not exceed the standard, the enable register is configured to be disabled, and the throttling control number N received by the throttling control valve is equal to the configuration value of the first register, and When the power consumption of the chip exceeds the standard, the enable register is configured to be enabled, and the throttling control number N received by the throttling control valve is equal to the configuration value of the second register, and The throttle control valve is configured to adjust a data transmission bandwidth through the selected throttle switch based on a throttle control number N, where N is an integer greater than or equal to zero.

10. The chip according to claim 9, wherein: When the functional module is a processing core, for the throttling switch used for the processing core, the throttling control number is the throttling number of memory access instructions, the number of memory access instructions received by the throttling control valve from the processing core is M, and the number of memory access instructions released by the throttling control valve to the data bus is MN, wherein M is an integer greater than or equal to 0, and when N is greater than or equal to M, the number of memory access instructions is 0.

11. The chip according to claim 9, wherein: When the functional module is a main memory controller, for the throttling switch used for the main memory controller, the throttling control number is the throttling number of memory access instructions, the number of memory access requests received by the throttling control valve from the data bus is M, and the number of memory access requests allowed by the throttling control valve from the data bus to the main memory controller is MN, wherein M is an integer greater than or equal to 0, and when N is greater than or equal to M, the number of memory access requests is 0.

12. The chip according to claim 9, wherein: When the functional module is a chip connector, for the throttle switch used for the chip connector, the throttling control number is the cross-chip data request throttling number, the number of data requests received by the throttling control valve from the chip connector is M, and the number of data requests released by the throttling control valve to the data bus is MN, wherein M is an integer greater than or equal to 0, and when N is greater than or equal to M, the number of data requests is 0.

13. The chip according to any one of claims 1 to 7, wherein: The power consumption management processing unit is further configured to configure different bandwidths based on priorities of data paths between different functional modules and the data bus.

14. An electronic device comprising the chip according to any one of claims 1 to 13.

15. A power consumption management method for a chip, comprising: The distributed power consumption and temperature monitoring network distributed in the chip collects the activity data and temperature data of the chip, and sends the activity data and the temperature data to the power consumption management processing unit through a control bus; The power consumption management processing unit calculates the power consumption data of the chip based on the activity data and the temperature data, and outputs a control signal for adjusting the data transmission bandwidth between the plurality of functional modules and the data bus based on the power consumption data; as well as A plurality of throttling switches directly adjust the data transmission bandwidth between the plurality of functional modules and the data bus respectively based on the control signal, Wherein, different throttle switches are configured to adjust different functional modules, and Wherein, the multiple throttling switches are respectively arranged between the multiple functional modules and the data bus.

16. The power consumption management method according to claim 15, further comprising: The distributed power consumption and temperature monitoring network counts the operations of the multiple functional modules respectively through multiple counters, and collects and counts the count values ​​of the operations of the multiple functional modules respectively through the control bus. Among them, the multiple functional modules include one or more of a processor core, a main memory controller, a peripheral controller, and a chip connector, the activity data includes multiple counts of various operation times of the multiple functional modules, and the distributed power consumption and temperature monitoring network includes multiple counters distributed in the multiple functional modules.

17. The power consumption management method according to claim 15, further comprising: The power management processing unit counts the types and numbers of activities of the chip in a period of time before the current time and the real-time temperature, and calculates the current power consumption value of the chip based on the power consumption weights of different types of activities of the chip at the real-time temperature.

18. The power consumption management method according to any one of claims 15 to 17, wherein: The plurality of throttling switches directly adjust the data transmission bandwidth between the plurality of functional modules and the data bus respectively based on the control signal, including: The power consumption management processing unit performs the following operations on a throttle switch selected from among the throttle switches respectively arranged in the plurality of functional modules and the data bus: The throttling number register of the selected throttling switch is configured, wherein the throttling number register includes a first register for the throttling number when the power consumption is not exceeded and a second register for the throttling number when the power consumption is exceeded, and the value of the first register is the same as or different from the value of the second register. When the power consumption of the chip does not exceed the standard, the enable register of the selected throttling switch is configured to be disabled, and the throttling control number N received by the throttling control valve of the selected throttling switch is equal to the configuration value of the first register, When the power consumption of the chip exceeds the standard, the enable register is configured to be enabled, and the throttling control number N received by the throttling control valve of the selected throttling switch is equal to the configuration value of the second register, The throttle control valve is enabled to adjust a data transmission bandwidth passing through the selected throttle switch based on the throttle control number N, where N is an integer greater than or equal to 0.

19. The power consumption management method according to any one of claims 15 to 17, further comprising: The power consumption management processing unit configures different bandwidths based on the priorities of data paths between different functional modules and the data bus.

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