A multi-chip cooperative scheduling method for ZNS SSDs

Abstract

The application relates to the technical field of computer storage, in particular to a multi-chip cooperative scheduling method for ZNS SSDs; the method aims to minimize the total response time of all requests, and designs a first multi-chip cooperative method and a second multi-chip cooperative method; when a ZNS SSD device receives a request, the request is converted by a partition conversion layer, and the converted request is split into multiple transactions by an SSD controller according to a partition mapping module, and each transaction corresponds to a chip; if the request is selected by a scheduling algorithm, a transaction scheduling module schedules the positions of all transactions in the request according to the scheduling algorithm and the first multi-chip cooperative method; if the request is not selected by the scheduling algorithm, the transaction scheduling module schedules the positions of all transactions in the request according to the second multi-chip cooperative method; the application further reduces the total response time of all requests on the basis of guaranteeing the scheduling effect of an existing scheduling algorithm.

Description

Technical Field

[0001] This invention relates to the field of computer storage technology, and in particular to a multi-chip collaborative scheduling method for ZNS SSDs. Background Technology

[0002] Solid-state drives (SSDs) based on flash memory are widely used in modern computer systems, such as storage centers, personal computers, and embedded devices, due to their high performance and low power consumption. With the advent of the big data and cloud computing era, user demands for SSD performance have further increased. However, the mismatch between traditional block interfaces and the characteristics of flash memory has gradually become one of the reasons hindering further improvements in SSD performance. Therefore, the ZNS (Zoned Namespace) interface has been proposed as a replacement for traditional block interfaces to compensate for their shortcomings and further improve SSD performance.

[0003] On one hand, the ZNS interface divides the logical address space into fixed-size zones, allowing the host to more rationally partition data based on its application information, thus reducing garbage collection overhead. On the other hand, the ZNS interface stipulates that each zone must be written sequentially and reset before being rewritten, making data writing more consistent with the characteristics of flash memory media to avoid unnecessary conversions. Furthermore, based on the above methods, ZNS SSD devices only need to maintain the mapping relationship between partitions and physical blocks, thereby reducing the space overhead of the mapping table. Although the NVMe ZNS specification does not specify a concrete partition mapping method, in order to utilize the chip parallelism of SSDs, each partition typically needs to be mapped to multiple chips, allowing requests for that partition to be responded to by these chips in parallel. However, scheduling within an SSD device often only considers the scheduling of transactions within a single chip (such as fair scheduling), ignoring other chips that coordinate in responding to the same request, leading to increased response times for other requests. Summary of the Invention

[0004] To address the aforementioned issues, the purpose of this invention is to propose a multi-chip collaborative scheduling method for ZNS SSD devices, which can be used in conjunction with existing scheduling algorithms to minimize the total response time of all requests while ensuring scheduling effectiveness.

[0005] The multi-chip collaborative scheduling method for ZNS SSDs proposed in this invention includes the following steps:

[0006] S1. Initialize the ZNS SSD device, which includes a partition translation layer, a partition mapping module, an SSD controller, a transaction scheduling module, and a flash memory module; the flash memory module includes multiple chips, each chip corresponding to a chip queue;

[0007] S2. To minimize the total response time of all requests, design a first multi-chip collaborative method and a second multi-chip collaborative method;

[0008] S3. When the ZNS SSD device receives a request, it transforms the request through the partition transformation layer. The SSD controller then splits the transformed request into multiple transactions according to the partition mapping module, with each transaction corresponding to one chip.

[0009] S4 If the request is selected by the scheduling algorithm, the transaction scheduling module performs position scheduling for all transactions in the request according to the scheduling algorithm and the first multi-chip collaborative method;

[0010] S5. If the request is not selected by the scheduling algorithm, the transaction scheduling module performs position scheduling for all transactions in the request according to the second multi-chip collaborative method;

[0011] S6. The chips in the flash memory module continuously retrieve transactions from the head of their own chip queue to respond. When all the transactions split from a request have been responded to, the request response is complete.

[0012] Furthermore, in step S4, when the first multi-chip collaborative method is used to perform location scheduling on the request selected by the scheduling algorithm, the specific process includes:

[0013] S11. When storing all transactions of the requests selected by the scheduling algorithm into their respective chip queues, calculate the nearest head position of each transaction in its chip queue according to the scheduling algorithm.

[0014] S12. Select the maximum value among all recent header positions as the maximum scheduling position for all transactions in this request;

[0015] S13. The tail of each chip queue is the initial position. All transactions start from the initial position in their respective chip queues and move towards the head of the chip queue.

[0016] S14. Calculate the total response time gain for each move, until the maximum scheduling position is reached;

[0017] S15. Filter out the maximum value of the total response time benefit, and take the position corresponding to the maximum value as the final scheduling position, and insert all transactions in the request into the final scheduling position.

[0018] Furthermore, assuming that the response time for each chip to respond to each transaction is t, the transaction that responds last in a request is called the last transaction, and the transaction that moves to the tail of the chip queue due to the insertion of a scheduled transaction is called the queue-jumping transaction; the calculation process of the total response time benefit for each move in step S14 includes:

[0019] Before moving one position from position A to position B, obtain the total number of transactions currently at position A among the requests selected by the scheduling algorithm. ;

[0020] Moving these M transactions to position B reduces the response time of the request selected by the scheduling algorithm by t; however, it also results in multiple pre-queueed transactions. The number of transactions belonging to the last transaction is then determined by deduplicating these pre-queueed transactions. The response time gain for this move from location A to location B is... ;

[0021] Assuming the initial position is 1 and the final scheduled position is k, the total response time gain at position B is: .

[0022] Furthermore, requests not selected by the scheduling algorithm are scheduled using a second multi-chip collaborative method, specifically including:

[0023] S21. When storing all transactions in a request that was not selected by the scheduling algorithm into their respective chip queues, traverse the depth of the chip queues corresponding to all transactions in that request.

[0024] S22. Select the position corresponding to the minimum depth as the target position for all transactions in this request;

[0025] S23. Insert the transactions belonging to the chip queue corresponding to the minimum depth directly to the tail of the chip queue;

[0026] S24. Calculate the position of the remaining transactions in the chip queue that yields the greatest benefit, and perform position scheduling.

[0027] Furthermore, in step S24, the process of calculating the position of maximum profit for the remaining transactions includes:

[0028] S241. Determine the tail of the chip queue for each remaining transaction, and move from the tail towards the target location;

[0029] S242. Calculate the total response time gain for each move; end the move when the total response time gain is less than or equal to 0.

[0030] S243. Filter out the maximum value of the total response time benefit and insert all remaining transactions into the positions corresponding to the maximum value of the total response time benefit.

[0031] Furthermore, assuming that the response time of each chip to each transaction is t, the last transaction to respond to a request is called the last transaction, and the transaction that moves to the tail of the chip queue due to the insertion of a scheduled transaction is called the queue-jumping transaction; in step S242, the calculation process of the total response time benefit for each move includes:

[0032] Before moving one position from position A to position B, obtain the total number of remaining transactions currently at position A. ;

[0033] Moving these N remaining transactions to position B reduces the response time of the requests belonging to the remaining transactions by t; however, this also results in multiple pre-queueed transactions. The number of transactions belonging to the last transaction is then determined by deduplicating these pre-queueed transactions. The response time gain for this move from location A to location B is... ;

[0034] Assuming the initial position is 1 and the final scheduled position is k, the total response time gain at position B is: .

[0035] The beneficial effects of this invention are:

[0036] This invention proposes a multi-chip collaborative scheduling method for ZNS SSDs, which can be used in conjunction with existing scheduling algorithms. For transactions that existing scheduling algorithms need to schedule, it avoids increasing the total request response time caused by scheduling only transactions in a single chip queue by comprehensively scheduling other transactions belonging to the same request. For transactions that do not need to be scheduled, it inserts them into the most suitable position in the chip queue by comprehensively considering the transaction situation of all transactions corresponding to the same request, thereby minimizing the total request response time. The method of this invention further reduces the total response time of all requests while maintaining the scheduling effect of existing scheduling algorithms. Attached Figure Description

[0037] Figure 1 This is a flowchart of the method of the present invention;

[0038] Figure 2 This is a schematic diagram of the internal structure of the ZNS SSD device according to an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram illustrating the requests that need to be scheduled in the multi-chip collaborative scheduling of an embodiment of the present invention;

[0040] Figure 4This is a schematic diagram illustrating a multi-chip collaborative scheduling request that does not need to be scheduled, according to an embodiment of the present invention.

[0041] Figure 5 This is a multi-chip collaborative scheduling diagram according to an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] This invention provides a multi-chip collaborative scheduling method for ZNS SSDs, such as... Figure 1 As shown, it includes:

[0044] S1. Initialize the ZNS SSD device, which includes a partition translation layer, a partition mapping module, an SSD controller, a transaction scheduling module, and a flash memory module; the flash memory module includes multiple chips, each chip corresponding to a chip queue;

[0045] S2. To minimize the total response time of all requests, design a first multi-chip collaborative method and a second multi-chip collaborative method;

[0046] S3. When the ZNS SSD device receives a request, it transforms the request through the partition transformation layer. The SSD controller then splits the transformed request into multiple transactions according to the partition mapping module, with each transaction corresponding to one chip.

[0047] S4 If the request is selected by the scheduling algorithm, the transaction scheduling module performs position scheduling for all transactions in the request according to the scheduling algorithm and the first multi-chip collaborative method;

[0048] S5. If the request is not selected by the scheduling algorithm, the transaction scheduling module performs position scheduling for all transactions in the request according to the second multi-chip collaborative method;

[0049] S6. The chips in the flash memory module continuously retrieve transactions from the head of their own chip queue to respond. When all the transactions split from a request have been responded to, the request response is complete.

[0050] Generally, transaction scheduling modules operate on transactions. However, in order to coordinate the scheduling of all transactions for the same request across multiple chips, the present invention ensures that as long as one transaction in the request is selected, it is equivalent to selecting all transactions in the request, i.e., the request itself.

[0051] In one embodiment, the internal structure of the ZNS SSD device to which this invention is directed is as follows: Figure 2 As shown, the ZNS SSD device includes an SSD controller, a partition translation layer, a partition mapping module, a transaction scheduling module, and a flash memory module (flash memory medium). The flash memory module includes multiple chips, each corresponding to a chip queue. The partition mapping module includes all partitions split from the ZNS interface and the mapping relationship between these partitions and the physical media. When the ZNS SSD device receives a host request from the SQ, it first converts the host request into a specific operation (read, write, or erase operation) for a specific partition through the partition translation layer. The SSD controller, based on the mapping relationship of the partition in the partition mapping module, splits the converted request into multiple transactions. Each transaction is stored in a chip queue corresponding to a chip and processed by that corresponding chip. Figure 5 As shown; these multiple transactions can be processed in parallel by different chips; the chips in the flash memory module will continuously take transactions from the head of their own chip queue to respond. Only when all transactions of a request have been responded to is the request considered completed. Finally, the completed request is submitted to CQ.

[0052] Specifically, it takes a certain amount of time for a chip to respond to a transaction. Transactions that cannot be responded to in time are temporarily stored in the chip queue of the corresponding chip and then wait to be responded to. For transactions waiting for a response in the chip queue, the transaction scheduling module can schedule certain transactions forward or backward according to pre-agreed rules, thereby achieving corresponding purposes, such as increasing fairness and prioritizing read requests.

[0053] The transaction status in each chip queue is not entirely the same. Considering only the scheduling algorithm for a single chip's transaction means failing to perceive the scheduling status of other transactions belonging to the same request, which may increase the overall response time of that request and other requests. For example... Figure 3 As shown in (a), transaction TR4 in chip queue 1 and transaction TR4 in chip queue 2 both belong to request 4. However, during scheduling, only the scheduling situation in chip queue 2 was considered, while the transaction situation in chip queue 1 was ignored. After scheduling, the total response time of all requests increased by 600us. A request is considered complete when the last transaction in all its sub-transactions is completed; therefore, the response time of a request is calculated until the last transaction is completed. Figure 3In (a), even if TR4 in chip queue 2 is moved to a higher position, TR4 in chip queue 1 remains unchanged. Its position is further back than TR4 in chip queue 2, closer to the tail of the chip queue. Therefore, the response time of request 4 after scheduling is the same as before scheduling. At the same time, in chip queue 2, because TR4 is moved to the front, TR1, TR2, and TR3 are moved one position to the back. Therefore, the response time of requests 1, 2, and 3 all increases by 200µs, resulting in an increase of 600µs in the total response time of all requests.

[0054] In one embodiment, a first multi-chip collaborative method is proposed, which comprehensively considers all transactions in multiple chip queues within a single request during scheduling, specifically including:

[0055] S11. The request selected by the scheduling algorithm is split into multiple transactions, each transaction corresponding to a chip; scheduling is performed when all transactions are ready to be stored in their respective chip queues.

[0056] S12. A request is considered complete only after all transactions of a request have been responded to. Therefore, the response time of a request depends on the response time of the transaction (the last transaction) that is in the deepest queue (closest to the tail of the chip queue) among all its transactions. Therefore, in this embodiment, during scheduling, the chip queues corresponding to all transactions of the request selected by the scheduling algorithm are first traversed, and the nearest head position of each transaction in its chip queue is calculated according to the scheduling algorithm. The nearest head position refers to the position closest to the head of the queue that the transaction can be inserted into in its corresponding chip queue.

[0057] S13. Select the maximum value among all the nearest head positions as the maximum scheduling position (pos-max) for all transactions in this request; thereby avoiding unnecessary increase in response time for other requests, because even if transactions in other chip queues are scheduled to a position closer to the head of the queue than pos-max, the response time of this request will not decrease, but may even increase the response time of other requests.

[0058] Specifically, all chip queues have the same depth, meaning they can store the same number of transactions (i.e., the number of positions is the same). Positions closer to the head of the chip queue have smaller depths, while positions closer to the tail have larger depths. Selecting the maximum depth involves choosing the position closest to the tail of the chip queue from all the nearest head positions—that is, selecting the position with the largest depth.

[0059] S14. Starting from the tail of the chip queue as the initial position, all transactions move from their respective initial positions in the chip queue toward the head of the chip queue.

[0060] Specifically, the tail of a chip queue refers to the position after the last transaction in the chip queue before the latest transaction is stored in the chip queue, such as... Figure 5 As shown, request 4 is split into four transactions, corresponding to chip 1, chip 2, chip 3, and chip 4 respectively. When preparing to store all transactions of request 4 into their respective chip queues, the tail of chip queue 1 refers to the position after transaction TR3, and the first TR4 starts from this position; the tail of chip queue 2 refers to the position after transaction TR1, and the tail of chip queue 3 refers to the position after transaction TR2. This shows that the initial positions of all transactions of the same request in their respective chip queues are not necessarily the same.

[0061] S14. Calculate the total response time gain for each move, until the maximum scheduling position is reached;

[0062] Specifically, starting from the initial position closest to the tail of the queue among all transactions of the request, the process moves one position at a time. Not all transactions of a request move forward simultaneously. Instead, when it is necessary to move from position A to position B, if one or more transactions of the request are found to be at position A, those transactions at position A move together to position B. Eventually, almost all transactions of the request will reach the same position in the queue. The purpose of this movement is to ensure that all transactions of the same request are in the same position in their respective queues. The movement ends when all transactions of the request have reached the maximum scheduling position.

[0063] S15. Filter out the maximum value of the total response time benefit, and take the position corresponding to the maximum value as the final scheduling position, and insert all transactions in the request into the final scheduling position.

[0064] Specifically, such as Figure 3 As shown in (b), the arrow points to pos-max, which is the maximum scheduling position for all transactions in request 4. Starting from the tail of the chip queue, transactions TR4 in chip queue 1 and chip queue 2 move from their respective initial positions towards the head of the chip queue. For each position moved, the total response time gain is calculated until the maximum scheduling position is reached. The maximum total response time gain is selected, and the position corresponding to the maximum total response time gain (in...) is... Figure 3 (b) uses pos-max as the final scheduling position, and inserts all transactions in request 4 into the final scheduling position.

[0065] For requests that do not require scheduling, all transactions are typically inserted directly into the tail of the chip queue according to the First-In-First-Out (FIFO) principle. However, for chip queues with varying levels of busyness, this transaction placement method does not achieve the optimal overall request response time. For example... Figure 4 As shown in (a), the two transactions TR6 of request 6 are placed directly at the end of the queue by default. However, TR6 in chip queue 2 can be moved forward to reduce the response time of request 6 without affecting the response time of other requests.

[0066] In one embodiment, a second multi-chip collaboration method is provided. For requests that do not require scheduling, this method still inserts all transactions into the most suitable position in the corresponding chip queue from the perspective of multi-chip collaboration to minimize the total response time of all requests. The specific scheduling method is as follows:

[0067] S21. Requests not selected by the scheduling algorithm are split into multiple transactions, each transaction corresponding to a chip; when storing all transactions into their respective chip queues, the depth of the chip queues corresponding to all transactions in the request is traversed, that is, the depth value of the tail position of the chip queue.

[0068] S22. Select the position corresponding to the minimum depth as the target position for all transactions in this request;

[0069] S23. Insert the transactions belonging to the chip queue corresponding to the minimum depth directly to the tail of the chip queue;

[0070] S24. Calculate the maximum profit position of all other transactions in the request in their respective chip queues and perform position scheduling.

[0071] Specifically, in step S24, the process of calculating the position of maximum profit for all remaining transactions includes:

[0072] S241. Determine the tail of the chip queue where each of the remaining transactions is located, and move all the remaining transactions from the tail towards the target position;

[0073] S242. Calculate the total response time gain for each move; when the total response time gain is less than or equal to 0, all other transactions end the move.

[0074] S243. Filter out the maximum value of the total response time benefit and insert all remaining transactions into the positions corresponding to the maximum value of the total response time benefit.

[0075] Specifically, such as Figure 4As shown, the depths of the chip queues corresponding to the two transactions in request 6 are traversed, i.e., the depth values ​​of the tail positions of the chip queues corresponding to the two transactions are obtained. Among them, the depth value of the tail position of chip queue 3 is the smallest, so the tail position of chip queue 3 is selected as the target position of the two transactions in request 6. The transactions corresponding to chip queue 3 are directly inserted into the tail of chip queue 3. The transactions in chip queue 2 start from the tail of chip queue 2 and move towards the target position. For each position moved by the transactions in chip queue 2, the total response time gain of this move is calculated. When the total response time gain is less than or equal to 0, the remaining transactions end their movement. The maximum value of the total response time gain is selected, and the transactions in chip queue 2 are inserted into the position corresponding to the maximum value of the total response time gain. Figure 4 As can be seen in (b), the location corresponding to the maximum total response time benefit is the target location.

[0076] The response completion condition for a request is that all transactions split from that request are completed. Therefore, the response time of a request is equal to the response time of its last responded transaction (the last transaction). If another request's transaction is inserted before the last transaction of a request, the response time of the last transaction will increase (because the waiting time increases), thus increasing the response time of the request to which the last transaction belongs. In one embodiment, the transaction to be scheduled (the transaction scheduled using the first or second multi-chip collaborative method) is called the target transaction, and the transaction forced to move to the tail of the queue due to the insertion of the target transaction is called the queue-jumped transaction. Obviously, when the queue-jumped transaction is the last transaction of its own request, this scheduling will increase the response time of the request to which the queue-jumped transaction belongs. Therefore, the specific way to calculate the total response time benefit of each move is as follows:

[0077] S101. Assume that t is the response time of one chip to one transaction, and that the response time of each chip to each transaction is the same;

[0078] S102. Whenever the target transaction moves one transaction position toward the head of the chip queue, the response time of the scheduled request is reduced by t;

[0079] Specifically, when moving to a new position, there may be only one target transaction or multiple target transactions moving, because each target transaction only moves if the position it is about to move to is the next position of its current position. Regardless of how many target transactions move each time, the response time of the request to which the target transaction belongs only decreases by t, and these target transactions participating in the moving process belong to the same request.

[0080] S103. For a transaction that is interrupted, if it is not the last transaction of its parent request, it will not affect the response time of its parent request; if it is the last transaction of its parent request, the response time of its parent request will increase by t; furthermore, when n non-repeating interrupted transactions are the last transactions of their parent requests, the total response time of all requests will increase by n×t.

[0081] S4. Therefore, the response time gain of the target transaction moving once is (1-n)×t; and for a certain position, its total response time gain is the sum of the response time gains of all the positions that have been moved before.

[0082] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," "fixing," "rotation," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Unless otherwise explicitly limited, those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0083] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A multi-chip collaborative scheduling method for ZNS SSDs, characterized in that, include: S1. Initialize the ZNS SSD device, which includes a partition translation layer, a partition mapping module, an SSD controller, a transaction scheduling module, and a flash memory module; the flash memory module includes multiple chips, each chip corresponding to a chip queue; S2. To minimize the total response time of all requests, design a first multi-chip collaborative method and a second multi-chip collaborative method; S3. When the ZNS SSD device receives a request, it transforms the request through the partition transformation layer. The SSD controller then splits the transformed request into multiple transactions according to the partition mapping module, with each transaction corresponding to one chip. S4 If the request is selected by the scheduling algorithm, the transaction scheduling module performs position scheduling for all transactions in the request according to the scheduling algorithm and the first multi-chip collaborative method; When using the first multi-chip collaborative method to perform location scheduling for requests selected by the scheduling algorithm, the specific process includes: S11. When storing all transactions of the requests selected by the scheduling algorithm into their respective chip queues, calculate the nearest head position of each transaction in its chip queue according to the scheduling algorithm. S12. Select the maximum value among all recent header positions as the maximum scheduling position for all transactions in this request; S13. The tail of each chip queue is the initial position. All transactions start from the initial position in their respective chip queues and move towards the head of the chip queue. S14. Calculate the total response time gain for each move, until the maximum scheduling position is reached; S15. Filter out the maximum value of the total response time benefit, and take the position corresponding to the maximum value as the final scheduling position, and insert all transactions in the request into the final scheduling position; Assuming the response time for each chip to each transaction is t, the transaction that responds last in a request is called the last transaction, and the transaction that moves to the tail of the chip queue due to the insertion of a scheduled transaction is called the queue-jumping transaction; the calculation process of the total response time benefit for each move in step S14 includes: Before moving one position from position A to position B, obtain the total number of transactions currently at position A among the requests selected by the scheduling algorithm. ; Moving these M transactions to position B reduces the response time of the request selected by the scheduling algorithm by t; however, it also results in multiple pre-queueed transactions. The number of transactions belonging to the last transaction is then determined by deduplicating these pre-queueed transactions. The response time gain for this move from location A to location B is... ; Assuming the initial position is 1 and the final scheduled position is k, the total response time gain at position B is: ; S5. If the request is not selected by the scheduling algorithm, the transaction scheduling module performs position scheduling for all transactions in the request according to the second multi-chip collaborative method; Requests not selected by the scheduling algorithm are scheduled using a second multi-chip collaborative method, which includes: S21. When storing all transactions in a request that was not selected by the scheduling algorithm into their respective chip queues, traverse the depth of the chip queues corresponding to all transactions in that request. S22. Select the position corresponding to the minimum depth as the target position for all transactions in this request; S23. Insert the transactions belonging to the chip queue corresponding to the minimum depth directly to the tail of the chip queue; S24. Calculate the position with the greatest profit for the remaining transactions in the chip queue and perform position scheduling; S6. The chips in the flash memory module continuously retrieve transactions from the head of their own chip queue to respond. When all the transactions split from a request have been responded to, the request response is complete.

2. The multi-chip collaborative scheduling method for ZNS SSDs according to claim 1, characterized in that, In step S24, the process of calculating the position of maximum profit for the remaining transactions includes: S241. Determine the tail of the chip queue for each remaining transaction, and move from the tail towards the target location; S242. Calculate the total response time gain for each move; end the move when the total response time gain is less than or equal to 0. S243. Filter out the maximum value of the total response time benefit and insert all remaining transactions into the positions corresponding to the maximum value of the total response time benefit.

3. The multi-chip collaborative scheduling method for ZNS SSDs according to claim 2, characterized in that, Assuming that the response time of each chip to each transaction is t, the last transaction to respond to a request is called the last transaction, and the transaction that moves to the tail of the chip queue due to the insertion of a scheduled transaction is called the queue-jumped transaction. In step S242, the calculation process for the total response time gain for each move includes: Before moving one position from position A to position B, obtain the total number of remaining transactions currently at position A. ; Moving these N remaining transactions to position B reduces the response time of the requests belonging to the remaining transactions by t; however, this also results in multiple pre-queueed transactions. The number of transactions belonging to the last transaction is then determined by deduplicating these pre-queueed transactions. The response time gain for this move from location A to location B is... ; Assuming the initial position is 1 and the final scheduled position is k, the total response time gain at position B is: .

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