A system and method for detecting abnormal signals on an I2C bus

Abstract

The present invention discloses a system and method for detecting abnormal signals on an I2C bus, belonging to the technical field of I2C buses. A system for detecting abnormal signals on an I2C bus according to the present invention includes an I2C bus and an I2C bus detection module, wherein the I2C bus is connected to one or more master devices and one or more slave devices for data communication; the detection module is applicable to both master devices and slave devices, and when receiving or sending data, the detection module will detect the clock bus and data bus on the I2C bus, detect abnormal signals caused by external interference on the bus, and then cause errors in the received and transmitted data and clock frequencies. When error data and error clock frequencies are found, an interrupt signal is generated to prompt the corresponding error type, improving the communication security of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of I2C bus technology, and specifically provides a system and method for detecting abnormal signals on an I2C bus. Background Art

[0002] I2C (Inter-Integrated Circuit) is a two-wire serial bus developed by PHILIPS in the 1980s for connecting microcontrollers and their peripheral devices.

[0003] The I2C bus is a serial bus that can be used to send and receive data and can perform bidirectional data transfer between devices. Each device connected to the same I2C bus has a unique address. The I2C bus has two signal lines: the SDA line (data line) and the SCL line (clock line), where the master device generates the clock signal. A complete data transfer on the I2C bus includes a start phase, an addressing and acknowledgment phase, a data transfer and acknowledgment phase, and a final stop phase.

[0004] Since the I2C specification requires the receiving device to feedback ACK / NACK after receiving the address or data, the control of the I2C bus during the address or data sending phase is controlled by the sending device and the bus control right will be lost after the address or data is sent. At this time, the data receiving device acquires the bus control right and feedbacks ACK / NACK. Since there is a delay between the two transceiver devices from one device losing control of the bus to another device acquiring the bus control right, that is, there is a period of time when the bus is in an uncontrolled state. In this state, the bus signal is extremely vulnerable to external interference, resulting in incorrect high and low level signals. Due to the existence of the above phenomenon, when the bus is interfered, it is extremely easy to cause abnormal high and low levels of the bus, which in turn affects the security of data transmission on the bus.

[0005] Regarding the handling of I2C bus communication anomalies, in the market, by detecting the I2C clock line signal and the I2C clock line feedback signal, it can only determine which slave device among the one master and multiple slaves connected to the I2C bus has a fault, or by detecting whether there is an acknowledgment signal within a certain period of time after the data transmission on the I2C bus is completed to determine whether the communication is normal, and it cannot detect data and clock errors and abnormal signals of error types and problems under normal communication. Summary of the Invention

[0006] The purpose of the present invention is to provide a system and method for detecting abnormal signals on an I2C bus to solve the problems raised in the above background art.

[0007] To solve the above technical problems, the present invention provides the following technical solution: A system for detecting abnormal signals on an I2C bus, the detection system comprising an I2C bus, a bus information acquisition and parsing module, and an I2C bus detection module; the I2C bus detection module includes a transmitted data comparison module, a received data comparison module, and an interrupt module;

[0008] The bus information acquisition and parsing module is connected to the I2C bus, obtains real-time information of the data line and the clock line, and transmits the collected bus signals to the received data comparison module after parsing;

[0009] The transmitted data comparison module is used for data comparison. When the comparison results are inconsistent, an interrupt signal indicating an error in the transmitted data is sent; the transmitted data comparison module includes a first counter Cnt1, a second counter Cnt2, a first data comparator, and a first clock comparator;

[0010] Further, during the above transmitted data comparison process, attention needs to be paid to the time interval T1 from when the data in the transmitted data memory is stored in the memory to when it is sent to the bus. When comparing, the first counter Cnt1 is used for counting. When the counted value meets the time interval T1, the data is compared with the bus data; the data memory is connected to the I2C bus and is used for receiving the transmitted data;

[0011] In the transmitted data comparison module, the first counter Cnt1 can achieve comparison of any one byte or all the bytes of data to be transmitted by presetting a time value;

[0012] Further, during the above transmitted data process, when acting as a master device, the bus information acquisition and parsing module also transmits the parsed bus clock signal to the clock signal comparator. The second counter Cnt2 counts the high and low periods of the clock signal, and then the clock comparator compares the bus clock with the preset clock. If the comparison results are inconsistent, the interrupt module issues a clock error interrupt signal;

[0013] The received data comparison module parses the clock and data signals on the I2C bus, counts the length of each received data signal, and determines whether it is abnormal; the received data comparison module includes a third counter Cnt3, a fourth counter Cnt4, a second data comparator, and a second clock comparator;

[0014] The I2C bus is electrically connected to the bus information acquisition and parsing module; the output end of the bus information acquisition and parsing module is respectively connected to the input ends of the transmitted data comparison module and the received data comparison module; the output ends of the transmitted data comparison module and the received data comparison module are connected to the input end of the interrupt module.

[0015] When receiving data, the bus information acquisition and parsing module first parses the clock and data signals on the bus. The third counter Cnt3 counts the length of each BIT data signal received, and judges whether there is a BIT bit that should be high level but is abnormally changed to low level due to bus interference. If an abnormality occurs, the interrupt module will send a data interrupt error signal;

[0016] Further, during the above data receiving process, when used as the master device, the fourth counter Cnt4 counts the high and low level periods of the clock signal during data reception, and compares the clock signal in the clock comparator 2 according to the preset transmission frequency. If the received clock signal is different from the set clock frequency, that is, the comparison fails, the interrupt module will send a clock error interrupt signal;

[0017] Further, during the above data receiving process, when used as the master device, if the receive data memory is full and the CPU has not read the stored data, resulting in the master device actively pulling down the clock line to wait for the data to be read out, this will trigger other interrupts, rather than triggering the above clock error interrupt.

[0018] A method for detecting abnormal signals on the I2C bus, characterized in that: the detection method includes the following steps:

[0019] S1. The bus information acquisition and parsing module acquires real-time bus information, and after parsing the bus information, transmits it to the counter, data comparator, and clock comparator respectively;

[0020] S2. During the data sending process, the data sending comparison module compares the data to be sent in the I2C data register with the data being transmitted on the data bus. When the comparison result is inconsistent, the bus abnormal signal interrupt module will immediately send an interrupt signal of data sending error;

[0021] S3. During the data receiving process, the counter counts the length of each BIT data signal received, and judges whether there is a BIT bit that should be high level but is abnormally changed to low level due to bus interference. When an abnormality occurs, the interrupt module will send a data interrupt error signal.

[0022] Further, in step S2, when used as the master device or the slave device, the second counter Cnt2 is used to calculate the clock frequency on the bus, and cooperate with the first clock comparator to compare whether the preset clock frequency is consistent with the current bus clock frequency.

[0023] Further, in step S3, when used as the master device or the slave device, the fourth counter Cnt4 in the data receiving comparison module is used to count the bus clock frequency, and cooperate with the second clock comparator to compare with the preset clock frequency.

[0024] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: The present invention can detect the signals on the I2C bus in real time, including abnormal clock signals and abnormal data signals, and send corresponding interrupt signals in a timely manner after the above abnormal signals appear, indicating the corresponding error types, improving the communication security of the device, realizing the detection of abnormal signals on the I2C bus, and greatly improving the security of data transmission on the I2C bus. It can be seen that, compared with the prior art, the present invention has prominent substantive features and significant progress. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention, but do not constitute a limitation to the present invention. In the drawings:

[0026] Figure 1 A schematic diagram of the module structure for detecting abnormal signals on the I2C bus;

[0027] Figure 2 A flowchart for detecting the data bus when sending data;

[0028] Figure 3 A flowchart for detecting the data bus when receiving data;

[0029] Figure 4 A flowchart for detecting the clock bus when acting as a master device;

[0030] Figure 5 A flowchart for detecting the clock bus when acting as a slave device;

[0031] In the figure, 1. Counter Cnt1; 2. Data comparator [1]; 3. Counter Cnt2; 4. Clock comparator [1]; 5. Interrupt module; 6. Clock comparator [2]; 7. Counter Cnt4; 8. Data comparator [2]; 9. Counter Cnt3; 10. Bus information acquisition and parsing module; 11. I2C bus. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] Please refer to Figures 1 - 5, the present invention provides a technical solution: a system for detecting abnormal signals on an I2C bus. The detection system includes an I2C bus, a bus information acquisition and parsing module, and an I2C bus detection module; the I2C bus detection module includes a transmitted data comparison module, a received data comparison module, and an interrupt module;

[0034] The bus information acquisition and parsing module is connected to the I2C bus, obtains real-time information of the data line and the clock line, and transmits the collected bus signals to the received data comparison module after parsing;

[0035] The transmitted data comparison module is used for data comparison. When the comparison results are inconsistent, an interrupt signal indicating an error in the transmitted data is sent out; the transmitted data comparison module includes a first counter Cnt1, a second counter Cnt2, a first data comparator, and a first clock comparator; the first counter Cnt1 uses counter Cnt1; the second counter Cnt2 uses counter Cnt2; the first data comparator uses data comparator [1]; the first clock comparator uses clock comparator [1];

[0036] Further, during the above-mentioned transmitted data comparison process, attention needs to be paid to the time interval T1 from when the data in the transmitted data memory is stored in the memory to when it is sent to the bus. When comparing, the first counter Cnt1 is used for counting. When the counted value meets the time interval T1, the data is compared with the bus data; the data memory is connected to the I2C bus and is used for receiving the transmitted data;

[0037] In the transmitted data comparison module, the first counter Cnt1 can achieve the comparison of any one byte or all the bytes to be transmitted by presetting a time value;

[0038] Further, during the above-mentioned transmitted data process, when used as the master device, the bus information acquisition and parsing module will also transmit the parsed bus clock signal to the clock signal comparator. The second counter Cnt2 will count the high and low cycles of the clock signal, and then the clock comparator will compare the bus clock with the preset clock. If the comparison results are inconsistent, the interrupt module will send out a clock error interrupt signal;

[0039] The received data comparison module parses the clock and data signals on the I2C bus, counts the length of each received data signal, and determines whether it is abnormal; the received data comparison module includes a third counter Cnt3, a fourth counter Cnt4, a second data comparator, and a second clock comparator; the third counter Cnt3 uses counter Cnt3; the fourth counter Cnt4 uses counter Cnt4; the second data comparator uses data comparator [2]; the second clock comparator uses clock comparator [2];

[0040] The I2C bus is electrically connected to the bus information acquisition and parsing module; the output end of the bus information acquisition and parsing module is respectively connected to the input ends of the transmitted data comparison module and the received data comparison module; the output ends of the transmitted data comparison module and the received data comparison module are connected to the input end of the interrupt module.

[0041] When receiving data, the bus information acquisition and parsing module first parses the clock and data signals on the bus. The third counter Cnt3 counts the length of each BIT data signal received, and judges whether there is a BIT bit that should be high level but has been abnormally changed to low level due to bus interference. If an abnormality occurs, the interrupt module will send a data interrupt error signal.

[0042] Further, during the above process of receiving data, when used as the master device, the fourth counter Cnt4 counts the high and low level cycles of the clock signal during data reception. In the clock comparator, the clock signal is compared according to the preset transmission frequency. If the received clock signal is different from the set clock frequency, that is, the comparison fails, the interrupt module will send a clock error interrupt signal.

[0043] Further, during the above process of receiving data, when used as the master device, if the received data memory is full and the CPU has not read the stored data, resulting in the master device actively pulling down the clock line to wait for the data to be read out, other interrupts will be triggered, rather than the above-mentioned clock error interrupt.

[0044] Further, when used as the master device or the slave device, the second counter Cnt2 is used to calculate the clock frequency on the bus, and cooperate with the first clock comparator to compare whether the preset clock frequency is consistent with the current bus clock frequency.

[0045] Further, when used as the master device or the slave device, the fourth counter Cnt4 in the received data comparison module is used to count the bus clock frequency, and cooperate with the second clock comparator to compare with the preset clock frequency.

[0046] In the embodiment of the present invention, as Figure 1 shown, a system and method for detecting abnormal signals on the I2C bus provided in this embodiment case includes counters: 1, 3, 7, 9, data comparators: 2, 8, clock comparators: 4, 6, and an interrupt module 5; the data comparator 2 is connected to the transmitted data memory; the bus information acquisition and parsing module 10 is connected to the I2C bus 11, and is used to collect bus information and transmit it to the counter, data comparator and clock comparator respectively after parsing.

[0047] The detection steps of a method for detecting abnormal signals on the I2C bus include:

[0048] Step S1: The bus information acquisition and parsing module 10 acquires real-time bus information, and after parsing the bus information, it is respectively transmitted to the counter, the data comparator, and the clock comparator;

[0049] Step S2: During the data sending process, the data sending comparison module 2 compares the data to be sent in the I2C data register with the data being transmitted on the data bus. If the comparison results are inconsistent, then the bus exception signal interruption module 5 will immediately issue an interruption signal indicating a data sending error;

[0050] As shown in the process Figure 2 shown, the comparison process in step S2 is as follows: The CPU controls the low-speed peripheral bus APB to write the data to be sent into the I2C data register or uses DMA to transfer the data to be sent from other memory blocks to the sending data register of the I2C. When data sending is enabled, the data comparator [1] reads the data to be sent in the sending data register. The I2C device sends data, and the I2C transmits the data to be sent in its data register to the bus, and is received by the I2C device with the corresponding address. While the above data is being transmitted to the data bus, the bus information acquisition and parsing module reads back the real-time signal on the data bus and sends it to the data comparator [1]. At this time, the data comparator has the real-time data bus signal on the bus and the real data to be sent. The two are compared bit by bit. If there are different situations, the interruption module releases an error interruption signal. If they are the same, the comparison continues bit by bit until the data transmission is completed.

[0051] Step S3: During the data receiving process, the counter 9 counts the length of each BIT data signal received, and judges whether there is a BIT bit that should have been high level but has been abnormally changed to low level due to bus interference. If an abnormality occurs, the interruption module 5 will issue a data interruption error signal;

[0052] As shown in the process Figure 3As shown, the detailed comparison process described in step S3 is as follows: The data sending device transmits the data to be sent to the data bus. After the information acquisition and parsing module acquires the data information on the bus, it sends it to the data comparator [2]. The data comparator [2] performs a high and low cycle count on the received data bus information. For example, it records the high or low level time length of the data information within the current bit time and saves it, and then records the high or low level time length of the data information within the next bit time. Then, it compares the two recorded time lengths. If they are not equal, the interrupt module releases an interrupt signal; if they are equal, it discards the time length recorded for the first time, saves the time length recorded for the second time, then continues to record the high or low level time length of the data within the next bit time and makes a comparison, and so on for recording and comparison until the data transmission is completed.

[0053] Specifically, in step S2, when sending data as the master device, the counter 3 performs a high and low cycle count on the clock signal, and then the clock comparator 4 compares the bus clock with the preset clock. If the comparison result is inconsistent, the interrupt module 5 issues a clock error interrupt signal;

[0054] As Figure 4 shown, in the above step S2, when sending data as the master device, the detailed comparison process of the clock bus is as follows: Before the I2C master device starts sending data, it needs to configure the clock register to achieve different data transmission rates. After configuring the I2C clock register, the clock comparator [1] of the master device reads the clock parameters in the I2C clock register. When the data transmission starts, the bus information acquisition and parsing module acquires the information of the clock bus and sends it to the clock comparator [1] after parsing. At this time, the clock comparator [1] has the preset clock information and the real-time clock information. It compares the high and low level cycles on the clock bus with the high and low level cycle lengths preset in the I2C clock register. If they are inconsistent, the interrupt module releases an interrupt signal.

[0055] Specifically, in step S2, when receiving and sending data as the slave device, the counter 3 records the high and low cycle lengths of the clock signal, and then the clock comparator 4 compares the high and low level lengths of the previous clock cycle with those of the current clock cycle. If the comparison result is inconsistent, the interrupt module 5 issues a clock error interrupt signal;

[0056] As Figure 5As shown, when receiving and transmitting data as a slave device in step S2, the detailed comparison process of the clock comparator is as follows: After the master device starts initiating data communication, the bus information acquisition and parsing module of the slave device will acquire the clock bus information and send it to the clock comparator [2]. After the data transmission starts, starting from a rising edge of the clock bus, the clock comparator records the lengths of the high and low levels within the clock cycle of the current clock bus (the lengths are obtained by counting with a counter) and saves them. Then, it records the lengths of the high and low levels within the next clock cycle of the clock bus (the lengths are obtained by counting with a counter), and compares these two records. If there is a difference, the interrupt module releases an interrupt signal.

[0057] Specifically, in step S3, when receiving data as the master device, the counter 7 counts the high and low level cycles of the clock signal during data reception, and in the clock comparator 2, the clock signal is compared according to a pre-set transmission frequency. When the comparison fails, the interrupt module 5 issues a clock error interrupt signal. The detailed comparison process is referred to Figure 4 as shown.

[0058] Specifically, in step S3, when transmitting data as the slave device, the counter 7 records the high and low cycle lengths of the clock signal, and then the clock comparator 2 compares the high and low level lengths of the previous clock cycle with those of the current clock cycle. If the comparison result is inconsistent, the interrupt module 5 issues a clock error interrupt signal. The detailed comparison process is referred to Figure 5 as shown.

[0059] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device.

[0060] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A system for detecting abnormal signals on an I2C bus, characterized in that: the detection system includes an I2C bus, a bus information acquisition and parsing module, and an I2C bus detection module; the I2C bus detection module includes a transmitted data comparison module, a received data comparison module, and an interrupt module; the I2C bus includes two signal lines: the SDA line, i.e., the data line, and the SCL line, i.e., the clock line; the bus information acquisition and parsing module is connected to the I2C bus, obtains the real-time information of the data line and the clock line, and transmits the collected bus signals to the received data comparison module after parsing; the transmitted data comparison module is used for data comparison. When the comparison result is inconsistent, an interrupt signal indicating an error in the transmitted data is sent; the transmitted data comparison module includes a first counter Cnt1, a second counter Cnt2, a first data comparator, and a first clock comparator; the received data comparison module parses the clock and data signals on the I2C bus, counts the length of each received data signal, and determines whether it is abnormal; the received data comparison module includes a third counter Cnt3, a fourth counter Cnt4, a second data comparator, and a second clock comparator; the I2C bus is electrically connected to the bus information acquisition and parsing module; the output end of the bus information acquisition and parsing module is respectively connected to the input ends of the transmitted data comparison module and the received data comparison module; the output ends of the transmitted data comparison module and the received data comparison module are connected to the input end of the interrupt module; in the received data comparison module, the third counter Cnt3 is used to count the high or low level length of each 1BIT data, and cooperate with the single BIT length of the data received by the first data comparator to determine whether there is incorrect data on the data bus that should be high level but suddenly changes to low level due to bus contention or other interference.

2. The system for detecting abnormal signals on an I2C bus according to claim 1, characterized in that: the first counter Cnt1 in the transmitted data comparison module is used to count the time interval for data to be sent from the data memory to the bus, and perform data comparison according to the bus data obtained by the first data comparator; the data memory is connected to the I2C bus and is used to receive the transmitted data.

3. The system for detecting abnormal signals on an I2C bus according to claim 2, characterized in that: the first counter Cnt1 in the transmitted data comparison module realizes the comparison of any byte or all bytes to be transmitted through a preset time value.

4. The system for detecting abnormal signals on an I2C bus according to claim 1, characterized in that: the I2C bus detection module is applicable to I2C master devices and I2C slave devices, and simultaneously realizes the detection of the data and clock bus that are being transmitted on the bus.

5. The system for detecting abnormal signals on an I2C bus according to claim 4, characterized in that: A number of devices are connected to the I2C bus. The connected devices include one master and one slave, one master and multiple slaves, multiple masters and one slave, and multiple masters and multiple slaves modes, and support the functions of the I2C bus detection module to be used by the I2C master device and the I2C slave device simultaneously or separately.

6. A method for detecting abnormal signals on an I2C bus, applied to a system for detecting abnormal signals on an I2C bus according to any one of claims 1-5. Characterized in that: This detection method includes the following steps: S1. The bus information acquisition and parsing module acquires real-time bus information, and after parsing the bus information, it transmits the information to the counter, the data comparator, and the clock comparator respectively. S2. During the process of sending data, the sending data comparison module compares the data to be sent in the I2C data register with the data being transmitted on the data bus. When the comparison result is inconsistent, the bus abnormal signal interruption module immediately issues an interruption signal indicating a sending data error. S3. During the process of receiving data, the counter counts the length of each BIT data signal received, and determines whether there is a BIT bit that should have been high level but has been abnormally changed to low level due to bus interference. When an abnormality occurs, the interruption module issues a data interruption error signal.

7. A method for detecting abnormal signals on an I2C bus according to claim 6. Characterized in that: In step S2, when acting as a master device or a slave device, the second counter Cnt2 is used to calculate the clock frequency on the bus, and in cooperation with the first clock comparator, it compares whether the preset clock frequency is consistent with the current bus clock frequency.

8. A method for detecting abnormal signals on an I2C bus according to claim 6. Characterized in that: In step S3, when acting as a master device or a slave device, the fourth counter Cnt4 in the received data comparison module is used to count the bus clock frequency, and in cooperation with the second clock comparator, it compares with the preset clock frequency.

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