Memory operation control method, storage device and memory control circuit unit

Abstract

The present application provides a memory operation control method, a memory storage device and a memory control circuit unit. The method includes: establishing management data including state record data; storing first state information corresponding to a first entity unit in the state record data; receiving an operation instruction from a host system; querying the management data according to the operation instruction; and determining whether to allow the operation instruction to be executed on the first entity unit according to the query result. Thus, the working efficiency of a rewritable non-volatile memory module can be improved.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a memory operation control method, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of smartphones, tablets, and personal computers in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the various portable multimedia devices exemplified above due to their characteristics such as data non-volatility, low power consumption, small size, and lack of mechanical structure.

[0003] Generally, rewritable non-volatile memory modules have several operational guidelines, such as only one write mode being used to write data to the same memory block, memory addresses within the same memory block being used sequentially, and the next instruction only being executed after the previous one has finished. Violation of these guidelines will result in data failing to be correctly written to the rewritable non-volatile memory module. However, in practice, there is no integrated memory operation monitoring mechanism that addresses one or more of these guidelines, leading to frequent execution failures of rewritable non-volatile memory modules. Summary of the Invention

[0004] This invention provides a memory operation control method, a memory storage device, and a memory control circuit unit, which can improve the working efficiency of rewritable non-volatile memory modules.

[0005] An exemplary embodiment of the present invention provides a memory operation control method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical units. The memory operation control method includes: establishing management data, wherein the management data includes status record data; storing first status information corresponding to a first physical unit among the multiple physical units in the status record data; receiving an operation instruction from a host system; querying the management data according to the operation instruction; and determining whether to allow the execution of the operation instruction on the first physical unit based on the query result.

[0006] An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: establish management data, wherein the management data includes status record data; store first status information corresponding to a first physical unit among the multiple physical units in the status record data; receive an operation instruction from the host system; query the management data according to the operation instruction; and determine whether to allow the execution of the operation instruction on the first physical unit based on the query result.

[0007] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used to: establish management data, wherein the management data includes status record data; store first status information corresponding to a first physical unit among the multiple physical units in the status record data; receive an operation instruction from the host system; query the management data according to the operation instruction; and determine whether to allow the execution of the operation instruction on the first physical unit based on the query result.

[0008] Based on the above, after establishing the management data, the first state information corresponding to the first entity unit can be stored in the state record data within the management data. Subsequently, according to the operation instructions from the host system, the management data can be queried, and the query result can be used to determine whether the operation instructions are allowed to be executed on the first entity unit. This effectively reduces execution failure events of the rewritable non-volatile memory module and / or improves the operating efficiency of the rewritable non-volatile memory module. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0014] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0015] Figure 7 This is a schematic diagram of the system architecture of a memory storage device according to an exemplary embodiment of the present invention;

[0016] Figure 8 This is a flowchart illustrating a memory operation control method according to an exemplary embodiment of the present invention. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0018] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0019] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0020] Please refer to Figure 1 and Figure 2The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be connected to the system bus 110.

[0021] In one exemplary embodiment, the host system 11 can be connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0022] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be connected to the memory storage device 10 via wired or wireless means.

[0023] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0024] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0025] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0026] Please refer to Figure 3 The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0027] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0028] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0029] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0030] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0031] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0032] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0033] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0034] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0035] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0036] Please refer to Figure 5The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to a description of the operation of the memory control circuit unit 42.

[0037] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0038] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0039] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0040] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0041] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0042] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0043] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0044] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0045] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0046] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0047] Please refer to Figure 6 The memory management circuit 51 can logically group the physical cells 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. In one exemplary embodiment, a physical cell refers to a physical erase unit. However, in another exemplary embodiment, a physical cell may also contain multiple physical erase units.

[0048] Entity cells 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 may store valid data and / or invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0049] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in the memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses. A, B, and C are all positive integers and can be adjusted according to practical needs; this invention does not impose any limitations.

[0050] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0051] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0052] Figure 7 This is a schematic diagram of the system architecture of a memory storage device according to an exemplary embodiment of the present invention.

[0053] Please refer to Figure 7 The rewritable non-volatile memory module 43 may include multiple chip-enabled (CE) regions CE(0) to CE(M). For example, the rewritable non-volatile memory module 43 may include one or more dies. Dies are obtained from wafers by laser cutting. Each die may be divided into one or more chip-enabled regions. Each chip-enabled region among the chip-enabled regions CE(0) to CE(M) may include one or more planes (also called memory planes). Each plane may include multiple physical cells.

[0054] It should be noted that whether a certain chip enable region can be accessed can be controlled by the chip enable signal corresponding to that chip enable region. For example, when the chip enable signal corresponding to the chip enable region CE(i) is pulled up, the rewritable non-volatile memory module 43 can read data from or store data in the chip enable region CE(i). However, if the chip enable signal corresponding to the chip enable region CE(i) is not pulled up, the rewritable non-volatile memory module 43 cannot read data from or store data in the chip enable region CE(i).

[0055] It should be noted that in this exemplary embodiment, each of the chip enable regions CE(0) to CE(M) contains the same number of planes (denoted as planes (0) to planes (P)). For example, chip enable region CE(0) contains planes 701(0) to 701(P), and chip enable region CE(M) contains planes 702(0) to 702(P), and so on. However, the total number of planes (i.e., P) in different chip enable regions may also be different, and this invention does not impose any limitations on this.

[0056] The memory management circuit 51 can access the rewritable non-volatile memory module 43 via channels (also referred to as memory channels) 71(0) to 71(N). In particular, each of the channels 71(0) to 71(N) can be used to access one or more specific chip enable regions. For example, channel 71(0) can be used to access the chip enable region CE(0) (and planes 701(0) to 701(P)), and channel 71(N) can be used to access the chip enable region CE(M) (and planes 702(0) to 702(P)), and so on, and N can be the same as or different from M. In addition, N, M and P are all positive integers and can be adjusted according to practical needs, which is not limited by the present invention.

[0057] In one exemplary embodiment, the memory management circuit 51 can establish management data. The memory management circuit 51 can store this management data in a specific area (e.g., the system area) within the rewritable non-volatile memory module 43. In one exemplary embodiment, the memory management circuit 51 can set access permissions for physical units in this system area to be inaccessible to the user and / or host system 11. This prevents the user and / or host system 11 from accidentally modifying or deleting data in this system area, thus avoiding malfunction of the memory storage device 10. In one exemplary embodiment, this management data can also be stored in any physical unit and / or other storage area within the rewritable non-volatile memory module 43; this invention is not limited thereto.

[0058] In one exemplary embodiment, the management data includes status record data. The memory management circuit 51 can store status information (also referred to as first status information) corresponding to a specific entity unit (also referred to as a first entity unit) in this status record data. For example, the first entity unit may include… Figure 6 The memory management circuit 51 can then obtain state information (i.e., first state information) related to the first entity unit from the state record data. Furthermore, when the usage state of the first entity unit changes, the memory management circuit 51 can update the first state information in response to this change. The updated first state information can be stored in this state record data.

[0059] In one exemplary embodiment, the first state information may reflect the operating mode (also referred to as the first operating mode) of the first entity unit. For example, the first operating mode may refer to the current operating mode of the first entity unit or a preset operating mode of the first entity unit. For example, the first operating mode may include SLC mode, MLC mode, TLC mode, or QLC mode, and the type of the first operating mode is not limited to these. Thus, the memory management circuit 51 can obtain the operating mode of the first entity unit based on the first state information.

[0060] In one exemplary embodiment, the first state information may include identification information (also referred to as first identification information). The first identification information can be used to identify the operating mode (i.e., the first operating mode) of the first entity unit. For example, if the bit value of a specific bit (also referred to as the first identification bit) in the first identification information is "0", it indicates that the first operating mode is a certain operating mode (e.g., SLC mode). If the bit value of the first identification bit in the first identification information is "1", it indicates that the first operating mode is another operating mode (e.g., MLC mode, TLC mode, or QLC mode). In addition, the first identification information may also represent the type of the first operating mode in other ways, which is not limited by the present invention.

[0061] In one exemplary embodiment, the first state information may also reflect the data storage state of the first entity unit. For example, the first state information may reflect whether the first entity unit has been fully written (i.e., whether all entity programmable units in the first entity unit have been written with data). In one exemplary embodiment, a fully written entity unit may be considered as an entity unit in a stable state, and / or an entity unit that is not fully written may be considered as an entity unit in an unstable state. Thus, the memory management circuit 51 can obtain the data storage state of the first entity unit based on the first state information.

[0062] In one exemplary embodiment, the first status information may include another identification information (also referred to as second identification information). The second identification information can be used to identify the data storage status of the first entity unit. For example, if the bit value of a specific bit in the second identification information (also referred to as the second identification bit) is "1", it indicates that the first entity unit has been filled. If the bit value of the second identification bit is "0", it indicates that the first entity unit is empty (i.e., no data has been written to it) or that the first entity unit has stored data but has not yet been filled. Furthermore, the second identification information may also represent the data storage status of the first entity unit in other ways, and this invention is not limited thereto.

[0063] In one exemplary embodiment, the first state information may further include the address information of the last programmed entity unit (also referred to as the first programmed entity unit) in the first entity unit. For example, assuming that multiple programmed entities have been programmed to store data in the first entity unit, the first programmed entity unit refers to the last programmed entity unit among these programmed entities. Thus, the memory management circuit 51 can obtain the address information of the last programmed entity unit (i.e., the first programmed entity unit) in the first entity unit based on the first state information.

[0064] In one exemplary embodiment, the memory management circuit 51 may receive at least one operation instruction from the host system. For example, the operation instruction may include a write instruction, a read instruction, and an erase instruction. A write instruction instructs the storage of data. A read instruction instructs the reading of data. An erase instruction instructs the erasure of data. Furthermore, the operation instruction may also include other types of operation instructions, which are not limited by the present invention.

[0065] In one exemplary embodiment, the memory management circuit 51 may query the management data according to the operation instruction. Then, the memory management circuit 51 may determine whether to allow the execution of the operation instruction on the first entity unit based on the query result. For example, the query result may include a query result for first status information. For example, based on the query result, the memory management circuit 51 may obtain the first status information. Then, the memory management circuit 51 may determine whether to allow the execution of the operation instruction on the first entity unit based on the first status information.

[0066] In one exemplary embodiment, before issuing a sequence of operation instructions to instruct the rewritable non-volatile memory module 43 to perform an operation corresponding to the operation instructions, the memory management circuit 51 may obtain characteristic information of the operation. The memory management circuit 51 may compare the characteristic information with the query result (or first status information). If (or in response to) the comparison result reflecting that the characteristic information matches the query result (or first status information), the memory management circuit 51 may allow the execution of the operation instructions on the first entity unit. Furthermore, if (or in response to) the comparison result reflecting that the characteristic information does not match the query result (or first status information), the memory management circuit 51 may prohibit the execution of the operation instructions on the first entity unit.

[0067] In one exemplary embodiment, if the memory management circuit 51 allows the execution of the operation instruction on the first physical unit, the memory management circuit 51 may send a sequence of operation instructions to instruct the rewritable non-volatile memory module 43 to perform the operation corresponding to the operation instruction, such as storing data to or reading data from the first physical unit. However, if the memory management circuit 51 does not allow (i.e., prohibits) the execution of the operation instruction on the first physical unit, the memory management circuit 51 may not send the sequence of operation instructions.

[0068] In one exemplary embodiment, by preemptively disabling or preventing the execution of the operation instructions on the first physical unit, the execution failure events of the rewritable non-volatile memory module can be effectively reduced. Alternatively, by preemptively disabling or preventing the execution of the operation instructions on the first physical unit, the expenditure of system resources on predictable failure events can also be effectively reduced.

[0069] In one exemplary embodiment, it is assumed that the operation instruction is a write instruction. Before instructing the rewritable non-volatile memory module 43 to perform a data write operation corresponding to this write instruction, the memory management circuit 51 may obtain characteristic information corresponding to this data write operation. For example, this characteristic information may reflect that this data write operation is programmed starting from a specific entity programming unit (also referred to as the second entity programming unit) in the first entity unit using a specific operating mode (also referred to as the second operating mode).

[0070] After querying the management data, the memory management circuit 51 can compare this characteristic information with the query result (or the first status information). If the comparison result reflects that the second operating mode is the same as the first operating mode and the second entity programming unit is the next entity programming unit after the first entity programming unit, the memory management circuit 51 can determine that this data write operation conforms to the preset operating specifications. In response to the data write operation conforming to the preset operating specifications, the memory management circuit 51 can allow the execution of this write instruction on the first entity unit. For example, when the execution of this write instruction on the first entity unit is allowed, the memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to perform a data write operation corresponding to this write instruction.

[0071] However, if the comparison results show that the second operating mode is different from the first operating mode and / or the second entity programming unit is not the next entity programming unit after the first entity programming unit, the memory management circuit 51 can determine that this data write operation does not conform to the preset operating specifications. In response to this data write operation not conforming to the preset operating specifications, the memory management circuit 51 may not allow (i.e., prohibit) the execution of this write instruction on the first entity unit. For example, if the execution of this write instruction on the first entity unit is not allowed, the memory management circuit 51 may not instruct the rewritable non-volatile memory module 43 to execute the data write operation corresponding to this write instruction. Thus, the expenditure of system resources on operational events that are expected to fail can be reduced.

[0072] In one exemplary embodiment, it is assumed that the operation instruction is a read instruction. Before instructing the rewritable non-volatile memory module 43 to perform a data read operation corresponding to this read instruction, the memory management circuit 51 may obtain characteristic information corresponding to this data read operation. For example, this characteristic information may reflect that this data read operation reads data from a specific entity programmable unit (also referred to as a third entity programmable unit) in the first entity unit using a specific operating mode (i.e., a second operating mode).

[0073] After querying the management data, the memory management circuit 51 can compare this characteristic information with the query result (or the first status information). If the comparison result reflects that the second operating mode is the same as the first operating mode and the third entity programmable unit has been programmed, the memory management circuit 51 can determine that this data read operation conforms to the preset operating specifications. In response to the data read operation conforming to the preset operating specifications, the memory management circuit 51 can allow the execution of this read instruction on the first entity unit. For example, when the execution of this read instruction on the first entity unit is allowed, the memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to perform a data read operation corresponding to this read instruction.

[0074] However, if the comparison results show that the second operating mode is different from the first operating mode and / or the third entity programmable unit has not yet been programmed, the memory management circuit 51 can determine that this data read operation does not conform to the preset operating specifications. In response to this data read operation not conforming to the preset operating specifications, the memory management circuit 51 may not allow (i.e., prohibit) the execution of this read instruction on the first entity unit. For example, if the execution of this read instruction on the first entity unit is not allowed, the memory management circuit 51 may not instruct the rewritable non-volatile memory module 43 to execute the data read operation corresponding to this read instruction. Thus, system resources can also be reduced on operation events that are expected to fail or be invalid (e.g., reading an entity programmable unit that has not yet been programmed).

[0075] In one exemplary embodiment, it is assumed that the operation instruction is an erase instruction. Before instructing the rewritable non-volatile memory module 43 to perform a data erase operation corresponding to this erase instruction, the memory management circuit 51 may obtain characteristic information corresponding to this data erase operation. For example, this characteristic information may reflect that this data erase operation erases the first physical cell based on a specific operating mode (i.e., a second operating mode).

[0076] After querying the management data, the memory management circuit 51 can compare this characteristic information with the query result (or the first status information). If the comparison result reflects that the second operating mode is the same as the first operating mode and the first entity unit has been programmed, the memory management circuit 51 can determine that this data erasure operation conforms to the preset operating specifications. In response to the data erasure operation conforming to the preset operating specifications, the memory management circuit 51 can allow the execution of this erasure instruction on the first entity unit. For example, if the execution of this erasure instruction on the first entity unit is allowed, the memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to perform an erasure operation corresponding to this erasure instruction.

[0077] However, if the comparison results show that the second operating mode is different from the first operating mode and / or the first physical unit has not been programmed, the memory management circuit 51 can determine that this data erasure operation does not conform to the preset operating specifications. In response to this data erasure operation not conforming to the preset operating specifications, the memory management circuit 51 may not allow (i.e., prohibit) the execution of this erasure instruction on the first physical unit. For example, if the execution of this erasure instruction on the first physical unit is not allowed, the memory management circuit 51 may not instruct the rewritable non-volatile memory module 43 to perform the erasure operation corresponding to this erasure instruction. Thus, system resources can also be reduced on operation events that are expected to fail or be invalid (e.g., erasing physical units that have not yet been programmed).

[0078] It should be noted that the characteristic information and related operating procedures mentioned in the foregoing exemplary embodiments are merely examples and are not intended to limit the present invention. In another exemplary embodiment, the characteristic information and related operating procedures can be set and adjusted according to practical needs, and the present invention does not impose any limitations on them.

[0079] In one exemplary embodiment, the management data further includes instruction record data. The memory management circuit 51 may store instruction information corresponding to a specific chip-enabled region (also referred to as the first chip-enabled region) in the rewritable non-volatile memory module 43 in this instruction record data. The first physical unit may be included in the first chip-enabled region.

[0080] In one exemplary embodiment, the instruction information relates to at least one previously issued operation instruction to the first chip enable region. For example, the instruction information may reflect the instruction content of the last operation instruction issued to the first chip enable region. For example, the instruction content may include the type of operation instruction (e.g., a write instruction, a read instruction, or an erase instruction), the data content carried by this operation instruction, and / or the entity unit or entity programmable unit targeted by this operation instruction, etc.

[0081] In one exemplary embodiment, the query result may further include a query result for the instruction information. For example, based on the query result, the memory management circuit 51 can obtain the first status information and the instruction information. Then, the memory management circuit 51 can determine whether to allow the execution of a specific operation instruction on the first entity unit based on the first status information and the instruction information.

[0082] In one exemplary embodiment, two consecutive operation instructions issued for the same chip enable region must conform to specific operation specifications. For example, the next operation instruction may not be executed until the previous one has been completed, including waiting for the cached data of the previous read or write instruction to be moved before executing the next instruction, and / or waiting for the previous operation instruction to be completed before performing a reset. Furthermore, different types of memory storage devices may also set different operation specifications for two consecutive operation instructions issued for the same chip enable region, and this invention does not impose any limitations on this.

[0083] In one exemplary embodiment, the above-mentioned comparison of the characteristic information of the operation behavior corresponding to the operation instruction with the query result, and the determination of whether to allow the operation of the operation instruction to be executed on the first entity unit based on the comparison result, also includes referring to the query result of the instruction information. Only if the relevant operation specifications are met is the execution of the next operation instruction allowed for the first chip enable region. This also reduces the expenditure of system resources on operation events that are expected to fail or be invalid.

[0084] It should be noted that the various operating procedures mentioned in the foregoing exemplary embodiments are merely examples and are not intended to limit the present invention. In other exemplary embodiments, the memory management circuit 51 may determine whether to allow the execution of specific operation instructions on the first entity unit based on the query results of the management data and other operating procedures or strategies, which will not be described one by one here.

[0085] In one exemplary embodiment, after determining that a specific operation instruction is not permitted to be executed on the first physical unit, the memory management circuit 51 may send an alternative response message corresponding to the operation instruction to the host system 11 without executing the operation instruction. For example, for a read instruction, write instruction, or erase instruction that is not permitted to be executed, the memory management circuit 51 may directly send read failure (or success) information, write failure (or success) information, or erase failure (or success) information to the host system 11, depending on practical needs. Thus, the efficiency of the rewritable non-volatile memory module can be improved by reducing the execution of meaningless or expected-to-fail operation instructions.

[0086] Figure 8 This is a flowchart illustrating a memory operation control method according to an exemplary embodiment of the present invention. Please refer to... Figure 8 In step S801, management data is established, wherein the management data includes status record data. In step S802, first status information corresponding to the first entity unit is stored in the status record data. In step S803, an operation instruction from the host system is received. In step S804, the management data is queried according to the operation instruction. In step S805, a decision is made based on the query result as to whether to allow the execution of the operation instruction on the first entity unit.

[0087] However, Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 8 Each step can be implemented as multiple pieces of code or circuits; this application does not impose any restrictions. Furthermore, Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this case does not impose any restrictions.

[0088] In summary, the memory operation control method, memory storage device, and memory control circuit unit provided in the exemplary embodiments of the present invention can improve the working efficiency of rewritable non-volatile memory modules by reducing or prohibiting the execution of meaningless or expected-to-fail operation instructions.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory operation control method, characterized in that, For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units, and the memory operation control method includes: Establish management data, wherein the management data includes status record data; The first state information corresponding to the first entity unit among the plurality of entity units is stored in the state record data; Receive operation instructions from the host system; Query the management data according to the operation instructions; and Based on the query results, a decision is made on whether to allow the execution of the operation instructions on the first entity unit, including prohibiting the execution of meaningless or expected-to-fail operation instructions, and if the meaningless or expected-to-fail operation instructions are not executed, sending alternative response information corresponding to the meaningless or expected-to-fail operation instructions to the host system.

2. The memory operation control method according to claim 1, wherein the first state information reflects the operation mode of the first entity unit.

3. The memory operation control method according to claim 1, wherein the first state information reflects the data storage state of the first entity unit.

4. The memory operation control method according to claim 3, wherein the first state information includes the address information of the last programmed entity unit in the first entity unit.

5. The memory operation control method according to claim 1, wherein the rewritable non-volatile memory module further includes a plurality of chip enable regions, the first entity unit is located in the first chip enable region of the plurality of chip enable regions, the management data further includes instruction log data, and the memory state identification method further includes: The instruction information corresponding to the first chip enable region is stored in the instruction record data, wherein the instruction information is related to at least one operation instruction previously issued to the first chip enable region.

6. The memory operation control method according to claim 5, wherein the instruction information reflects the instruction content of the last operation instruction issued to the first chip enable region.

7. The memory operation control method according to claim 1, wherein the step of determining whether to allow the execution of the operation instruction on the first entity unit based on the query result includes: Before instructing the rewritable non-volatile memory module to perform an operation corresponding to the operation instruction, the characteristic information of the operation is compared with the query result; In response to the comparison result reflecting that the characteristic information matches the query result, the rewritable non-volatile memory module is instructed to perform the operation. as well as If the comparison result indicates that the characteristic information does not match the query result, the rewritable non-volatile memory module is not instructed to perform the operation.

8. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units; as well as The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Establish management data, wherein the management data includes status record data; The first state information corresponding to the first entity unit among the plurality of entity units is stored in the state record data; Receive operation instructions from the host system; Query the management data according to the operation instructions; as well as Based on the query results, a decision is made on whether to allow the execution of the operation instructions on the first entity unit, including prohibiting the execution of meaningless or expected-to-fail operation instructions, and if the meaningless or expected-to-fail operation instructions are not executed, sending alternative response information corresponding to the meaningless or expected-to-fail operation instructions to the host system.

9. The memory storage device according to claim 8, wherein the first state information reflects the operating mode of the first entity unit.

10. The memory storage device according to claim 8, wherein the first state information reflects the data storage state of the first entity unit.

11. The memory storage device according to claim 10, wherein the first state information includes the address information of the last programmed entity unit in the first entity unit.

12. The memory storage device of claim 8, wherein the rewritable non-volatile memory module further includes a plurality of chip enable regions, the first physical unit is located in a first chip enable region of the plurality of chip enable regions, the management data further includes instruction log data, and the memory control circuit unit is further configured to: The instruction information corresponding to the first chip enable region is stored in the instruction record data, wherein the instruction information is related to at least one operation instruction previously issued to the first chip enable region.

13. The memory storage device of claim 12, wherein the instruction information reflects the instruction content of the last operation instruction issued to the first chip enable region.

14. The memory storage device according to claim 8, wherein the memory control circuit unit determines whether to allow the execution of the operation instruction on the first entity unit based on the query result, comprising: Before instructing the rewritable non-volatile memory module to perform an operation corresponding to the operation instruction, the characteristic information of the operation is compared with the query result; In response to the comparison result reflecting that the characteristic information matches the query result, the rewritable non-volatile memory module is instructed to perform the operation. as well as If the comparison result indicates that the characteristic information does not match the query result, the rewritable non-volatile memory module is not instructed to perform the operation.

15. A memory control circuit unit, characterized in that, This is used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units, and the memory control circuit unit includes: Host interface, used to connect to the host system; A memory interface for connecting to the rewritable non-volatile memory module; and The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: Establish management data, wherein the management data includes status record data; The first state information corresponding to the first entity unit among the plurality of entity units is stored in the state record data; Receive operation instructions from the host system; Query the management data according to the operation instructions; and Based on the query results, a decision is made on whether to allow the execution of the operation instructions on the first entity unit, including prohibiting the execution of meaningless or expected-to-fail operation instructions, and if the meaningless or expected-to-fail operation instructions are not executed, sending alternative response information corresponding to the meaningless or expected-to-fail operation instructions to the host system.

16. The memory control circuit unit according to claim 15, wherein the first state information reflects the operating mode of the first entity unit.

17. The memory control circuit unit according to claim 15, wherein the first state information reflects the data storage state of the first entity unit.

18. The memory control circuit unit according to claim 17, wherein the first state information includes the address information of the last programmed entity unit in the first entity unit.

19. The memory control circuit unit of claim 15, wherein the rewritable non-volatile memory module further includes a plurality of chip enable regions, the first physical unit being located in a first chip enable region of the plurality of chip enable regions, the management data further including instruction record data, and the memory management circuit further being used to: The instruction information corresponding to the first chip enable region is stored in the instruction record data, wherein the instruction information is related to at least one operation instruction previously issued to the first chip enable region.

20. The memory control circuit unit according to claim 19, wherein the instruction information reflects the instruction content of the last operation instruction issued to the first chip enable region.

21. The memory control circuit unit of claim 15, wherein the memory management circuit determines whether to allow the execution of the operation instruction on the first entity unit based on the query result, comprising: Before instructing the rewritable non-volatile memory module to perform an operation corresponding to the operation instruction, the characteristic information of the operation is compared with the query result; In response to the comparison result reflecting that the characteristic information matches the query result, the rewritable non-volatile memory module is instructed to perform the operation. as well as If the comparison result indicates that the characteristic information does not match the query result, the rewritable non-volatile memory module is not instructed to perform the operation.

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