Extension method of SPI working mode of FT4232H chip

Abstract

The application provides an extension method of an FT4232H chip SPI working mode, connects the SPI clock signal of the FT4232H chip with a D flip-flop, and extends the working mode of the FT4232H chip SPI after processing by the D flip-flop, so that the SPI interface of the FT4232H chip can be extended from the original 2 working modes to a state of full support of 4 working modes, and the application range of the FT4232H chip is expanded.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly relates to an extension method of an FT4232H chip SPI working mode. BACKGROUND

[0002] The FT4232H chip is produced by the FTDI (Future Technology Devices International) company, and is specially used for level conversion between USB and RS232 / RS4851 / RS422. Data receiving and sending and protocol conversion work can be independently completed by the chip, without manual intervention, without programming the chip firmware, which brings great convenience to circuit development and design personnel. Compared with similar products, the main features of the FT4232H chip include: 1) single-chip to 4-way serial port conversion, the entire interface protocol is internally fixed, without additional programming; 2) supporting 480 Mb / s USB 2.0 high-speed specification, and can be configured under various industrial standard serial or parallel interfaces (such as UART or FIFO); 3) through external EEPROM, the VID, PID, device serial number and device related description of the product can be provided; 4) having the characteristics of low power consumption and high speed, and having an industrial temperature range of -40 ~ +85℃.

[0003] At present, the FT4232H chip is mostly developed according to the supported ports of the chip in the actual use process, for example, USB to four-way UART, which can simulate JTAG, SPI, I2C, Bit-Bang or other synchronous serial modes through two multi-protocol synchronous serial engines (MPSSE) of the FT4232H. Among the many interfaces, SPI (Serial Peripheral Interface, serial peripheral interface) is a high-speed, full-duplex and synchronous communication bus, which only occupies four lines on the pin of the chip, and can greatly save the pins of the chip, saving space for the layout of the PCB. It is just due to this simple and easy-to-use characteristic that the compatibility of SPI has become one of the necessary functions of many chips. The SPI protocol has four working modes in total, but the existing FT4232H chip only supports two working modes of MODE0 and MODE2 in SPI, so it can be seen that the support of the FT4232H chip for the SPI protocol in the prior art is not complete and comprehensive enough, and the compatibility is not enough, and there is still certain limitation when developing using the FT4232H chip. SUMMARY

[0004] The application aims at overcoming the defects of the prior art, and provides an extension method of an SPI working mode of an FT4232H chip, which can extend the SPI interface of the FT4232H chip from the original 2 working modes to a full support state of 4 working modes, so as to expand the application range of the FT4232H chip.

[0005] The application solves the technical problems by adopting the technical solution of an extension method of an SPI working mode of an FT4232H chip, wherein the SPI clock signal of the FT4232H chip is connected to a D flip-flop, and the working mode of the SPI of the FT4232H chip is extended after the processing of the D flip-flop.

[0006] Further, the D flip-flop requires a forward edge triggering mode.

[0007] Further, the delay of the D flip-flop is required to be in the nanosecond level, preferably, the SN74LVC74A flip-flop is used, and the data delay is only 5.2 ns.

[0008] Further, the SPI clock signal spi0_clk of the FT4232H chip is connected to the 1LCK pin of the D flip-flop, and the SPI data signal spi0_data is connected to the 1D pin of the D flip-flop.

[0009] Further, after the processing of the D flip-flop, a new SPI data signal spi1_data is output from the 1Q pin, and a clock signal spi1_clk is directly pulled out from the spi0_clk, and the spi1_data and the spi1_clk form a new SPI signal.

[0010] Further, when the SPI working mode of the FT4232H is configured as the MODE0 mode, the working mode of the SPI signal formed by the two SPI data signals spi1_data and spi1_clk is the MODE1 mode.

[0011] Further, when the SPI working mode of the FT4232H is configured as the MODE2 mode, the working mode of the SPI signal formed by the two SPI data signals spi1_data and spi1_clk is the MODE3 mode.

[0012] Compared with the prior art, the application has the beneficial effects that the SPI interface of the FT4232H chip can be extended from the original 2 working modes to a full support state of 4 working modes by the external circuit, and the application range of the FT4232H chip is expanded. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 This is the timing diagram of SPI in working mode MODE0, at this time CPHA=0, CPOL=0;

[0014] Figure 2 This is the timing diagram of SPI in working mode MODE1, at this time CPHA=1, CPOL=0;

[0015] Figure 3 This is the timing diagram of SPI in working mode MODE2, at this time CPHA=0, CPOL=1;

[0016] Figure 4 This is the timing diagram of SPI in working mode MODE3, at this time CPHA=1, CPOL=1;

[0017] Figure 5 This is a simplified timing diagram of SPI MODE0 in Example 1 of the present invention;

[0018] Figure 6 This is a simplified timing diagram of SPI MODE2 in Example 1 of the present invention;

[0019] Figure 7 This is a simplified structural diagram of Example 1 of the present invention;

[0020] Figure 8 Detailed circuit diagram of embodiment 1 of the present invention; DETAILED DESCRIPTION

[0021] The present invention will be further described below with reference to the accompanying drawings and examples, but these specific embodiments do not limit the scope of protection of the present invention in any way. Example

[0022] like Figures 1-8 As shown in the figure, a method for expanding the SPI working mode of the FT4232H chip is shown. The SPI clock signal from the FT4232H chip is connected to a D flip-flop. The D flip-flop requires the trigger mode to be positive edge triggered. In this embodiment, the SN74LVC74A flip-flop is used, and its data delay is only 5.2ns.

[0023] Connect the SPI clock signal spi0_clk from the FT4232H chip to the 1LCK pin of the D flip-flop, and the SPI data signal spi0_data to the 1D pin of the D flip-flop; after the SPI clock signals spi0_clk and spi0_data are processed by the D flip-flop, a new SPI data signal spi1_data is output from the 1Q pin, and a clock signal spi1_clk is directly pulled out from spi0_clk. spi1_data and spi1_clk form a new SPI signal.

[0024] When the SPI working mode of FT4232H is configured as MODE0 mode, the working mode of the SPI signal composed of the two SPI data signals spi1_data and spi1_clk is MODE1 mode. When the SPI working mode of FT4232H is configured as MODE2 mode, the working mode of the SPI signal composed of the two SPI data signals spi1_data and spi1_clk is MODE3 mode.

[0025] The specific principles of the application are as follows:

[0026] The four working modes of SPI are shown in Table 1 as follows:

[0027] Table 1

[0028]

[0029] In the table:

[0030] CPOL: clock signal level when SPI is idle (1: high level, 0: low level);

[0031] CPHA: SPI samples at the first edge of the clock (1: start at the second edge, 0: start at the first edge).

[0032] CPOL = 0, indicating that when SCLK = 0, it is in an idle state, so the effective state is when SCLK is at a high level;

[0033] CPOL = 1, indicating that when SCLK = 1, it is in an idle state, so the effective state is when SCLK is at a low level;

[0034] CPHA = 0, indicating that data sampling is at the first edge, and data transmission is at the second edge;

[0035] CPHA = 1, indicating that data sampling is at the second edge, and data transmission is at the first edge.

[0036] The timing diagrams of the four modes of SPI are shown in the accompanying Figures 1-4 :

[0037] The difference between the MODE0 mode and the MODE1 mode of SPI is that the data sampling points are different, the MODE0 mode samples at the first edge of the clock (rising edge), and the MODE1 mode samples at the second edge of the clock (falling edge). The D flip-flop requires forward edge triggering, and the delay requirement is in the order of ns. Currently, SN74LVC74A is selected, and its data delay is only 5.2ns.

[0038] Signal connection mode: the SPI clock signal spi0_clk from the FT4232H chip is connected to the 1LCK pin of the D flip-flop, the SPI data signal spi0_data is connected to the 1D pin of the D flip-flop, and a new spi data signal spi1_data is output from the 1Q pin after the processing of the D flip-flop. A clock signal spi1_clk is directly pulled out from spi0_clk, and the spi1_data and spi1_clk form a new SPI signal.

[0039] When the SPI working mode of the FT4232H is configured as the MODE0 mode, the new SPI signal formed by the spi1_data and spi1_clk has the working mode as the MODE1 mode. As shown in Figure 5 When the SPI signal (spi0_clk, spi0_data) of the FT4232H chip works in the MODE0 mode, the data 01010101 is sent, and the data read by the SPI signal (spi1_clk, spi1_data) after the D flip-flop in the MODE1 mode is also 01010101, so that the SPI signal MODE1 working mode of the FT4232H chip is realized.

[0040] As shown in Figure 6 When the SPI working mode of the FT4232H is configured as the MODE2 mode, the new SPI signal formed by the spi1_data and spi1_clk has the working mode as the MODE3 mode. As shown in Figure 6 When the SPI signal (spi0_clk, spi0_data) of the FT4232H chip works in the MODE2 mode, the data 01010101 is sent, and the data read by the SPI signal (spi1_clk, spi1_data) after the D flip-flop in the MODE3 mode is also 01010101, so that the SPI signal MODE3 working mode of the FT4232H chip is realized.

[0041] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the technical solution of the present application, and the equivalent embodiments with equivalent changes are equivalent. Any simple modification, equivalent change and modification of the above embodiments based on the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A method for extending the SPI working mode of the FT4232H chip, characterized by: Connect the SPI clock signal from the FT4232H chip to a D-type flip-flop. After being processed by the D-type flip-flop, the SPI working mode of the FT4232H chip is expanded. The SPI clock signal spi0_clk from the FT4232H chip is connected to the 1LCK pin of the D flip-flop, and the SPI data signal spi0_data is connected to the 1D pin of the D flip-flop; After the SPI clock signals spi0_clk and spi0_data are processed by the D flip-flop, a new SPI data signal spi1_data is output from the 1Q pin, and a clock signal spi1_clk is directly pulled out from spi0_clk. spi1_data and spi1_clk form a new SPI signal.

2. The method for extending the FT4232H chip SPI operating mode according to claim 1, wherein: The triggering mode of the D flip-flop is positive edge triggering.

3. The method for extending the SPI operating mode of the FT4232H chip according to any one of claims 1 to 2, wherein: The delay requirement of the D flip-flop is in nanosecond level.

4. The method for extending the FT4232H chip SPI operating mode according to claim 1, wherein: When the SPI working mode of FT4232H is configured to MODE0 mode, the working mode of the SPI signal composed of the two SPI data signals spi1_data and spi1_clk is MODE1 mode.

5. The method for expanding the FT4232H chip SPI operating mode according to claim 1, wherein: When the SPI working mode of FT4232H is configured to MODE2 mode, the working mode of the SPI signal composed of the two SPI data signals spi1_data and spi1_clk is MODE3 mode.

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