A kind of I 2 C interface circuit and control method thereof

Abstract

The present invention provides a 2 C interface circuit and control method thereof, applicable to host mode and slave mode, including: I 2 C register module, used to 2 The C register module is configured to generate an SCL generation circuit for the SCL clock signal, a state machine that performs state transitions and sends control signals based on the SCL clock signal and the SDA data signal, and a control logic circuit for serial-to-parallel conversion of data sent or received by the control bus and detecting start / stop signals. The state machine includes a state machine in the host mode state and a state machine in the slave mode state. The use of an improved state machine reduces circuit area, reduces power consumption, and simplifies software control. During data transmission, only two flag bits and one register need to be controlled for reading and writing. In slave mode, data transmission errors are resolved by changing the response and SCL clock signal pull-down positions.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an I 2 C interface circuit and control method thereof. Background Art

[0002] I 2 The Inter-Integrated-Circuit control bus (C) is a serial communication control bus developed by Philips. It is a high-performance serial control bus with the control bus arbitration and high-speed and low-speed device synchronization functions required by multi-host systems. It is widely used in consumer electronics, communications products, and industrial electronics. It is a control bus standard widely adopted in the field of microelectronic communication control. It supports multi-master control (multimastering), where any device capable of sending and receiving can become the master control bus. 2 The C control bus realizes serial signal transmission of each device on the control bus through two signal lines, one is the data line SDA (Serial Data), and the other is the clock signal line SCL (Serial Clock). It has the advantages of fewer interface lines, small device packaging, and faster communication speed.

[0003] However, in the actual project development process, since the existing interface circuits are mostly designed with state machines, the central processing unit (CPU) is often required to frequently write configuration data to the registers inside the interface circuit, so that the state machine can jump according to the transmission format. This makes the software operation very complicated, the circuit area is large, and the power consumption is high. At the same time, due to the I 2 There is a host on the C control bus that does not detect whether the SCL level is pulled down during data transmission, making the existing I 2 The C-interface circuit can only avoid the possibility of signal transmission errors by reducing the transmission speed of the signal. Summary of the Invention

[0004] The present invention provides a 2 The C interface circuit and its control method are intended to solve the problem of transmission error caused by the host of the software simulating IO port not detecting that SCL is pulled down.

[0005] In order to achieve the above object, the present invention provides a 2 C interface circuit, including:

[0006] I 2 C register module;

[0007] SCL generation circuit for 2 The configuration of the C register module generates the SCL clock signal;

[0008] The state machine changes state according to the SCL clock signal and the SDA data signal, and sends a control signal. The state of the state machine includes the master mode state and the slave mode state;

[0009] A control logic circuit is used to perform serial-to-parallel conversion on the data transmitted by the control bus and detect the start / stop signal of the state machine;

[0010] I 2 The first signal transmission end of the C register module is connected to the central processing unit CPU through the control bus. 2 The second signal transmission end of the C register module is connected to the first signal transmission end of the SCL generation circuit, the second signal transmission end of the SCL generation circuit is connected to the first signal transmission end of the state machine, the third signal transmission end of the SCL generation circuit is connected to the first input end of the first buffer, the second signal transmission end of the state machine is connected to the second input end of the first buffer, the output end of the first buffer is respectively connected to one end of the SCL clock signal line and the third signal transmission end of the state machine, the fourth signal transmission end of the state machine is connected to the first signal transmission end of the control logic circuit, the fifth signal transmission end of the state machine is connected to the first input end of the second buffer, the second signal transmission end of the control logic circuit is connected to the central processing unit CPU through the control bus, the third signal transmission end of the control logic circuit is connected to the sixth signal transmission end of the state machine, and the output end of the second buffer is respectively connected to one end of the SDA data line, the seventh signal transmission end of the state machine, and the fourth signal transmission end of the control logic circuit.

[0011] Furthermore, I 2 The C register module includes:

[0012] A status register, wherein a signal transmission end of the status register is connected to a first signal transmission end of the control bus;

[0013] An address register, wherein a signal transmission end of the address register is connected to a second signal transmission end of the control bus;

[0014] a speed register, wherein a signal transmission end of the speed register is connected to a third signal transmission end of the control bus;

[0015] The control register has a first signal transmission terminal connected to the fourth signal transmission terminal of the control bus, and a second signal transmission terminal of the control register is connected to the first signal transmission terminal of the SCL generation circuit.

[0016] Further, the SCL generation circuit includes an SCL clock generation module and a first OUTPUT module;

[0017] The first signal transmission end of the SCL clock generation module is used as the first signal transmission end of the SCL generation circuit, and is connected to the second signal transmission end of the control register. The second signal transmission end of the SCL clock generation module is connected to the signal transmission end of the state machine. The third signal transmission end of the SCL clock generation module is connected to the input end of the first OUTPUT module. The output end of the first OUTPUT module is connected to the first input end of the first buffer, and the SCL0 signal is transmitted to the first buffer.

[0018] Furthermore, the control logic circuit includes: a synchronization logic module, an I2CDAT register, a match detection module, a second OUTPUT module and an ACK module;

[0019] The first signal transmission terminal of the synchronization logic module is connected to the fourth signal transmission terminal of the state machine, the second signal transmission terminal of the synchronization logic module is connected to the first signal transmission terminal of the I2CDAT register, the third signal transmission terminal of the synchronization logic module is connected to the input terminal of the second OUTPUT module, the output terminal of the second OUTPUT module is connected to the second input terminal of the second buffer, the output terminal of the second buffer is connected to the input terminal of the ACK module, the input terminal of the ACK module is connected to the seventh signal transmission terminal of the state machine, the output terminal of the ACK module is connected to the input terminal of the I2CDAT register, the second signal transmission terminal of the I2CDAT register is connected to the control bus, the output terminal of the I2CDAT register is connected to the input terminal of the match detection module, and the output terminal of the match detection module is connected to the sixth signal transmission terminal of the state machine.

[0020] The present invention also provides a 2 C interface circuit control method, applied to the above-mentioned I 2 C interface circuit, including:

[0021] The state machine in the host mode is designed to have 12 states, namely: idle state, host start state, send address state, answer address state, first waiting state, host send data state, answer send data state, second waiting state, host receive data state, third waiting state, answer receive data state and stop state;

[0022] The state machine in host mode includes the following state jump process:

[0023] After the CPU is powered on or restarted, I 2 C interface circuit according to I 2 The mode control bit of the C register module jumps from the idle state to the host start state;

[0024] I 2 The C register sends a start signal to the control bus, and after sending the start signal, it jumps to the send address state;

[0025] I 2 The C register sends the slave device address and read / write control word to the control bus serially, and jumps to the response address state after sending the slave device address and read / write control word;

[0026] I 2 The C interface circuit transfers the control right of the data line SDA from the state machine in the master mode state to the state machine in the slave mode state. If the state machine in the slave mode state does not receive the slave response signal, it jumps to the master start state; if the state machine in the slave mode state receives the slave response signal, it jumps to the first waiting state or the master receiving data state according to the written read / write control word;

[0027] When in the first waiting state, the SCL generation circuit stops outputting the SCL clock signal, and the central processing unit CPU writes data to the control logic circuit through the control bus, and automatically jumps to the host data sending state after the data is written;

[0028] The control logic circuit sends data serially to the control bus, and automatically jumps to the data sending state after sending the data;

[0029] In the response data sending state, I 2 The C interface circuit transfers the control right of the SDA data line from the state machine in the master mode to the state machine in the slave mode. If the state machine in the slave mode receives a slave response signal, it jumps to the second waiting state. If the state machine in the slave mode does not receive a slave response signal, it jumps to the stop state.

[0030] When in the second waiting state, the SCL generating circuit stops outputting the SCL clock signal and waits for the central processing unit CPU to write data to the control logic circuit through the control bus, and then jumps to the host sending data state. If I 2 If the stop flag of the C register module is high, it jumps to the stop state;

[0031] When the host is in the data receiving state, the control logic circuit automatically jumps to the third waiting state after receiving data serially from the control bus. After the central processing unit CPU finishes reading the data of the control logic circuit through the control bus, it jumps to the data receiving state.

[0032] In the state of receiving data, when I 2 When the stop flag of the C register module is low, the control logic circuit controls the data line SDA to output a low level, and replies to the ACK signal of the state machine in the slave mode state and jumps to the master receiving data state; when I 2When the stop flag bit of the C register module is high, the control logic circuit controls the data line SDA to output a high level and notifies the state machine in the slave mode to jump to the stop state after the data transmission is completed;

[0033] In the stopped state, I 2 The C interface circuit sends a stop signal to the control bus, and automatically jumps to the idle state after sending the stop signal.

[0034] Furthermore, it also includes:

[0035] The state machine in the slave mode is designed to have 11 states, namely: idle state, slave start state, slave address receiving state, address response state, first waiting state, slave data sending state, data sending response state, second waiting state, slave data receiving state, data receiving response state and third waiting state;

[0036] The state machine in slave mode includes the following state jump process:

[0037] After the CPU is powered on or restarted, I 2 The C interface circuit jumps from the idle state to the slave start state according to the mode control bit of the I2C register module;

[0038] I 2 The C register sends a start signal to the control bus, and after sending the start signal, it jumps to the state of receiving the slave address;

[0039] In the slave address receiving state, the control bus serially sends the slave device address and read / write control word. When the received slave address is inconsistent with the self-configured address or the general broadcast address, it jumps to the slave start state. When the received slave address is consistent with the self-configured address or the general broadcast address and the read / write control word is "write", it jumps to the response address state. When the received slave address is consistent with the self-configured address or the general broadcast address and the read / write control word is "read", it jumps to the response address state according to I 2 The software and hardware identification bits of the C register module determine the jump to the response address state or the first waiting state;

[0040] In the response address state, I 2 The C register responds to the address signal of the state machine in the host mode state. The state machine in the host mode state reads and writes the control word and I 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state, the slave sending data state, and the first waiting state;

[0041] When in the first waiting state, I 2The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter the waiting state. After the central processing unit CPU writes data to the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and 2 The software and hardware identification bits of the C register module automatically jump to the slave sending data state and response address state;

[0042] The control logic circuit sends data serially to the control bus, and after sending the data, it automatically jumps to the state of responding to sending data;

[0043] In the response data sending state, I 2 If the C interface circuit receives a response signal from the host, it jumps to the second waiting state. If it does not receive a response signal from the host, it jumps to the slave starting state.

[0044] When in the second waiting state, I 2 The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter the second waiting state. After the central processing unit CPU writes data to the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and automatically jumps to the slave data sending state;

[0045] In the slave receiving data state, the control logic circuit receives the data sent by the control bus, and after the reception is completed, the control logic circuit receives the data sent by the control bus, and then receives the data according to the I 2 The software and hardware identification bits of the C register module automatically jump to the response data reception state and the third waiting state;

[0046] In the state of receiving data, I 2 C interface circuit responds to the ACK signal of the state machine in the host mode state, according to the I 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state and the third waiting state;

[0047] In the third waiting state, I 2 The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter the third waiting state. After the central processing unit CPU reads the data of the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state and the response receiving data state.

[0048] The above solution of the present invention has the following beneficial effects:

[0049] The present invention provides 2 C interface circuit only includes I 2 C register module, used to2 The SCL generation circuit generates an SCL clock signal according to the configuration of the C register module, a state machine that performs state transitions and sends a control signal according to the SCL clock signal and the SDA data signal, and a control logic circuit for performing serial-to-parallel conversion on the data sent or received by the control bus and detecting the start / stop signal. The state machine includes a state machine in the host mode state and a state machine in the slave mode state; it is compatible with hosts with non-standard protocols, and the use of an improved state machine can not only reduce circuit area and power consumption, but also solve the problem of data transmission errors caused by the host of the software-simulated IO port not detecting that the SCL clock signal is pulled down by changing the pull-down position of the response and SCL clock signals when in slave mode; the embodiment of the present invention also provides a method suitable for I 2 The control method of the C interface circuit only needs to control two flag bits and one register for reading and writing during data transmission, which simplifies software control.

[0050] Other beneficial effects of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 In the embodiment of the present invention, 2 Schematic diagram of the structure of the C interface circuit;

[0052] Figure 2 (a) is a schematic diagram of an embodiment of the present invention in a host sending mode, (b) is a schematic diagram of an embodiment of the present invention in a host receiving mode, (c) is a schematic diagram of an embodiment of the present invention in a slave sending mode, and (d) is a schematic diagram of an embodiment of the present invention in a slave receiving mode;

[0053] Figure 3 This is a jump flow chart of a state machine in the host mode state in an embodiment of the present invention;

[0054] Figure 4 4 is a jump flow chart of the state machine in the slave mode state in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] To make the technical problems, technical solutions, and advantages to be solved by the present invention more clear, the following is a detailed description with reference to the accompanying drawings and specific embodiments. It is obvious that the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0056] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0057] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to a locking connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0058] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0059] The present invention aims at solving the existing problems and provides a 2 C interface circuit and control method thereof.

[0060] like Figure 1 As shown, the embodiment of the present invention provides an I 2 C interface circuit, suitable for master mode and slave mode, including:

[0061] I 2 C register module;

[0062] SCL generation circuit for 2 The configuration of the C register module generates the SCL clock signal;

[0063] The state machine changes state according to the SCL clock signal and the SDA data signal, and sends a control signal. The state of the state machine includes the master mode state and the slave mode state;

[0064] A control logic circuit is used to perform serial-to-parallel conversion on the data transmitted (sent or received) by the control bus and detect the start / stop signal sent by the state machine;

[0065] I 2 The first signal transmission end of the C register module is connected to the central processing unit CPU through the control bus. 2The second signal transmission end of the C register module is connected to the first signal transmission end of the SCL generation circuit, the second signal transmission end of the SCL generation circuit is connected to the first signal transmission end of the state machine, the third signal transmission end of the SCL generation circuit is connected to the first input end of the first buffer, the second signal transmission end of the state machine is connected to the second input end of the first buffer, the output end of the first buffer is respectively connected to one end of the SCL clock signal line and the third signal transmission end of the state machine, the fourth signal transmission end of the state machine is connected to the first signal transmission end of the control logic circuit, the fifth signal transmission end of the state machine is connected to the first input end of the second buffer, the second signal transmission end of the control logic circuit is connected to the central processing unit CPU through the control bus, the third signal transmission end of the control logic circuit is connected to the sixth signal transmission end of the state machine, and the output end of the second buffer is respectively connected to one end of the SDA data line, the seventh signal transmission end of the state machine, and the fourth signal transmission end of the control logic circuit.

[0066] Specifically, I 2 The C register module includes:

[0067] A status register, wherein a signal transmission end of the status register is connected to a first signal transmission end of the control bus;

[0068] An address register, wherein a signal transmission end of the address register is connected to a second signal transmission end of the control bus;

[0069] a speed register, wherein a signal transmission end of the speed register is connected to a third signal transmission end of the control bus;

[0070] The control register has a first signal transmission terminal connected to the fourth signal transmission terminal of the control bus, and a second signal transmission terminal of the control register is connected to the first signal transmission terminal of the SCL generation circuit.

[0071] Specifically, the SCL generation circuit includes an SCL clock generation module and a first OUTPUT module;

[0072] The first signal transmission end of the SCL clock generation module is used as the first signal transmission end of the SCL generation circuit, and is connected to the second signal transmission end of the control register. The second signal transmission end of the SCL clock generation module is connected to the signal transmission end of the state machine. The third signal transmission end of the SCL clock generation module is connected to the input end of the first OUTPUT module. The output end of the first OUTPUT module is connected to the first input end of the first buffer, and the SCL0 signal is transmitted to the first buffer.

[0073] Specifically, the control logic circuit includes: a synchronization logic module, an I2CDAT register, a matching detection module, a second OUTPUT module and an ACK module for confirming that the sent data has been received (ACKnowledgeCharacter, ACK);

[0074] The first signal transmission terminal of the synchronization logic module is connected to the fourth signal transmission terminal of the state machine, the second signal transmission terminal of the synchronization logic module is connected to the first signal transmission terminal of the I2CDAT register, the third signal transmission terminal of the synchronization logic module is connected to the input terminal of the second OUTPUT module, the output terminal of the second OUTPUT module is connected to the second input terminal of the second buffer, the output terminal of the second buffer is connected to the input terminal of the ACK module, the input terminal of the ACK module is connected to the seventh signal transmission terminal of the state machine, the output terminal of the ACK module is connected to the input terminal of the I2CDAT register, the second signal transmission terminal of the I2CDAT register is connected to the control bus, the output terminal of the I2CDAT register is connected to the input terminal of the match detection module, and the output terminal of the match detection module is connected to the sixth signal transmission terminal of the state machine.

[0075] The embodiment of the present invention also provides a 2 The control method of the C interface circuit is applied to the above I 2 C interface circuit, when I 2 When the C interface circuit works in host mode, it is referred to as host. 2 When the C interface circuit works in slave mode, it is referred to as slave; the state machine is used as I 2 The core of the C interface circuit can be based on the I 2 C interface circuit works in master mode or slave mode to configure I 2 The mode control bit of the control register in the C register module enters the state machine in the master mode state or the state machine in the slave mode state. 2 When the C interface circuit works in the master mode, the master first sends a start signal and a 7-bit device address and a 1-bit read / write control bit. If the slave responds, the next working state is determined according to the read / write control bit. At this time, if the 1-bit read / write control bit sent is 1, the master starts to follow Figure 2 (b) The host starts to work in the receiving mode format; if the received 1-bit read / write control bit is 1, the host starts to work according to the attached Figure 2 The host sends the mode format shown in (a) to start working;

[0076] When the read / write control bit is 0, the host reports an interrupt message and stops sending the SCL clock signal. The central processing unit CPU writes data to the I2CDAT register in the control logic circuit through the control bus. After the data is written to the I2CDAT register, the host sends 8 bits of data to the control bus. After receiving the response signal from the slave, the host reports an interrupt message and stops sending the SCL clock signal. After the data is written to the I2CDAT register, the host sends 8 bits of data to the control bus until the last bit of data is sent. After receiving the response signal from the slave, the host sends a stop signal.

[0077] When the read / write control bit is 1, after receiving 8 bits of data, the host stops sending the SCL clock signal and reports an interrupt message. After the I2CDAT register finishes reading the data, it responds to the slave's response signal, then receives 8 bits of data from the control bus, stops sending the SCL clock signal, and reports an interrupt message. Until the last bit of data is sent, the host will not respond to the slave's response signal, and the host sends a stop signal.

[0078] When I 2 When the C interface circuit works in slave mode, the slave detects the start signal and starts to receive the 7-bit I 2 C address data and 1-bit read / write control bit. If the 7-bit I 2 C address data and the I 2 If the preset value of the C interface circuit is consistent, the slave device will control the bus to send a response signal to notify the host that the first frame of data has been received correctly. At this time, if the received 1-bit read / write control bit is 1, the slave device will start to follow the Figure 2 (d) The slave starts to work in the sending mode format shown in FIG. If the received 1-bit read / write control bit is 1, the slave starts to work in accordance with Figure 2 The slave receive mode format shown in (c) starts operation.

[0079] When the read / write control bit is 0, 8 bits of data are received on the control bus. After responding to the host's response signal, the SCL clock signal is pulled low and an interrupt signal is issued until the data is read from the I2CDAT register. The SCL clock signal is released and data continues to be received on the control bus until a stop signal is received, ending the transmission.

[0080] When the read / write control bit is 1, 8 bits of data are sent to the control bus. After the host responds to the acknowledge signal, the SCL clock signal is pulled low and an interrupt signal is issued until the data is written to the I2CDAT register. The SCL clock signal is released and data is sent to the control bus. The transmission ends when the host does not respond to the acknowledge signal or receives a stop signal.

[0081] It should be noted that the signal value 0 appearing in the embodiment of the present invention corresponds to a low level of the digital potential, and the signal value 1 corresponds to a high level of the digital potential.

[0082] Specifically, the embodiment of the present invention designs the state machine in the host mode state into 12 states, namely: idle state, host start state, send address state, answer address state, first wait state, host send data state, answer send data state, second wait state, host receive data state, third wait state, answer receive data state and stop state;

[0083] like Figure 3 As shown, the state transition process of the state machine in host mode is as follows:

[0084] After the CPU is powered on or restarted, I 2 C interface circuit according to I 2 The mode control bit of the C register module jumps from the idle state to the host start state;

[0085] I 2 The C register module sends a start signal to the control bus and jumps to the send address state after sending the start signal;

[0086] I 2 The C register module sends the slave device address and read / write control word serially to the control bus, and jumps to the response address state after sending the slave device address and read / write control word;

[0087] I 2 The C interface circuit transfers the control right of the SDA data line from the state machine in the master mode state to the state machine in the slave mode state. If the state machine in the slave mode state does not receive the slave response signal, it jumps to the master start state; if the state machine in the slave mode state receives the slave response signal, it jumps to the first waiting state or the master receiving data state according to the written read / write control word;

[0088] When in the first waiting state, the SCL generation circuit stops outputting the SCL clock signal, and the central processing unit CPU writes data to the control logic circuit through the control bus, and automatically jumps to the host data sending state after the data is written;

[0089] The control logic circuit sends data serially to the control bus, and automatically jumps to the data sending state after sending the data;

[0090] In the response data sending state, I 2The C interface circuit transfers the control right of the SDA data line from the state machine in the master mode to the state machine in the slave mode. If the state machine in the slave mode receives a slave response signal, it jumps to the second waiting state. If the state machine in the slave mode does not receive a slave response signal, it jumps to the stop state.

[0091] When in the second waiting state, the SCL generating circuit stops outputting the SCL clock signal and waits for the central processing unit CPU to write data to the control logic circuit through the control bus, and then jumps to the host sending data state. If I 2 If the stop flag of the C register module is high, it jumps to the stop state;

[0092] When the host is in the data receiving state, the control logic circuit automatically jumps to the third waiting state after receiving data serially from the control bus. After the central processing unit CPU finishes reading the data of the control logic circuit through the control bus, it jumps to the data receiving state.

[0093] In the state of receiving data, when I 2 When the stop flag of the C register module is low, the control logic circuit controls the data line SDA to output a low level, and replies to the ACK signal of the state machine in the slave mode state and jumps to the master receiving data state; when I 2 When the stop flag bit of the C register module is high, the control logic circuit controls the data line SDA to output a high level and notifies the state machine in the slave mode to jump to the stop state after the data transmission is completed;

[0094] In the stopped state, I 2 The C interface circuit sends a stop signal to the control bus, and automatically jumps to the idle state after sending the stop signal.

[0095] Specifically, the embodiment of the present invention designs the state machine in the slave mode state into 11 states, namely: idle state, slave start state, slave address receiving state, address response state, first waiting state, slave data sending state, data sending response state, second waiting state, slave data receiving state, data receiving response state and third waiting state;

[0096] like Figure 4 As shown, the state transition process of the state machine in slave mode is as follows:

[0097] After the CPU is powered on or restarted, I 2 C interface circuit according to I 2 The mode control bit of the C register module jumps from the idle state to the slave start state;

[0098] I 2The C register module sends a start signal to the control bus, and after sending the start signal, it jumps to the receiving slave address state;

[0099] In the slave address receiving state, the control bus serially sends the slave device address and read / write control word. When the received slave address is inconsistent with the self-configured address or the general broadcast address, it jumps to the slave start state. When the received slave address is consistent with the self-configured address or the general broadcast address and the read / write control word is "write", it jumps to the response address state. When the received slave address is consistent with the self-configured address or the general broadcast address and the read / write control word is "read", it jumps to the response address state according to I 2 The software and hardware identification bits of the C register module determine the jump to the response address state or the first waiting state;

[0100] In the response address state, I 2 The C register module responds to the address signal of the state machine in the host mode state. The state machine in the host mode state reads and writes the control word and I 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state, the slave sending data state, and the first waiting state;

[0101] When in the first waiting state, I 2 The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter the waiting state. After the central processing unit CPU writes data to the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and 2 The software and hardware identification bits of the C register module automatically jump to the slave sending data state and response address state;

[0102] The control logic circuit sends data serially to the control bus, and after sending the data, it automatically jumps to the state of responding to sending data;

[0103] In the response data sending state, I 2 If the C interface circuit receives a response signal from the host, it jumps to the second waiting state. If it does not receive a response signal from the host, it jumps to the slave starting state.

[0104] When in the second waiting state, I 2 The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter the second waiting state. After the central processing unit CPU writes data to the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and automatically jumps to the slave data sending state;

[0105] In the slave receiving data state, the control logic circuit receives the data sent by the control bus, and after the reception is completed, the control logic circuit receives the data sent by the control bus, and then receives the data according to the I 2The software and hardware identification bits of the C register module automatically jump to the response data reception state and the third waiting state;

[0106] In the state of receiving data, I 2 C interface circuit responds to the ACK signal of the state machine in the host mode state, according to the I 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state and the third waiting state;

[0107] In the third waiting state, I 2 The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter the third waiting state. After the central processing unit CPU reads the data of the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state and the response receiving data state.

[0108] The embodiment of the present invention provides 2 C interface circuit only includes I 2 C register module, used to 2 The SCL generation circuit generates an SCL clock signal according to the configuration of the C register module, a state machine that performs state transitions and sends a control signal according to the SCL clock signal and the SDA data signal, and a control logic circuit for performing serial-to-parallel conversion on the data sent or received by the control bus and detecting the start / stop signal. The state machine includes a state machine in the host mode state and a state machine in the slave mode state; it is compatible with hosts with non-standard protocols, and the use of an improved state machine can not only reduce circuit area and power consumption, but also solve the problem of data transmission errors caused by the host of the software-simulated IO port not detecting that the SCL clock signal is pulled down by changing the pull-down position of the response and SCL clock signals when used as a slave mode; the embodiment of the present invention also provides a method suitable for I 2 The control method of the C interface circuit only needs to control two flag bits and one register for reading and writing during data transmission, which simplifies software control.

[0109] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A kind of I 2 C interface circuit, characterized in that, include: I 2 C register module; SCL generating circuit for generating an SCL signal according to the I 2 The configuration of the C register module generates the SCL clock signal; A state machine, which performs state transitions according to the SCL clock signal and the SDA data signal and sends a control signal, wherein the state of the state machine includes a master mode state and a slave mode state; A control logic circuit, configured to perform serial-to-parallel conversion on data transmitted on the control bus and detect a start / stop signal of the state machine; a first buffer and a second buffer; I 2 The first signal transmission end of the C register module is connected to the central processing unit CPU through the control bus. 2 The second signal transmission end of the C register module is connected to the first signal transmission end of the SCL generation circuit, the second signal transmission end of the SCL generation circuit is connected to the first signal transmission end of the state machine, the third signal transmission end of the SCL generation circuit is connected to the first input end of the first buffer, the second signal transmission end of the state machine is connected to the second input end of the first buffer, the output end of the first buffer is respectively connected to one end of the SCL clock signal line and the third signal transmission end of the state machine, the fourth signal transmission end of the state machine is connected to the first signal transmission end of the control logic circuit, the fifth signal transmission end of the state machine is connected to the first input end of the second buffer, the second signal transmission end of the control logic circuit is connected to the central processing unit CPU through the control bus, the third signal transmission end of the control logic circuit is connected to the sixth signal transmission end of the state machine, and the output end of the second buffer is respectively connected to one end of the SDA data line, the seventh signal transmission end of the state machine, and the fourth signal transmission end of the control logic circuit.

2. The method according to claim 1 2 C interface circuit, characterized in that, I 2 The C register module includes: a status register, wherein a signal transmission end of the status register is connected to the first signal transmission end of the control bus; an address register, wherein a signal transmission end of the address register is connected to a second signal transmission end of the control bus; a speed register, wherein a signal transmission end of the speed register is connected to a third signal transmission end of the control bus; A control register, wherein a first signal transmission terminal of the control register is connected to a fourth signal transmission terminal of the control bus, and a second signal transmission terminal of the control register is connected to a first signal transmission terminal of the SCL generation circuit.

3. The method according to claim 2 2 C interface circuit, characterized in that, The SCL generation circuit includes an SCL clock generation module and a first OUTPUT module; The first signal transmission end of the SCL clock generation module is used as the first signal transmission end of the SCL generation circuit and is connected to the second signal transmission end of the control register. The second signal transmission end of the SCL clock generation module is connected to the signal transmission end of the state machine. The third signal transmission end of the SCL clock generation module is connected to the input end of the first OUTPUT module. The output end of the first OUTPUT module is connected to the first input end of the first buffer, and the SCL0 signal is transmitted to the first buffer.

4. The method according to claim 3 2 C interface circuit, characterized in that, The control logic circuit includes: a synchronization logic module, an I2CDAT register, a matching detection module, a second OUTPUT module and an ACK module; The first signal transmission terminal of the synchronization logic module is connected to the fourth signal transmission terminal of the state machine, the second signal transmission terminal of the synchronization logic module is connected to the first signal transmission terminal of the I2CDAT register, the third signal transmission terminal of the synchronization logic module is connected to the input terminal of the second OUTPUT module, the output terminal of the second OUTPUT module is connected to the second input terminal of the second buffer, the output terminal of the second buffer is connected to the input terminal of the ACK module, the input terminal of the ACK module is connected to the seventh signal transmission terminal of the state machine, the output terminal of the ACK module is connected to the input terminal of the I2CDAT register, the second signal transmission terminal of the I2CDAT register is connected to the control bus, the output terminal of the I2CDAT register is connected to the input terminal of the match detection module, and the output terminal of the match detection module is connected to the sixth signal transmission terminal of the state machine.

5. A kind of I 2 A control method for a C interface circuit, applied to an I2C interface circuit as claimed in any one of claims 1 to 4 2 C interface circuit, characterized in that, include: The state machine in the host mode is designed to have 12 states, namely: idle state, host start state, send address state, answer address state, first waiting state, host send data state, answer send data state, second waiting state, host receive data state, third waiting state, answer receive data state and stop state; The state machine in the host mode state includes the following state jump process: After the central processing unit CPU is powered on or restarted, the I 2 The I2C interface circuit jumps from the idle state to the host start state according to the mode control bit of the I2C register module; I 2 The C register sends a start signal to the control bus, and jumps to the send address state after sending the start signal; I 2 The C register serially sends the slave device address and the read / write control word to the control bus, and jumps to the response address state after sending the slave device address and the read / write control word; I 2 The C interface circuit transfers the control right of the SDA data line from the state machine in the master mode state to the state machine in the slave mode state. If the state machine in the slave mode state does not receive the slave response signal, it jumps to the master start state; if the state machine in the slave mode state receives the slave response signal, it jumps to the first waiting state or the master receiving data state according to the written read / write control word; When in the first waiting state, the SCL generation circuit stops outputting the SCL clock signal, the central processing unit CPU writes data to the control logic circuit through the control bus, and automatically jumps to the host data sending state after the data is written; The control logic circuit sends data serially to the control bus, and automatically jumps to the data sending response state after sending the data; When responding to the data sending state, the I 2 The C interface circuit transfers the control right of the SDA data line from the state machine in the master mode state to the state machine in the slave mode state, and if the state machine in the slave mode state receives a slave response signal, jumps to the second waiting state; if the state machine in the slave mode state does not receive a slave response signal, jumps to the stop state; When in the second waiting state, the SCL generating circuit stops outputting the SCL clock signal, waits for the central processing unit CPU to write data to the control logic circuit through the control bus, and then jumps to the host sending data state. If the I 2 If the stop flag of the C register module is high, it jumps to the stop state; When the host is in the data receiving state, the control logic circuit automatically jumps to the third waiting state after serially receiving data from the control bus, and jumps to the data receiving response state after the central processing unit CPU finishes reading the data of the control logic circuit through the control bus; In the reply data receiving state, when the I 2 When the stop flag of the C register module is low, the control logic circuit controls the data line SDA to output a low level, and replies to the ACK signal of the state machine in the slave mode state and jumps to the host receiving data state; when the I 2 When the stop flag bit of the C register module is high, the control logic circuit controls the data line SDA to output a high level, and notifies the state machine in the slave mode state to jump to the stop state after the data transmission is completed; In the stopped state, the I 2 The C interface circuit sends a stop signal to the control bus, and automatically jumps to the idle state after sending the stop signal.

6. The method according to claim 5 2 The control method of the C interface circuit is characterized in that: Also includes: The state machine in the slave mode is designed to have 11 states, namely: idle state, slave start state, slave address receiving state, address response state, first waiting state, slave data sending state, data sending response state, second waiting state, slave data receiving state, data receiving response state and third waiting state; The state machine in slave mode includes the following state jump process: After the central processing unit CPU is powered on or restarted, the I 2 The I2C interface circuit jumps from the idle state to the slave start state according to the mode control bit of the I2C register module; I 2 The C register sends a start signal to the control bus, and after sending the start signal, jumps to the receiving slave address state; In the receiving slave address state, the control bus serially sends the slave device address and the read-write control word. When the received slave address is inconsistent with the self-configured address or the general broadcast address, it jumps to the slave start state. When the received slave address is consistent with the self-configured address or the general broadcast address and the read-write control word is "write", it jumps to the response address state. When the received slave address is consistent with the self-configured address or the general broadcast address and the read-write control word is "read", it jumps to the response address state according to the I 2 The software and hardware identification bits of the C register module determine the jump to the response address state or the first waiting state; In the response address state, the I 2 The C register responds to the address signal of the state machine in the host mode state, and the state machine in the host mode state reads and writes the control word and the I 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state, the slave sending data state, and the first waiting state; When in the first waiting state, the I 2 The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter a waiting state. After the central processing unit CPU writes data to the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and starts the slave mode according to the I2C interface circuit. 2 The software and hardware identification bits of the C register module automatically jump to the slave sending data state and response address state; The control logic circuit sends data serially to the control bus, and automatically jumps to the data sending response state after sending the data; When responding to the data sending state, the I 2 If the C interface circuit receives a response signal from the host, it jumps to the second waiting state. If it does not receive a response signal from the host, it jumps to the slave starting state. When in the second waiting state, the I 2 The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter the second waiting state. After the central processing unit CPU writes data to the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and automatically jumps to the slave data sending state. In the slave receiving data state, the control logic circuit receives the data sent by the control bus, and after receiving the data, the control logic circuit receives the data sent by the control bus according to the I 2 The software and hardware identification bits of the C register module automatically jump to the response data reception state and the third waiting state; In the state of receiving data, the I 2 The C interface circuit replies to the ACK signal of the state machine in the host mode state, according to I 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state and the third waiting state; In the third waiting state, the I 2 The C interface circuit pulls down the SCL clock signal, forcing the state machine in the slave mode to enter the third waiting state. After the central processing unit CPU finishes reading the data of the control logic circuit through the control bus, the state machine in the slave mode releases the SCL clock signal and starts the slave mode according to the I 2 The software and hardware identification bits of the C register module automatically jump to the slave receiving data state and the response receiving data state.

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