Core particle layout optimization method, electronic device, and storage medium

Abstract

This invention discloses a chip layout optimization method, comprising: determining a mapping layout confirmation order based on the communication data volume of the chips to be arranged; and confirming the mapping layout position of the chips to be arranged in the topology structure used for chip arrangement based on the mapping layout confirmation order and first data information, wherein the first data information includes: the communication power consumption between the chips to be arranged and the chips with confirmed mapping layout positions, and the predicted temperature of the current topology structure after the mapping layout position of the chips to be arranged is confirmed. This invention considers both the communication power consumption between chips and the chip temperature when confirming the mapping layout position of chips. Therefore, each chip mapping layout method obtained can significantly reduce the communication power consumption and temperature after arrangement compared with existing mapping layout methods, and effectively alleviate the situation of excessively high local temperatures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a chip layout optimization method, electronic device, and storage medium. Background Technology

[0002] 2.5D integration technology enables the design of heterogeneous package systems consisting of multiple different chips (CPU, GPU, memory, etc.), which can be manufactured using different technologies and processes. 2.5D integration places these chiplets side-by-side on a silicon interposer, enabling communication between these chiplets to achieve performance comparable to on-chip integration. Compared to 2D integration, 2.5D integration achieves higher performance and lower power consumption.

[0003] One of the design challenges of 2.5D integration is the design of interconnects between cores. Typically, 2.5D system layout planning focuses on minimizing system area, neglecting the communication relationships between cores and the resulting changes in physical parameters due to their inherent interrelationships and mutual influences. For example, the tight packing of high-power cores can lead to localized overheating, potentially causing core damage. To prevent overheating, existing technologies employ advanced but expensive cooling techniques, or shut down some cores or reduce their frequencies. However, these methods are costly and may come at the expense of performance. Other existing technologies utilize optimized layout design to reduce communication power consumption, thereby lowering temperature, but localized overheating remains a problem. Therefore, there is a pressing need to develop a method that achieves optimal core mapping and arrangement to address the issues of communication power consumption and overheating in 2.5D integration. Summary of the Invention

[0004] This invention provides a chip layout optimization method, an electronic device, and a storage medium to obtain a chip mapping arrangement scheme with low communication power consumption and low overall temperature, which to a certain extent solves the problems of excessively high communication power consumption and local temperature in 2.5D integrated circuits, and effectively reduces costs.

[0005] In a first aspect, embodiments of the present invention provide a method for optimizing the layout of core particles, comprising:

[0006] The mapping and arrangement confirmation order is determined based on the amount of communication data of the core particles to be arranged;

[0007] The mapping arrangement confirmation order and the first data information are used to confirm the mapping arrangement position of the core to be arranged in the topology structure used for core arrangement. The first data information includes: the communication power consumption between the core to be arranged and the core with the confirmed mapping arrangement position, and the predicted temperature of the current topology structure after the mapping arrangement position of the core to be arranged in the topology structure is confirmed.

[0008] In a second aspect, embodiments of the present invention provide an electronic device, including: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the steps of the chip layout optimization method of the first aspect described above.

[0009] Thirdly, embodiments of the present invention provide a storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the chip layout optimization method of the first aspect described above.

[0010] The beneficial effects of this invention are as follows: Unlike conventional chip mapping and arrangement methods that typically only consider communication power consumption, the method provided by this invention takes into account both communication power consumption and temperature between chips during the arrangement process. Although this significantly increases the complexity of the arrangement compared to conventional chip mapping and arrangement methods, the final chip mapping and arrangement method results in a substantial reduction in both communication power consumption and temperature, effectively mitigating the problem of excessively high local temperatures. Furthermore, by employing a method that designs the chip mapping and arrangement confirmation order based on the amount of communication data between chips, priority is given to optimizing the mapping and arrangement positions of chips with large amounts of communication data. This allows for reserving more space in the topology for the arrangement of chips with large amounts of communication data, thus prioritizing the mapping and arrangement positions of chips with large amounts of communication data to locations with lower communication power consumption and less impact from local temperature increases, thereby optimizing the overall mapping and arrangement method. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a flowchart of a core layout optimization method according to an embodiment of the present invention;

[0013] Figure 2 This is a communication task diagram of each chip in the chip layout optimization method according to an embodiment of the present invention.

[0014] Figure 3 This is a flowchart of the preprocessing method in the chip layout optimization method according to an embodiment of the present invention;

[0015] Figure 4This is a flowchart of step S12 of the core layout optimization method according to an embodiment of the present invention;

[0016] Figure 5 This is a schematic diagram illustrating the method for determining the mappable arrangement position of core 4 in a core layout optimization method according to an embodiment of the present invention.

[0017] Figure 6 This is a schematic diagram of the Manhattan distance between core 4 and core 8 in a core layout optimization method according to an embodiment of the present invention.

[0018] Figure 7 This is a schematic diagram of the mapped arrangement position of the core 8 in the core layout optimization method according to an embodiment of the present invention.

[0019] Figure 8 This is a schematic diagram of the symmetrical mapping arrangement of core particles 8 in a core particle layout optimization method according to an embodiment of the present invention.

[0020] Figure 9 The temperature distribution simulation diagram is for the mapping arrangement obtained without using the core layout optimization method of the present invention.

[0021] Figure 10 This is a temperature distribution simulation diagram of the mapping arrangement obtained using the core layout optimization method of the present invention;

[0022] Figure 11 This is a schematic diagram of the structure of an embodiment of the electronic device of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0025] This invention can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, elements, data structures, etc., that perform a specific task or implement a specific abstract data type. This invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0026] In this invention, terms such as "module," "device," and "system" refer to relevant entities applied to a computer, such as hardware, combinations of hardware and software, software, or software in execution. More specifically, for example, an element can be, but is not limited to, a process running on a processor, a processor, an object, an executable element, an execution thread, a program, and / or a computer. Furthermore, an application program or script running on a server, and the server itself, can also be an element. One or more elements may be in an execution process and / or thread, and elements may be localized on a single computer and / or distributed across two or more computers, and may be run on various computer-readable media. Elements can also communicate via local and / or remote processes based on signals having one or more data packets, for example, signals from data interacting with another element in a local system, a distributed system, and / or interacting with other systems via signals over a network of the Internet.

[0027] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising" or "including" include not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0028] The embodiments of the present invention will now be described in further detail with reference to the accompanying drawings.

[0029] Figure 1 The flowchart of a core layout optimization method according to an embodiment of the present invention is illustrated schematically, with reference to... Figure 1 As shown, the method includes the following steps:

[0030] Step S11: Determine the mapping and arrangement confirmation order based on the amount of communication data of the core particles to be arranged;

[0031] Step S12: Confirm the mapped arrangement position of the core to be arranged in the topology for core arrangement according to the mapping arrangement confirmation order and the first data information, wherein the first data information includes: the communication power consumption between the core to be arranged and the core with the confirmed mapped arrangement position, and the predicted temperature of the current topology after the mapped arrangement position of the core to be arranged in the topology is confirmed.

[0032] Step S11: Determine the mapping layout confirmation order. The mapping layout confirmation order is the order used when confirming the mapping layout positions of the core particles to be arranged. In one example, in step S11, the mapping layout confirmation order is determined based on the amount of communication data between the core particles. For example, it can be set to determine the order of confirming the mapping layout positions of the core particles to be arranged based on the order of the amount of communication data between the core particles from largest to smallest. Since a large amount of communication data will result in greater communication power consumption and greater heat generation of the corresponding core particles, by prioritizing the confirmation of the mapping layout positions of core particles with large amounts of communication data in the topology, more positions can be reserved in the topology for the selection of the layout positions of core particles with large amounts of communication data. This allows the mapping layout positions of core particles with large amounts of communication data to be prioritized to positions with lower communication power consumption and less impact from local temperature rise, thereby optimizing the overall mapping layout method.

[0033] For example, refer to Figure 2 As shown, Figure 2 This is a communication task diagram for all cores. Figure 2 The names of the core particles are displayed within the circles, and the numbers on the directed line segments represent the amount of communication data between core particles, in Mbit / s. Based on the sum of the communication data of each core particle and other core particles, the data is organized into Table 1 below. Table 1 is a priority list of core particles requiring mapping and arrangement. It sorts the mapping and arrangement confirmation order of each core particle according to its communication data volume; particles with the same communication data volume have the same priority. For example, the mapping and arrangement confirmation order of core particle 4 (index 4) and core particle 1 (index 1) can be reversed without affecting the final mapping and arrangement.

[0034] Table 1

[0035]

[0036] Step S12 involves confirming the mapped arrangement position of the core to be arranged in the topology. In step S12, the first data information is the specific data information used to confirm the mapped arrangement position of the core to be arranged in the topology. In one example, the first data information may include the communication power consumption between the core to be arranged and the core with a confirmed mapped arrangement position, and the predicted temperature of the current topology after confirming the mapped arrangement position of the core to be arranged. That is, when confirming the mapped arrangement position of the core to be arranged in the topology, it is determined based on the communication power consumption between the core to be arranged at the current mapped arrangement position (hereinafter referred to as the current core) and the core with a confirmed mapped arrangement position, and the predicted temperature of the current topology after confirming the mapped arrangement position of the current core. It can be understood that the current core is the core to be arranged whose mapped arrangement position in the topology is currently being confirmed, and the core with a confirmed mapped arrangement position is the core whose mapped arrangement position in the topology has been confirmed before the current core. Since there may be multiple mappable locations for the current core in the topology, the optimal mapping location for the current core can be determined by analyzing the communication power consumption and predicted temperature between the current core and cores with confirmed mapping locations. This invention optimizes the overall mapping arrangement by optimizing the mapping location of the current core, effectively mitigating the problems of excessively high communication power consumption and localized temperatures in 2.5D integrated circuits.

[0037] As a preferred embodiment, preprocessing can be performed before step S12. This preprocessing mainly involves standardizing the size attributes of the core particles. Figure 3 The preprocessing method flow in the core layout optimization method according to an embodiment of the present invention is illustrated schematically. (Refer to...) Figure 3 As shown, this method can be specifically implemented by including the following steps:

[0038] Step S21: Determine the theoretical size of the core particles based on their actual size and spacing.

[0039] Step S22: Determine the size of the unit cell based on the theoretical size of all core particles.

[0040] First, the theoretical dimensions of the core particles need to be determined. In step S21, the theoretical dimensions of each core particle to be arranged need to be determined. The actual dimensions of the core particles can be determined based on the inherent attributes of each core particle. Specifically, the actual dimensions of the core particles can be obtained through input or directly by communicating with other devices or systems. The actual dimensions of the core particles are d1*d2, where d1 is the length and d2 is the width. The length and width depend on the d1 and d2 values ​​input when obtaining the actual dimensions of the core particles. For elongated core particles, the length and width can be swapped by rotation. The arrangement spacing is the minimum interval required between adjacent core particles. The designed arrangement spacing between core particles needs to be no less than the preset arrangement spacing, which can be preset according to the actual situation. After determining the actual dimensions and arrangement spacing of the core particles, the theoretical dimensions of the core particles can be determined based on the actual dimensions and arrangement spacing. For example, the theoretical dimensions of the core particles can be designed to be calculated by adding the arrangement spacing to the actual dimensions of the core particles.

[0041] After determining the theoretical dimensions of all core particles, the dimensions of the unit cells need to be further determined. The topology is composed of unit cells, and the size of the unit cells is determined based on the theoretical dimensions of all core particles. This design ensures that when mapping and arranging the core particles according to the final determined mapping arrangement, there will not be excessive waste in the topology. Step S22 determines the size of the unit cells. The size of a unit cell can be represented as N1*N2, where N1 is the length and N2 is the width. N1 can be set based on the length of the theoretical dimensions of all core particles, and N2 can be set based on the width of the theoretical dimensions of all core particles, so that the topology corresponds to the core particles. In one example, the size of the unit cell can be set such that the length of each core particle's theoretical dimension is an integer multiple of N1, and the width of each core particle's theoretical dimension is an integer multiple of N2, so that the topology also has a corresponding integer multiple relationship with the theoretical dimensions of each core particle.

[0042] In a preferred embodiment, in step S22, when determining the size of the unit cell, the theoretical size of each core particle can be further adjusted so that the determined values ​​of N1 and N2 are as large as possible, thereby minimizing the number of unit cells that make up the topology, reducing the amount of computation and improving efficiency.

[0043] As a preferred implementation, since the theoretical dimensions of each core particle include both length and width, the theoretical dimensions of each core particle can be further adjusted in step S22 to ensure that the determined values ​​of N1 and N2 are equal, making the unit cell a square. In this implementation, the length and width of the theoretical dimensions of each core particle are integer multiples of the side length of the unit cell. This allows for the simultaneous consideration of different placement methods (horizontal and vertical) of the core particles when determining their mapping arrangement positions, thereby enabling the determination of the optimal mapping arrangement position of the core particles in the topology among the mapping arrangement positions corresponding to different placement methods.

[0044] For example, taking all the chips in Table 1 as an example, Table 2 shows the size and power consumption data of all the chips. The actual size and power of the chips in Table 2 can be determined according to the attributes of each chip, and the arrangement interval is set to not less than 0.5mm.

[0045] First, execute step S21 to determine the theoretical size of the core particle based on its actual size and spacing. For example, for core particle 8 with core particle number 8, its actual size is 4mm*1mm, and the theoretical size determined after taking the spacing into account is 4.5mm*1.5mm; for core particle 4 with core particle number 4, its actual size is 4mm*4mm, and the theoretical size determined after taking the spacing into account is 4.5mm*4.5mm.

[0046] Then, step S22 is executed to determine the size of the unit cell based on the theoretical size of all core particles. At this point, the theoretical size of the core particles can be finely adjusted so that N1 and N2 of the determined unit cells are equal, making the unit cell a square. For example, after adjustment, in this embodiment, the side length of the unit cell is specifically set to 1.5mm, that is, the unit cell is a 1.5mm*1.5mm unit cell, and the length and width of the adjusted theoretical size of each core particle are both integer multiples of 1.5mm. In other embodiments, the divided unit cells can also be 0.5mm*0.5mm or 0.1mm*0.1mm, etc. To reduce computational processing and improve efficiency, the size of the unit cell is determined to be as large as possible to minimize the number of unit cells constituting the topology. In this embodiment, the topology can be a square structure with a size of 12mm*10.5mm, composed of 8*7 1.5mm*1.5mm unit cells.

[0047] Table 2

[0048]

[0049] Figure 4 The flowchart of step S13 of the core layout optimization method according to an embodiment of the present invention is illustrated schematically. (Refer to...) Figure 4Specifically, this method can be implemented by including the following steps:

[0050] Step S31: Determine all mappable arrangement positions of the core particles to be arranged in the topology;

[0051] Step S32: Determine the first heuristic information and the second heuristic information corresponding to each mappable arrangement position;

[0052] Step S33: Determine the third heuristic information corresponding to each mappable arrangement position based on the first and second heuristic information corresponding to each mappable arrangement position;

[0053] Step S34: Confirm the mapping arrangement position of the core particle to be arranged in the topology based on the third heuristic information corresponding to each mappable arrangement position.

[0054] First, determine all mappable positions for the current core particle. In step S31, mappable positions are the unconfirmed mappable positions in the topology that can be used to map the current core particle. Specifically, this can be represented using unit cells in the topology. When determining all mappable positions for the current core particle, the current core particle can be divided into unit cells based on its theoretical size, so that the theoretical size of the current core particle can be represented by several unit cells. At this time, the unit cell at the upper left corner of the current placement of the current core particle can be selected as the marker cell. When the marker cell of the current core particle is set in a unit cell in the topology, that unit cell in the topology can be used to represent the mappable position of the current core particle in the topology. This setting can determine whether the current core particle can be mapped and arranged in the topology using that unit cell as the marker cell by performing a preset condition judgment on each unit cell in the topology, thereby determining all mappable positions for the current core particle in the topology.

[0055] Taking core 4, with a core number of 4, as an example, as having the second priority in confirming the mapping and arrangement position. (Refer to...) Figure 5 When confirming all mappable positions of core 4 in the topology, it is necessary to determine whether each unit cell meets the preset conditions in order to determine all mappable positions of core 4 in the topology.

[0056] The preset condition is used to determine whether the mapped arrangement positions of the core particles corresponding to the current unit cell are all within the topology and whether no mapped arrangement position of the core particles has been confirmed. In one example, the preset condition can be to determine whether the range enclosed by the length L from the top left corner to the right side of the unit cell and the length W from the top left corner to the bottom side of the unit cell are both within the topology and whether no mapped arrangement position of the core particles has been confirmed. Here, L is the length in the theoretical size of the current core particle, and W is the width in the theoretical size of the current core particle. If the range enclosed by the length L from the top left corner to the right side of a unit cell and the length W from the top left corner to the bottom side of the unit cell are both within the topology and no mapped arrangement position of the core particles has been confirmed, then it means that the mapped arrangement position of the current core particle corresponding to that unit cell is a mappable arrangement position of the current core particle. By setting it up in this way, after the unit cell is judged to meet the preset conditions, it can be determined whether the core particle will exceed the topology or conflict with the unit cells in the topology that have been confirmed to have a core particle when the core particle is mapped to the corresponding mapping position of the unit cell. Thus, it can be determined whether the mapping position of the current core particle corresponding to the unit cell is a mappable position of the current core particle.

[0057] In this embodiment, since the unit grid of the topology is set as a square, and the core particles with different lengths and widths will have different mappable arrangement positions when placed horizontally and vertically, when determining all mappable positions of the core particles in the topology, all mappable arrangement positions when the core particles are placed horizontally and all mappable arrangement positions when the core particles are placed vertically can be determined separately, so that the optimal mapping arrangement position can be determined from all mappable arrangement positions corresponding to different placement methods of the core particles.

[0058] After determining all mappable positions of the current chip in the topology, it is necessary to determine the first and second heuristic information corresponding to each mappable position according to step S32. The first heuristic information is related to communication power consumption, and the second heuristic information is related to predicted temperature. It can be understood that each mappable position of the current chip corresponds to one first heuristic information and one second heuristic information.

[0059] The first heuristic information is determined based on the Manhattan distance between the current core particle's mapped arrangement at the current mappable arrangement position and the corresponding mapped arrangement positions of core particles at each confirmed mapped arrangement position, as well as the amount of communication data between the current core particle and core particles at each confirmed mapped arrangement position. It can be obtained by the following formula:

[0060]

[0061] Where, η 1 iThis is the first heuristic information for mapping core i to its current mappable position, where i represents the core i whose mapping position is yet to be confirmed, and j represents each core j whose mapping position has been confirmed. i,j Let C be the Manhattan distance between the mapped arrangement of core i at the mappable arrangement position and the corresponding mapped arrangement positions of each core j (or, in other words, the Manhattan distance between core i and each core j when core i is mapped at the mappable arrangement position and each core j is mapped at its corresponding mapped arrangement position). i,j E represents the amount of communication data between core i and each core j. bit In this embodiment, the energy consumed to transmit 1Mb of data per unit distance between cores is taken as E. bit =186nJ / Mb·mm.

[0062] In one example, C i,j It can be determined according to Table 1; d i,j The distance between the center of core i and the center of the corresponding mapped arrangement position of each core j can be determined using the unit grid as the reference unit.

[0063] Reference Figure 6 As shown, depending on the arrangement of core i or core j in the topology (horizontal or vertical), the Manhattan distance between core i and the corresponding mapping arrangement position of each core j will also change. Figure 6 In Figure a, the core 8 is placed horizontally, and the Manhattan distance between the corresponding mapped positions of core 4 and core 8 can be determined as 4 units; in Figure b, the core 8 is placed vertically, and the Manhattan distance between the corresponding mapped positions of core 4 and core 8 can be determined as 2 units.

[0064] The second heuristic information is determined based on the Manhattan distance between the current core particle mapping arrangement at the current mappable arrangement position and the corresponding mapping arrangement positions of the core particles at each confirmed mapping arrangement position, as well as the power of the core particles at each confirmed mapping arrangement position, and can be obtained by the following formula:

[0065]

[0066] Where, η 2 i This is the second heuristic information for mapping core i to its current mappable position, where i represents the core i whose mapping position is yet to be confirmed, and j represents each core j whose mapping position has been confirmed. i,jP is the Manhattan distance between core i at the current mappable arrangement position and the corresponding mapped arrangement positions of each core j (or it can be understood as the Manhattan distance between core i and each core j when core i is mapped to the mappable arrangement position and each core j is mapped to its corresponding mapped arrangement position). Its calculation method can be found in the relevant description in the first heuristic information. j The power of each core particle j can be determined based on the relevant information in Table 2.

[0067] After determining the first and second heuristic information corresponding to each mappable arrangement position in step S32, the third heuristic information corresponding to each mappable arrangement position is determined according to step S33. Specifically, the third heuristic information is determined based on the maximum value and minimum value of each of the first heuristic information, the first heuristic information corresponding to the current mappable arrangement position, the maximum value and minimum value of each of the second heuristic information, the second heuristic information corresponding to the current mappable arrangement position, and preset weight values ​​for the first and second heuristic information. In one example, the third heuristic information can be obtained by the following formula:

[0068]

[0069] Where, η i η is the third heuristic information for the mapping arrangement of core i at the current mappable arrangement position. 1 i η is the first heuristic information for the mapping arrangement of core i at the current mappable arrangement position. 2 i This is the second heuristic information for core i when it is mapped and arranged in the currently mappable arrangement position, where i represents core i at the current unconfirmed mapping arrangement position. η 1 imax η is the maximum value among the first heuristic information determined in step S32. 1 imin η is the minimum value among the first heuristic information determined in step S32. 2 imax η is the maximum value among the second heuristic information determined in step S32. 2 imaxThe minimum value among the second heuristic information determined in step S32 is α. α is a preset weight value for the first and second heuristic information, where 0 ≤ α ≤ 1. Adjusting α adjusts the trade-off between communication power consumption and predicted temperature. If the desired chip mapping arrangement prioritizes minimizing communication power consumption, α should have a larger value; conversely, if the desired chip mapping arrangement prioritizes minimizing temperature, α should have a smaller value. As an example, in this embodiment, α = 0.5 is used for calculation. In this case, the weight between communication power consumption and predicted temperature in the calculated third heuristic information is 1:1.

[0070] After determining the third heuristic information corresponding to each mappable arrangement position, the mapping arrangement position of the current chip in the topology can be confirmed according to step S24. In one example, the mappable arrangement position corresponding to the minimum value of the third heuristic information can be confirmed as the mapping arrangement position of the current chip in the topology. The mappable arrangement position corresponding to the minimum value of the third heuristic information indicates that the communication power consumption and temperature generated when the current chip is mapped and arranged at that mappable arrangement position are optimal. Therefore, by confirming the mappable arrangement position corresponding to the minimum value of the third heuristic information as the mapping arrangement position of the chip in the topology when confirming the mapping arrangement position of each chip, the optimal mapping arrangement method can be obtained, so as to effectively solve the problems of communication power consumption and excessive local temperature in 2.5D integration.

[0071] In some implementations, during step S34, there may be two or more mappable arrangement positions corresponding to the minimum value of the third heuristic information. In this case, the minimum value of the third heuristic information of the next core particle can be determined when the current core particle is mapped to each mappable arrangement position corresponding to the minimum value of the third heuristic information, and the numerical value of the third heuristic information of the next core particle can be observed. If the minimum value of the third heuristic information of the next core particle is smaller, it indicates that the final mapping arrangement is more effective when the current core particle is mapped to the mappable arrangement position corresponding to the minimum value of the third heuristic information. Therefore, the mappable arrangement position of the current core particle in this case can be identified as the mapping arrangement position of the current core particle in the topology to reduce the amount of data computation.

[0072] For the core particle whose mapping and arrangement position is confirmed first, since no mapping and arrangement position of any core particle has been confirmed in the topology at this time, the mappable arrangement position of this core particle can be arbitrarily determined in the topology. For example, refer to... Figure 7 and Figure 8As shown, unit cells with unconfirmed mapping positions of core particles in the topology can be marked with -1, while unit cells with confirmed mapping positions of core particles can be marked with the corresponding core particle number, thereby distinguishing unit cells with unconfirmed mapping positions of core particles in the topology.

[0073] Reference Figure 7 Taking chip 8, with the largest communication data volume and serial number 8, as an example, it has the highest priority in determining its mapping arrangement position due to its large communication data volume. It is the first chip to have its mapping arrangement position determined, and its mapping arrangement position can be determined at any location in the topology. The determined mapping arrangement position of chip 8 in the topology will affect the mapping arrangement positions of other chips that are subsequently determined. Therefore, each determined mapping arrangement position of chip 8 corresponds to at least one mapping arrangement method for all chips in the topology, and the communication power consumption and local temperature conditions will differ for each different mapping arrangement method.

[0074] Reference Figure 8 Figures a and b correspond to two mappable arrangement positions of core 8. Since the two mappable arrangement positions of core 8 corresponding to figures a and b are symmetrically set, the overall layout extended from these two mappable arrangement positions is also symmetrical, and only one mappable arrangement position needs to be considered.

[0075] After determining each mapping arrangement, the Hotspot software can be used to simulate and test each arrangement to obtain temperature distribution maps for different layouts, allowing for the determination of the optimal mapping arrangement based on actual conditions. The Hotspot tool performs temperature analysis by calculating the thermal resistance matrix between the core particles, enabling predictive analysis of system temperature, and its results are obtained relatively quickly. Inputting each mapping arrangement obtained according to this invention into Hotspot yields the corresponding temperature distribution, which can be compared with the initial layout to analyze the optimization degree of the new mapping arrangement compared to the initial layout. For example, the Hotspot parameters are set as follows: ambient temperature is set to 318.5K, the side length of the heat spread is set to 5mm, and the side length of the heatsink is set to 20mm. To achieve better heat dissipation, a strong convection model is used, with lateral airflow. The heatsink uses a finned heatsink with a fin height of 30mm and a fin width of 1mm. The cooling fan radius is set to 10cm, and the speed is set to 5000 rpm. Specific temperature distribution details are as follows. Figure 9 and Figure 10 As shown.

[0076] Figure 9The temperature distribution simulation diagram for the mapping arrangement obtained without using the method of this invention is shown. Its communication power consumption is 1026.72 μJ and the peak temperature reaches 381.41 K. Figure 10 The temperature distribution simulation diagram of the mapped arrangement obtained by the chip layout optimization method of the present invention shows that the peak temperature is reduced to 373.58K, and the communication power consumption is also reduced to 794.59μJ. Chips with higher communication throughput (0) are placed in the middle position, while chips with lower communication throughput are arranged around them. In addition, chips with higher power consumption per unit area are also dispersed. Taking into account both temperature and communication power consumption, this layout significantly improves both communication power consumption and temperature.

[0077] When confirming the mapping layout positions, this invention designs the confirmation order of the core particles based on the amount of communication data between them, prioritizing the optimization of the mapping layout positions of core particles with large communication data volumes. Furthermore, the invention considers both communication power consumption and predicted temperature during the confirmation process. This results in each mapping layout obtained by this invention significantly reducing communication power consumption and temperature compared to conventional mapping layouts, effectively mitigating localized overheating. After obtaining all mapping layouts, each layout can be imported into Hotspot software to simulate its temperature distribution during operation and compare the results, determining the optimal mapping layout based on actual conditions.

[0078] In some embodiments, the present invention provides a non-volatile computer-readable storage medium storing one or more programs including execution instructions, which can be read and executed by an electronic device (including but not limited to a computer, server, or network device, etc.) to perform the chip layout optimization method of any of the above embodiments of the present invention.

[0079] In some embodiments, the present invention also provides a computer program product, the computer program product including a computer program stored on a non-volatile computer-readable storage medium, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the chip layout optimization method of any of the above embodiments.

[0080] In some embodiments, the present invention also provides an electronic device comprising: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the chip layout optimization method of any of the above embodiments.

[0081] In some embodiments, the present invention also provides a storage medium storing a computer program, characterized in that the program, when executed by a processor, implements the chip layout optimization method of any of the above embodiments.

[0082] Figure 11 This is a schematic diagram of the hardware structure of an electronic device for performing a chip layout optimization method according to another embodiment of this application, as shown below. Figure 11 As shown, the device includes:

[0083] One or more processors 110 and memory 120, Figure 11 Take a processor 110 as an example.

[0084] The apparatus for performing the core layout optimization method may further include an input device 130 and an output device 140.

[0085] The processor 110, memory 120, input device 130, and output device 140 can be connected via a bus or other means. Figure 10 Taking the example of a connection between China and Israel via a bus.

[0086] The memory 120, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the chip layout optimization method in the embodiments of this application. The processor 110 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 120, thereby implementing the chip layout optimization method of the above-described method embodiments.

[0087] Memory 120 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created using a chip layout optimization method, etc. Furthermore, memory 120 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 120 may optionally include memory remotely located relative to processor 110, and these remote memories may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0088] Input device 130 can receive input digital or character information and generate signals related to user settings and function control of the image processing device. Output device 140 may include display devices such as a display screen.

[0089] The one or more modules are stored in the memory 120, and when executed by the one or more processors 110, the chip layout optimization method in any of the above method embodiments is executed.

[0090] The above-described product can perform the methods provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects for performing the methods. Technical details not described in detail in this embodiment can be found in the methods provided in the embodiments of this application.

[0091] The electronic devices in this application embodiments exist in various forms, including but not limited to:

[0092] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and primarily aim to provide voice and data communication. These terminals include: smartphones (e.g., iPhones), multimedia phones, feature phones, and low-end phones, etc.

[0093] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access features. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0094] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes audio and video players (such as iPods), handheld game consoles, e-book readers, as well as smart toys and portable car navigation devices.

[0095] (4) Server: A device that provides computing services. The components of a server include a processor, hard disk, memory, system bus, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0096] (5) Other electronic devices with data interaction functions.

[0097] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0098] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for optimizing core particle layout, characterized in that, include: The mapping and arrangement confirmation order is determined based on the amount of communication data of the core particles to be arranged; The mapping arrangement confirmation order and the first data information are used to confirm the mapping arrangement position of the core to be arranged in the topology structure used for core arrangement. The first data information includes: the communication power consumption between the core to be arranged and the core with the confirmed mapping arrangement position, and the predicted temperature of the current topology structure after the mapping arrangement position of the core to be arranged in the topology structure is confirmed. The step of confirming the mapped arrangement position of the core particle to be arranged in the topology for core particle arrangement according to the mapped arrangement confirmation order and the first data information includes: Determine all mappable positions of the core particles to be arranged in the topology; Determine the first and second heuristic information corresponding to each mappable arrangement position; The third heuristic information corresponding to each mappable arrangement position is determined based on the first and second heuristic information corresponding to each mappable arrangement position. The mapping arrangement position of the core particle to be arranged in the topology is confirmed based on the third heuristic information corresponding to each mappable arrangement position. The first heuristic information is determined based on the Manhattan distance between the core to be arranged and the corresponding mapping positions of the cores at the current maptable positions when the core to be arranged is mapped at the current maptable position, and the amount of communication data between the core to be arranged and the cores at the confirmed mapping positions. The second heuristic information is determined based on the Manhattan distance between the core to be arranged and the corresponding mapped arrangement position of each core at the confirmed mapped arrangement position when the core is mapped at the current mappable arrangement position, and the power of the core at each confirmed mapped arrangement position.

2. The method according to claim 1, characterized in that, Also includes: The theoretical size of the core particles to be arranged is determined based on the actual size and spacing of the core particles to be arranged. The size of the unit cell is determined based on the theoretical size of all core particles, where the topology is composed of unit cells.

3. The method according to claim 2, characterized in that, When determining the size of a unit cell based on the theoretical size of all core particles, the theoretical size of the core particles to be arranged is adjusted so that the length of the theoretical size of the core particles to be arranged is an integer multiple of the length of the unit cell, and the width is an integer multiple of the width of the unit cell.

4. The method according to claim 1, characterized in that, The third heuristic information is determined based on the maximum value of each first heuristic information, the minimum value of each first heuristic information, the first heuristic information corresponding to the current mappable arrangement position, the maximum value of each second heuristic information, the minimum value of each second heuristic information, the second heuristic information corresponding to the current mappable arrangement position, and the preset weight values ​​of the first and second heuristic information.

5. The method according to claim 1, characterized in that, When determining the mapped arrangement position of the core particle to be arranged in the topology based on the third heuristic information, the mappable arrangement position corresponding to the minimum value of the third heuristic information is determined as the mapped arrangement position of the core particle to be arranged in the topology. This applies when there are at least two mappable arrangement positions corresponding to the minimum value of the third heuristic information. The minimum value of the third heuristic information of the next core particle is determined when the core particle to be arranged is mapped to the maptable arrangement position corresponding to the minimum value of each third heuristic information. The mappable arrangement position of the core to be arranged corresponding to the minimum value of the third heuristic information of the smaller next core is determined as the mapped arrangement position of the core to be arranged in the topology.

6. An electronic device, characterized in that, include: At least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the steps of the method according to any one of claims 1-5.

7. A storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method described in any one of claims 1-5.

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