An optoelectronic chip layout wiring method, device, equipment and storage medium

Abstract

The application discloses an optoelectronic chip layout wiring method, device and equipment and a storage medium, relates to the technical field of optoelectronic chip layout automatic design wiring, and comprises the following steps: mapping the optoelectronic chip layout into a grid, mapping the PCell port of a parameterized unit into a point coordinate, and mapping the waveguide needing to be wired into a line segment; taking a cross-shaped grid in the grid as a basic unit, defining the center coordinate of the cross-shaped grid and the line segment passing through the center coordinate of the cross-shaped grid as variables; setting the path between the PCell ports, the restriction conditions of points and line segments on the path; using the variables to represent the length of the path, and based on the restriction conditions, calculating the corresponding variable values according to the equal-length path to be implemented, so as to determine the path planning, and finally mapping the path planning into the waveguide wiring. The application can ensure that the waveguide lengths are equal during wiring, the number of curved waveguides is equal, and the waveguide occupation area is minimum and the total length of the waveguide is shortest.

Description

Technical Field

[0001] This invention relates to the field of automated design and wiring technology for optoelectronic chips, specifically to a method, apparatus, device, and storage medium for layout wiring of optoelectronic chips. Background Technology

[0002] Existing automated design tools for optoelectronic chip layouts automatically generate waveguide routes according to the Manhattan algorithm for port links between parameterized cells (PCells) or between system links, thus planning the shortest horizontal and vertical paths.

[0003] However, the waveguide routing design for coherent optical chip layouts needs to consider the issue of multiple waveguides having equal lengths—equal waveguide lengths and an equal number of bent waveguides (usually assuming consistent bent waveguide radii). Simultaneously, it is desirable to have smaller waveguide lengths to reduce optical power loss (although the loss per unit length is very small in silicon photonics) and phase delay, as well as to minimize the area occupied by the entire module to reduce manufacturing costs and increase integration.

[0004] The tools mentioned above, while addressing the issue of equal-length waveguides, do not achieve automated equal-length routing. They still rely on manually calculating the length difference and the number of bent waveguides, and then adding control points along the waveguide path to change its orientation, thereby altering the waveguide length and the number of bent waveguides. This semi-manual, semi-automatic approach to equal-length waveguide routing is labor-intensive, time-consuming, and error-prone. Furthermore, the final equal-length waveguide may not represent the optimal solution in terms of total waveguide length and overall module area. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the first aspect of this invention provides a method for routing optoelectronic chip layouts that ensures equal waveguide lengths and an equal number of bent waveguides during routing, while simultaneously minimizing the waveguide area occupied and the total waveguide length.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A method for layout wiring of an optoelectronic chip, the method comprising the following steps:

[0008] The optoelectronic chip layout is mapped into a grid, and the parameterized unit PCell port is mapped into point coordinates. The waveguide that needs to be wired is mapped into line segments.

[0009] Using the grid as the basic unit, the center coordinates of the grid and the combination of line segments passing through the center coordinates of the grid are defined as variables;

[0010] Set constraints on the paths between PCell ports, the points and line segments on the paths, and the constraints include the path non-intersection condition, the path input point, the output point, and the existence condition of the line segments.

[0011] The path length is represented by the variable, and based on the constraints, the corresponding variable values ​​are calculated according to the desired equal-length path to determine the path planning. Finally, the path planning is mapped to waveguide routing.

[0012] In some embodiments, the step of using the grid's grid lines as basic units, defining the grid center coordinates and the combination of line segments passing through the grid center coordinates as variables, includes:

[0013] Set the center coordinates of the grid to (i, j);

[0014] And set the value to either 0 or 1:

[0015] The variable of the horizontal segment in the i-th row and j-th column on path-k: If on path-k, then otherwise

[0016] The variable of the vertical segment in the i-th row and j-th column on path-k: If on path-k, then otherwise

[0017] The variable indicating whether the point in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0018] The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then otherwise

[0019] The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then otherwise

[0020] The variable determining whether the left segment of the point in row i and column j is on path k: If both the top and left segments are on path-k, then otherwise

[0021] Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper and right segments are on path-k, then otherwise

[0022] Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then otherwise

[0023] Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then otherwise

[0024] In some embodiments, the constraints on the paths between PCell ports, the points on the paths, and the line segments are defined. These constraints include the non-intersection of paths, the existence of path input points, output points, and line segments, and include:

[0025] Restrict input point I on path-k k (i,j) satisfies Output point O k (i,j) satisfies

[0026] Through the formula: The paths must not intersect;

[0027] Through the formula: Each segment can only be on one path at most;

[0028] Through the formula: A point restricted to path-k has exactly two of its four segments (up, down, left, and right) on path-k;

[0029] Through the formula: The two endpoints of a segment restricted to path-k are also on path-k;

[0030] Through the formula:

[0031]

[0032]

[0033] Restrict the points in the i-th row and j-th column

[0034] In some embodiments, according to the formula:

[0035]

[0036] Calculate the length L of path-k k Where a is the unit length of the grid, and R is the corner radius;

[0037] When path-k1 and path-k2 need to be equal, we have L k1 =L k2 .

[0038] In some embodiments, it also includes:

[0039] Using the formula min∑ k L k Optimize the path to minimize the total length of all paths.

[0040] The second aspect of the present invention provides a layout wiring device for optoelectronic chips, which can ensure that the waveguide length is equal, the number of bent waveguides is equal, and at the same time ensures that the waveguide occupancy area is minimized and the total waveguide length is minimized during wiring.

[0041] A layout wiring device for an optoelectronic chip, comprising:

[0042] The mapping module is used to map the optoelectronic chip layout into a grid, map the parameterized unit PCell port into point coordinates, and map the waveguide that needs to be wired into line segments.

[0043] The configuration module is used to define the center coordinates of the grid and the combination of line segments passing through the center coordinates of the grid as variables, using the grid as the basic unit.

[0044] The calculation module is used to set the constraints on the paths between PCell ports, the points on the paths, and the line segments. The constraints include the paths not intersecting, the path input points, the output points, and the existence of line segments. The calculation module is also used to use the variables to represent the length of the paths, and based on the constraints, calculate the corresponding variable values ​​according to the desired equal-length paths to determine the path planning, and finally map the path planning to waveguide traces.

[0045] In some embodiments, the configuration module uses a grid of squares as the basic unit, defining the center coordinates of the squares and the combination of line segments passing through the center coordinates of the squares as variables, including:

[0046] Set the center coordinates of the grid to (i, j);

[0047] And set the value to either 0 or 1:

[0048] The variable of the horizontal segment in the i-th row and j-th column on path-k: If on path-k, then otherwise

[0049] The variable of the vertical segment in the i-th row and j-th column on path-k: If on path-k, then otherwise

[0050] The variable indicating whether the point in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0051] The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then otherwise

[0052] The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then otherwise

[0053] The variable determining whether the left segment of the point in row i and column j is on path k: If both the top and left segments are on path-k, then otherwise

[0054] Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper and right segments are on path-k, then otherwise

[0055] Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then otherwise

[0056] Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then otherwise

[0057] In some embodiments, the computing module sets constraints on paths between PCell ports, points on those paths, and line segments. These constraints include the non-intersection of paths, the existence of path input points, output points, and line segments, including:

[0058] Restrict input point I on path-k k (i,j) satisfies Output point O k (i,j) satisfies

[0059] Through the formula: The paths must not intersect;

[0060] Through the formula: Each segment can only be on one path at most;

[0061] Through the formula: A point restricted to path-k has exactly two of its four segments (up, down, left, and right) on path-k;

[0062] Through the formula: The two endpoints of a segment restricted to path-k are also on path-k;

[0063] Through the formula:

[0064]

[0065] Restrict the points in the i-th row and j-th column

[0066] The third aspect of the present invention provides a device that can ensure that the waveguide length is equal and the number of bent waveguides is equal during wiring, while simultaneously ensuring that the waveguide occupancy area is minimized and the total waveguide length is minimized.

[0067] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0068] An apparatus comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein the computer program, when executed by the processor, implements the steps of the aforementioned optoelectronic chip layout wiring method.

[0069] The fourth aspect of the present invention provides a computer-readable storage medium that can ensure that the waveguide length is equal and the number of bent waveguides is equal during wiring, while simultaneously ensuring that the waveguide occupancy area is minimized and the total waveguide length is minimized.

[0070] A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described optoelectronic chip layout wiring method.

[0071] Compared with the prior art, the advantages of the present invention are as follows:

[0072] In summary, the optoelectronic chip layout routing method of this invention maps the optoelectronic chip layout into a grid and maps the parameterized PCell ports into point coordinates. Using the grid's grid lines as basic units, the center coordinates of the grid lines and the combination of line segments passing through the grid center coordinates are defined as variables. Constraints are set on the paths between PCell ports, and on the points and line segments along the paths. These constraints include non-intersecting paths, path input points, output points, and the existence of line segments. The variables represent the path length, and based on the constraints and the desired equal-length paths, the corresponding variable values ​​are calculated to determine the path planning. This ensures that waveguide lengths are equal, the number of bent waveguides is equal, and simultaneously minimizes the waveguide area and the total waveguide length. Attached Figure Description

[0073] Figure 1 This is a flowchart of the optoelectronic chip layout wiring method in an embodiment of the present invention;

[0074] Figure 2 This is a schematic diagram of variables in an embodiment of the present invention;

[0075] Figure 3 This is a schematic diagram illustrating the effect in an embodiment of the present invention. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0077] See Figure 1 As shown, this embodiment of the invention provides a method for routing a layout of an optoelectronic chip, which includes the following steps:

[0078] S1. Map the optoelectronic chip layout to a grid, and map the parameterized unit PCell port to point coordinates, and map the waveguide that needs to be wired to line segments.

[0079] To address the shortcomings of current automated design tools for optoelectronic chip layouts in waveguide length equalization routing, this invention implements an automated routing mathematical model. This model enables pairwise interconnection between multiple ports and automatically routes multiple waveguides of equal length—waveguides of equal length and the same number of bent waveguides (usually with the same radius of bent waveguides by default). Simultaneously, it minimizes the waveguide area occupied and the total waveguide length, thereby significantly reducing layout drawing time and improving layout accuracy.

[0080] This invention primarily presents a mathematical model for automated routing. The model maps the optoelectronic chip layout to a grid and the PCell ports to point coordinates. First, an N x M (N×M) grid is established, requiring K sets of input points I. k and output point O k K waveguide paths are generated between (1≤k≤K), and the grid consists of segments and vertices.

[0081] S2. Using the grid as the basic unit, define the center coordinates of the grid and the combination of line segments passing through the center coordinates of the grid as variables.

[0082] In this embodiment of the invention, the following variables are defined. All variables are non-negative integers and can only take the value (0, 1). Their specific meanings are as follows: Figure 2 As shown, the coordinates of the center point of all the grids are (i, j).

[0083] Specifically, the following were defined:

[0084] The horizontal segment in the i-th row and j-th column (i.e. and Variables on path-k between two points: If on path-k, then otherwise

[0085] The vertical segment in the i-th row and j-th column (i.e.) and Variables on path-k between two points: If on path-k, then otherwise

[0086] The variable indicating whether the point in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0087] The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then otherwise

[0088] The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then otherwise

[0089] The variable determining whether the left segment of the point in row i and column j is on path k: If both the top and left segments are on path-k, then otherwise

[0090] Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper and right segments are on path-k, then otherwise

[0091] Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then otherwise

[0092] Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then otherwise

[0093] S3. Set the constraints for the paths between PCell ports, the points on the paths, and the line segments. The constraints include the non-intersection condition of the paths, the path input points, the output points, and the existence condition of the line segments.

[0094] Meanwhile, the embodiments of the present invention also set some limiting conditions, specifically:

[0095] (1) For each input point I on path-k k (i,j):

[0096]

[0097] (2) For each output point O on path-k k (i,j):

[0098]

[0099] (3) Paths do not intersect each other, nor do they add additional crossing devices. Each vertex(i,j) can only be on at most one path:

[0100]

[0101] (4) Each segment can only be on one path at most:

[0102]

[0103] (5) If a vertex is on path k, then exactly two of its four segments (up, down, left, and right) are also on path k:

[0104]

[0105] Specifically, for input and output points, only one of the four segments (up, down, left, right) can be on the path.

[0106] (6) If a segment is on path-k, then both of its endpoints are also on path k:

[0107]

[0108] (7) The vertex in the i-th row and j-th column The corresponding position connected to this vertex and Direct decision, Equivalent to have:

[0109]

[0110]

[0111] S4. The path length is represented by the variable, and based on the constraints, the corresponding variable values ​​are calculated according to the desired equal-length path to determine the path planning. Finally, the path planning is mapped to waveguide routing.

[0112] It is worth noting that the equal-length paths to be achieved can be achieved by having a reference path and then setting up several paths based on the reference path; or by ensuring that at least two paths have equal waveguide lengths and equal numbers of bent waveguides without having a reference path, through wiring.

[0113] In this embodiment of the invention, according to the formula:

[0114]

[0115] Calculate the length L of path-k k Where a is the unit length of the grid, and R is the corner radius;

[0116] When path-k1 and path-k2 need to be equal, we have

[0117] When a and R are both 2, that is, equation (1):

[0118]

[0119] To achieve: That is, formula (2):

[0120] It can be known that:

[0121]

[0122] ...

[0123]

[0124] Meanwhile, in order to minimize the area occupied by waveguide wiring, the total length of the paths should be optimized to the shortest possible value, i.e., equation (3):

[0125]

[0126] By solving the problem that satisfies the above constraints and optimizes the waveguide length, one or more sets of... and Minimize the total length of paths; see the results for details. Figure 3 As shown.

[0127] It is understood that, compared to manually drawing the layout, manually calculating the waveguide length and bending number, and constantly modifying and testing the layout, the method in the embodiments of the present invention can quickly and efficiently generate multiple paths that meet the requirements of equal length and equal bending number, and generate them automatically in one go without having to modify the layout multiple times, which greatly saves manpower and time.

[0128] Furthermore, compared to the automatic routing algorithms in existing optoelectronic chip layout automation design tools on the market, which can only generate the shortest path according to the Manhattan algorithm after defining the connection relationship between input and output ports, potentially resulting in waveguide crossings and failing to automatically generate paths of equal length, this patent can automatically generate multiple paths that meet the requirements of equal length and equal number of bends at once, without the need to manually add control points to the path to change the waveguide routing direction, and without the need to modify the layout multiple times.

[0129] Furthermore, compared to manual drawing and other automated design tools for optoelectronic chip layouts, this patent can automatically optimize waveguide path lengths to minimize the area occupied by the layout, avoid wasting layout area, and improve the effective utilization rate.

[0130] In summary, the optoelectronic chip layout routing method of this invention maps the optoelectronic chip layout into a grid and maps the parameterized PCell ports into point coordinates. Using the grid's grid lines as basic units, the center coordinates of the grid lines and the combination of line segments passing through the grid center coordinates are defined as variables. Constraints are set on the paths between PCell ports, and on the points and line segments along the paths. These constraints include non-intersecting paths, path input points, output points, and the existence of line segments. The variables represent the path length, and based on the constraints and the desired equal-length paths, the corresponding variable values ​​are calculated to determine the path planning. This ensures that waveguide lengths are equal, the number of bent waveguides is equal, and simultaneously minimizes the waveguide area and the total waveguide length.

[0131] Meanwhile, embodiments of the present invention also provide an optoelectronic chip layout wiring device, which includes a mapping module, a configuration module and a calculation module.

[0132] The mapping module maps the optoelectronic chip layout into a grid, the parameterized PCell ports into point coordinates, and the waveguides to be routed into line segments. The configuration module uses the grid's grid lines as basic units and defines the grid center coordinates and the combination of line segments passing through the grid center coordinates as variables. The calculation module sets the constraints on the paths between PCell ports, the points on the paths, and the line segments. The constraints include paths not intersecting, path input points, output points, and the existence of line segments. The calculation module also uses the variables to represent the path length and, based on the constraints, calculates the corresponding variable values ​​according to the desired equal-length paths to determine the path planning. Finally, the path planning is mapped to waveguide routing.

[0133] In some embodiments, the configuration module uses a grid of squares as the basic unit, defining the center coordinates of the squares and the combination of line segments passing through the center coordinates of the squares as variables, including:

[0134] Set the center coordinates of the grid to (i, j);

[0135] And set the value to either 0 or 1:

[0136] The variable of the horizontal segment in the i-th row and j-th column on path-k: If on path-k, then otherwise

[0137] The variable of the vertical segment in the i-th row and j-th column on path-k: If on path-k, then otherwise

[0138] The variable indicating whether the point in the i-th row and j-th column is on path-k: If on path-k, then otherwise

[0139] The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then otherwise

[0140] The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then otherwise

[0141] The variable determining whether the left segment of the point in row i and column j is on path k: If both the top and left segments are on path-k, then otherwise

[0142] Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper and right segments are on path-k, then otherwise

[0143] Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then otherwise

[0144] Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then otherwise

[0145] In some embodiments, the computing module sets constraints on paths between PCell ports, points on those paths, and line segments. These constraints include the non-intersection of paths, the existence of path input points, output points, and line segments, including:

[0146] Restrict input point I on path-k k (i,j) satisfies Output point O k (i,j) satisfies Through the formula: The paths must not intersect;

[0147] Through the formula: Each segment can only be on one path at most;

[0148] Through the formula: A point restricted to path-k has exactly two of its four segments (up, down, left, and right) on path-k;

[0149] Through the formula: The two endpoints of a segment restricted to path-k are also on path-k;

[0150] Through the formula:

[0151]

[0152] Restrict the points in the i-th row and j-th column

[0153] In some embodiments, the calculation module calculates according to the formula:

[0154]

[0155] Calculate the length L of path-k k Where a is the unit length of the grid, and R is the corner radius;

[0156] When path-k1 and path-k2 need to be equal, we have

[0157] In some embodiments, the calculation module also uses the formula min∑ k L k Optimize the path to minimize the total length of all paths.

[0158] This invention also provides an apparatus comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein the computer program, when executed by the processor, implements the steps of the above-described optoelectronic chip layout wiring method.

[0159] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0160] This invention also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described optoelectronic chip layout wiring method.

[0161] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer-readable storage media (or non-transitory media) and communication media (or transient media).

[0162] As is known to those skilled in the art, the term computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0163] For example, the computer-readable storage medium may be an internal storage unit of the electronic device described in the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., provided on the electronic device.

[0164] The above are merely specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the claims.

Claims

1. A method for routing layouts of an optoelectronic chip, characterized in that, The method includes the following steps: The optoelectronic chip layout is mapped into a grid, and the parameterized unit PCell port is mapped into point coordinates. The waveguide that needs to be wired is mapped into line segments. Using the grid as the basic unit, the center coordinates of the grid and the combination of line segments passing through the center coordinates of the grid are defined as variables; Set constraints on the paths between PCell ports, the points and line segments on the paths, and the constraints include the path non-intersection condition, the path input point, the output point, and the existence condition of the line segments. The variable is used to represent the length of the path, and based on the constraints, the corresponding variable values ​​are calculated according to the desired equal-length path to determine the path planning. Finally, the path planning is mapped to waveguide routing. The method uses the grid's grid lines as the basic unit, defining the grid center coordinates and the combination of line segments passing through the grid center coordinates as variables, including: Set the center coordinates of the grid as (i, j); And set the value to either 0 or 1: The variable of the horizontal segment in the i-th row and j-th column on path-k: If it is on path-k, then ,otherwise ; The variable of the vertical segment in the i-th row and j-th column on path-k: If it is on path-k, then ,otherwise ; The variable indicating whether the point in the i-th row and j-th column is on path-k: If it is on path-k, then ,otherwise ; The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then ,otherwise ; The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then ;otherwise ; The variable determining whether the left segment of the point in row i and column j is on path k: If both the top left and bottom segments are on path-k, then ;otherwise ; Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper right and lower right segments are on path-k, then ;otherwise ; Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then ;otherwise ; Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then ;otherwise ; The constraints on the paths between PCell ports, the points on those paths, and the line segments along those paths include the following: paths do not intersect, path input points, output points, and the existence of line segments. Restrict input points on path-k satisfy Output point satisfy ; Through the formula: The paths are restricted from intersecting; Through the formula: Each segment can only be on one path at most; Through the formula: For a point on path-k, there must be exactly two of its four segments (up, down, left, and right) on path-k. Through the formula: The two endpoints of the segment restricted to path-k are also on path-k; Through the formula: ； 2. The optoelectronic chip layout wiring method as described in claim 1, characterized in that: According to the formula: Calculate the length L of path-k k Where a is the unit length of the grid, and R is the corner radius; When path-k1 and path-k2 need to be equal, we have .

3. The optoelectronic chip layout wiring method as described in claim 2, characterized in that, Also includes: Through formula Optimize the path to minimize the total length of all paths.

4. A layout wiring device for an optoelectronic chip, characterized in that, include: The mapping module is used to map the optoelectronic chip layout into a grid, map the parameterized unit PCell port into point coordinates, and map the waveguide that needs to be wired into line segments. The configuration module is used to define the center coordinates of the grid and the combination of line segments passing through the center coordinates of the grid as variables, using the grid as the basic unit. The calculation module is used to set the constraints of the path between PCell ports, the points and line segments on the path, the constraints of the path not intersecting, the path input point, the output point and the existence of line segments, and the calculation module is also used to use the variables to represent the length of the path, and based on the constraints, calculate the corresponding variable values ​​according to the equal-length path to be achieved, so as to determine the path planning, and finally map the path planning to the waveguide trace. The configuration module uses the grid's grid lines as the basic unit, defining the grid center coordinates and the line segment combinations passing through the grid center coordinates as variables, including: Set the center coordinates of the grid as (i, j); And set the value to either 0 or 1: The variable of the horizontal segment in the i-th row and j-th column on path-k: If it is on path-k, then ,otherwise ; The variable of the vertical segment in the i-th row and j-th column on path-k: If it is on path-k, then ,otherwise ; The variable indicating whether the point in the i-th row and j-th column is on path-k: If it is on path-k, then ,otherwise ; The variable that determines whether the upper and lower segments of the point in the i-th row and j-th column are on path-k: If both the upper and lower segments are on path-k, then ,otherwise ; The variable determining whether the left and right segments of the point in the i-th row and j-th column lie on path-k: If both the left and right segments are on path-k, then ;otherwise ; The variable determining whether the left segment of the point in row i and column j is on path k: If both the top left and bottom segments are on path-k, then ;otherwise ; Whether the upper right segment of the point in the i-th row and j-th column is on path-k: If both the upper right and lower right segments are on path-k, then ;otherwise ; Whether the lower left segment of the point in the i-th row and j-th column is on path-k: If both the lower left and upper right segments are on path-k, then ;otherwise ; Whether the lower right segment of the point in the i-th row and j-th column is on path-k: If both the lower right and lower right segments are on path-k, then ;otherwise ; The computing module sets constraints on the paths between PCell ports, the points on those paths, and the line segments along those paths. These constraints include the following: paths do not intersect, path input points, output points, and the existence of line segments. Restrict input points on path-k satisfy Output point satisfy ; Through the formula: The paths are restricted from intersecting; Through the formula: Each segment can only be on one path at most; Through the formula: For a point on path-k, there must be exactly two of its four segments (up, down, left, and right) on path-k. Through the formula: The two endpoints of the segment restricted to path-k are also on path-k; Through the formula:

5. A device, characterized in that, The device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of a photoelectric chip layout wiring method as described in any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of a photoelectric chip layout wiring method as described in any one of claims 1 to 3.

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